A gate-level circuit reliability critical path identification method

Abstract

The application relates to a gate circuit reliability critical path identification method, which comprises the following steps: S1, constructing a circuit integrity chain table to identify all paths existing in the circuit; S2, constructing a local probability matrix based on input probability distribution and output probability distribution; S3, constructing a circuit adjacency matrix; S4, obtaining a local adjacency probability matrix; S5, obtaining a global probability matrix; S6, reading all paths to obtain a reliability value matrix of each path, sorting the paths according to the numerical value of each row of the reliability value matrix, and obtaining a reliability critical path. Compared with the prior art, the application has the advantages of reducing the complexity of calculation under the premise of ensuring the evaluation accuracy.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of integrated circuit reliability evaluation, in particular to a gate-level circuit reliability critical path identification method. BACKGROUND

[0002] Although the size of Complementary Metal Oxide Semiconductor (CMOS) is continuously reduced, the performance of the circuit is improved, but the introduction of new nanometer process technology in integrated circuit also makes the static and dynamic parameters of the device more susceptible to external factors, such as cosmic rays, atmospheric neutrons and alpha particles, which significantly increases the soft error rate of the circuit, thereby reducing the reliability of the circuit. Since some input vectors have a high frequency of occurrence in the input vector set used in some specific application environment, under these input vectors, the signals of some gates on some paths in the circuit will frequently flip, which directly affects the probability of correct output of the circuit signal. The traditional method and tool mainly find the critical path of the circuit from the perspective of delay and power consumption, although in recent years some research works have tried to locate the critical nodes according to the reliability analysis, but with the gradual increase of the circuit size, especially under the specific input vectors in the practical application scene, due to the relatively scattered position of the critical nodes, the existing technology cannot efficiently identify the critical nodes to form the critical path, which is not conducive to fault troubleshooting and hardening, and also causes a lot of waste of overhead. SUMMARY

[0003] The purpose of the present application is to overcome the defects of the prior art and provide a gate-level circuit reliability critical path identification method, which realizes the fast identification of the combinational gate-level circuit reliability critical path based on matrix operation, reduces the complexity of calculation under the premise of ensuring the evaluation accuracy.

[0004] The purpose of the present application can be achieved by the following technical solutions:

[0005] A gate-level circuit reliability critical path identification method, comprising the following steps:

[0006] S1, parse the netlist, extract the basic gate information of the circuit, build a circuit integrity linked list based on the basic gate information, identify all paths existing in the circuit, and generate input vectors, calculate the output signals of each gate facing the input vectors, and store the output signals in the circuit integrity linked list;

[0007] S2, calculate the input probability distribution and output signal change probability of each gate based on the circuit integrity linked list, and build a local probability matrix based on the input probability distribution and output probability distribution;

[0008] S3, constructing a circuit adjacency matrix based on the input types of each gate in the circuit integrity linked list;

[0009] S4, multiplying the local probability matrix and the circuit adjacency matrix to obtain a local adjacency probability matrix;

[0010] S5, obtaining the local adjacency probability corresponding to each gate in the local adjacency probability matrix, and obtaining a global probability matrix based on the local adjacency probability;

[0011] S6, reading all paths, constructing a path adjacency matrix based on all paths, multiplying the path adjacency matrix and the global probability matrix to obtain a reliability value matrix of each path, and sorting each path according to the numerical value of each row of the reliability value matrix to obtain a reliability critical path.

[0012] Further, the specific steps of S1 include:

[0013] S1.1, parsing the netlist, extracting the basic gate information of the circuit, and constructing a circuit integrity linked list based on the basic gate information, wherein the circuit integrity linked list stores the number of all basic gates, the types of inputs of each gate, and the input and output signal values of each gate;

[0014] S1.2, identifying all paths existing in the circuit through depth-first traversal of the graph;

[0015] S1.3, generating an input vector with uniform non-Bernoulli characteristics;

[0016] S1.4, based on the input vector, calculating the output signal of each gate based on the sine optimization algorithm, and storing the output signal in the circuit integrity linked list.

[0017] Further, the specific steps of S2 include:

[0018] S2.1, constructing a local probability matrix with a size of GN×1, wherein GN is the number of all basic gates contained in the circuit integrity linked list, initializing the local probability matrix to 0, and setting the first iteration variable i1 to 1;

[0019] S2.2, reading the set of input and output signal values of the i1th gate from the circuit integrity linked list;

[0020] S2.3, calculating the input probability distribution of the i1th gate based on the set of inputs of the i1th gate;

[0021] S2.4, reading the type of the i1th gate from the circuit integrity linked list, and analyzing the output signal change probability of the gate under the input probability distribution of S2.3;

[0022] S2.5, calculate the local probability of the ith gate based on the output signal change probability of S2.4 and the input probability distribution of S2.3, and assign the local probability to the element of the ith1 row and the first column of the local probability matrix, and update the matrix;

[0023] S2.6, determine whether all gates have been traversed, if yes, obtain the updated local probability matrix, execute S2.7, if no, increase the value of the first iteration variable i1 by 1, and return to S2.3;

[0024] S2.7, diagonalize and expand the updated local probability matrix obtained in S2.6 into a diagonal matrix with a size of GNxGN;

[0025] S2.8, output the local probability matrix after diagonalization and expansion obtained in S2.7.

[0026] Further, the specific steps of S3 include:

[0027] S3.1, create a circuit adjacency matrix with a size of GNxGN, and initialize the circuit adjacency matrix to 0, and set the second iteration variable i2 to 1;

[0028] S3.2, read the input j of the ith2 gate from the circuit integrity chain table;

[0029] S3.3, if the type of input j is spare or gain, continue to read the input k of input j, k is the predecessor information of j, and assign 1 to the kth row and the ith2 element of the circuit adjacency matrix, otherwise assign 1 to the jth row and the ith2 element of the circuit adjacency matrix, and update the matrix;

[0030] S3.4, determine whether all gates have been traversed, if yes, obtain the updated circuit adjacency matrix, execute S3.5, if no, increase the value of the second iteration variable i2 by 1, and return to S3.2;

[0031] S3.5, output the updated circuit adjacency matrix obtained in S3.4.

[0032] Further, the specific steps of S5 are:

[0033] S5.1, create a global probability matrix with a size of GNx1, and initialize the global probability matrix to 0, and set the third iteration variable i3 to GN;

[0034] S5.2, read the set of gates directly connected to the original output terminal of the circuit from the circuit integrity chain table;

[0035] S5.3, assign 1 to the corresponding position of the global probability matrix based on the set of gates directly connected to the original output terminal of the circuit;

[0036] S5.4, reading the local adjacency probability value of the ith3 gate from the local adjacency probability matrix;

[0037] S5.5, multiplying the local adjacency probability value of the ith3 gate with the global probability matrix obtained in S5.3 to obtain a global probability;

[0038] S5.6, assigning the global probability in S5.5 to the ith3 row of the global probability matrix to update the global probability matrix;

[0039] S5.7, judging whether all the gates have been traversed in reverse, if yes, obtaining the updated global probability matrix, executing S5.8, if no, reducing the value of the third iteration variable i3 by 1 and returning to S5.4;

[0040] S5.8, outputting the updated global probability matrix obtained in S5.7.

[0041] Further, the specific steps of S6 are as follows:

[0042] S6.1, reading all the paths in S1.2 and counting the number pn of all the paths;

[0043] S6.2, constructing a path adjacency matrix with a size of pn x GN and initializing the path adjacency matrix to 0, and setting the fourth iteration variable i4 to 1;

[0044] S6.3, assigning values to the path adjacency matrix according to all the paths, for the ith’ path passing through the j’ gate, the element of the ith’ row and the j’ column of the path adjacency matrix is assigned to 1, and the path adjacency matrix is updated;

[0045] S6.4, judging whether all the paths have been traversed, i.e. whether i4≥pn is satisfied, if yes, obtaining the updated path adjacency matrix, executing S6.5, if no, increasing the value of the fourth iteration variable i4 by 1 and returning to S6.3;

[0046] S6.5, constructing a reliability value matrix of each path with a size of pn x 1 and initializing the reliability value matrix to 0, multiplying the path adjacency matrix and the global probability matrix, and assigning the multiplication result to the reliability value matrix to obtain the updated reliability value matrix;

[0047] S6.6, sorting each path according to the numerical value of each row of the reliability value matrix to obtain the reliability critical path.

[0048] Further, the expression of the local probability of the ith1 gate is as follows:

[0049]

[0050] wherein, Local probability of the ith1 gate, Input quantity of the ith1 gate in the circuit integrity chain table, Input probability distribution of the ith1 gate, Output signal change probability of the ith1 gate, j1 is a serial number, and the expression of j1 is:

[0051] Further, in S2.6, whether all gates are traversed is determined by judging whether i1≥GN is established or not, if yes, all gates are traversed, otherwise, all gates are not traversed, in S3.4, whether all gates are traversed is determined by judging whether i2≥GN is established or not, if yes, all gates are traversed, otherwise, all gates are not traversed.

[0052] Further, whether all gates are traversed in reverse is determined by judging whether i3<1 is established or not, if yes, all gates are traversed in reverse, otherwise, all gates are not traversed in reverse.

[0053] Further, the size of the local adjacency probability matrix is GN×GN.

[0054] Compared with the prior art, the present application has the following beneficial effects:

[0055] The present application constructs the local adjacency probability matrix reflecting the local reliability of each gate and the global probability matrix reflecting the influence degree of each gate on the overall reliability of the circuit, on the basis of which, each path and the corresponding reliability can be quickly and accurately identified through matrix operation, compared with the prior art of positioning according to reliability analysis, the present application adopts matrix calculation, reduces the complexity of calculation under the premise of ensuring the evaluation accuracy, and is convenient for application in identification of the reliability critical path of large-scale integrated circuits. BRIEF DESCRIPTION OF DRAWINGS

[0056] Figure 1 The flow chart of the present application;

[0057] Figure 2 The flow chart of constructing the circuit integrity chain table for storing the circuit information after analyzing the net list of the present application. DETAILED DESCRIPTION

[0058] The present application will be described in detail below in combination with the drawings and specific embodiments. The present embodiment is implemented on the premise of the technical scheme of the present application, detailed implementation modes and specific operation processes are given, but the protection scope of the present application is not limited to the following embodiments.

[0059] The application provides a gate-level circuit reliability critical path identification method, which is mainly characterized by constructing a plurality of matrix models by means of the front and back positions of basic gates in an integrated circuit and the probability of correct signal transmission, and realizing fast identification of a combinational gate-level circuit reliability critical path based on matrix operation, thereby reducing the complexity of calculation under the premise of ensuring the evaluation accuracy, expanding the application range of the method, and facilitating application in identification of a large-scale integrated circuit reliability critical path.

[0060] The technical concept of the application is specifically as follows: firstly, a netlist is read and parsed, and original input ends, original output ends and basic gates of a circuit are stored in a circuit integrity linked list; secondly, all paths in the circuit are identified through depth-first traversal; then, a circuit local probability matrix and a circuit adjacency matrix are constructed and combined into a circuit adjacency probability matrix; next, a circuit global probability matrix is constructed and updated in real time through reverse traversal of all nodes; finally, the global probability matrix is multiplied by the path adjacency matrix to obtain a path probability matrix, all paths are sorted according to the numerical value, and the reliability critical path is returned.

[0061] The flowchart of the application is shown in Figure 1 The circuit integrity linked list construction flowchart of the application after parsing the netlist and storing the circuit information is shown in Figure 2

[0062] The gate-level circuit reliability critical path identification method provided by the application comprises the following steps:

[0063] Step 1: netlist parsing and related preprocessing operation

[0064] The specific steps of step 1 include:

[0065] 1.1) parse the netlist, extract the basic gate information of the circuit, and store the original input ends, original output ends, line numbers of each basic gate and front and back connection relationships and the like of the circuit through construction of a circuit integrity linked list Lc; the circuit integrity linked list Lc also stores the number of all basic gates, the types of inputs of each gate and the input and output signal values of each gate.

[0066] 1.2) identify all paths all_path in the circuit through depth-first traversal of the graph;

[0067] 1.3) generate an input vector input_vectors with uniform non-Bernoulli characteristics;

[0068] 1.4) calculate the output signal values of each gate based on the sine-cosine optimization algorithm SCA for the input vector input_vectors. The output signals are stored in the circuit integrity linked list.

[0069] ​Step 2: Calculate the input probability of each gate and construct the local probability matrix

[0070] 2.1) Construct a local probability matrix LPM with size GN x 1, GN is the number of all basic gates contained in the integrity chain table Lc, initialize LPM = 0, the first iteration variable il = 1;

[0071] 2.2) Read the input and output signal value set of the ilth gate from the integrity chain table Lc, respectively Input il, Output il;

[0072] 2.3) Calculate the input probability distribution of the ilth gate Input il is the number of input terminals of the ilth gate contained in Lc;

[0073] 2.4) Read the type of the ilth gate from Lc, analyze the output signal change probability under the input signal equiprobable distribution

[0074] 2.5) Calculate the local probability LP of the ilth gate using formula (1) i , and assign it to the local probability matrix

[0075]

[0076] 2.6) Judge whether all gates have been traversed, that is, il ≥ GN, if yes, go to 2.7), otherwise execute il = il + 1 and go to 2.3);

[0077] 2.7) Diagonalize LPM to a diagonal matrix with size GN x GN;

[0078] 2.8) Output LPM.

[0079] In S2, since the types of gates in the gate-level circuit are different, usually the input of a gate is not only one, so it is necessary to count the change probability of all inputs respectively to form the input probability distribution, and the output is usually one, so it is only necessary to count the change probability of this one output.

[0080] Step 3: Construct the circuit adjacency matrix.

[0081] The specific steps of S3 include:

[0082] 3.1) Create an adjacency matrix AM with size GN x GN, and initialize AM = 0, the second iteration variable i2 = 1;

[0083] 3.2) Read the input j of the i2th gate from Lc;

[0084] 3.3) If the type of input is "from" (backup) or "buff" (gain), continue to read the input k of j, and let k, i2 = 1, otherwise let AM j,i2 = 1;

[0085] 3.4) Determine whether all gates have been traversed, i.e. i2 > GN, if yes, go to 3.5), otherwise execute i2 = i2 + 1 and go to 3.2);

[0086] 3.5) Output AM.

[0087] In s3.2, the loop variable is i2, which indicates the i2th gate is traversed, and the purpose is to build the connection relationship of the gate in the adjacency matrix AM. Since the input has been confirmed as k, the kth row and ith column of AM is 1, indicating that gate k is connected to i. In 3.3, k is the predecessor information of j, and k, i2 = 1 means assigning 1 to the kth row and i2th element of the adjacency matrix.

[0088] Step 4: Synthesize the local adjacency probability matrix, multiply LPM and AM matrix according to formula (2) to get the local adjacency probability matrix LAPM of size GN x GN:

[0089] LAPM = LPM x AM (2)

[0090] Step 5: Construct the global probability matrix.

[0091] The specific steps of step 5 include:

[0092] 5.1) Create a global probability matrix GPM of size GN x 1, initialize GPM = 0, and the third iteration variable i3 = GN;

[0093] 5.2) Read the set of gates directly connected to the original output terminal of the circuit Out_g from Lc;

[0094] 5.3) Assign 1 to the corresponding position of GPM according to formula (3):

[0095] GPM Out_g(k) = 1, k = 1, 2, 3,..., length(Out_g) (3)

[0096] 5.4) Read the local adjacency probability value of the i3th gate from LAPM LAPM(i3, :);

[0097] 5.5) Multiply the local probability matrix corresponding to the i3th gate with the current global probability matrix according to formula (4) to get the global probability gp:

[0098] gp = LAPM(i3, :) x GPM (4)

[0099] 5.6) update the value corresponding to the ith gate in the global probability matrix, GPM i3 = gp;

[0100] 5.7) determine whether all gates have been traversed in reverse, i.e. i3 < 1, if yes, go to 5.8), otherwise execute i3 = i3 - 1 and go to 5.4);

[0101] 5.8) output GPM.

[0102] Step 6: construct a path probability matrix and return RCP

[0103] The specific steps of step 6 include:

[0104] 6.1) read the path identification result all_paths in step 1.2), and count the total number of paths pn = size(all_paths);

[0105] 6.2) construct a path adjacency matrix PAM with a size of pn x GN, and initialize PAM = 0, and a fourth iteration variable i4 = 1;

[0106] 6.3) assign values to PAM according to all_paths, PAM i，j = 1 indicates that the ith path passes through gate j';

[0107] 6.4) determine whether all paths have been traversed, i.e. i4 ≥ pn, if yes, go to 6.5), otherwise execute i4 = i4 + 1 and go to 6.3);

[0108] 6.5) construct a path probability matrix PPM with a size of pn x 1, and initialize PPM = 0;

[0109] 6.6) calculate the reliability value of each path according to formula (5):

[0110] PPM = PAM x GPM (5)

[0111] 6.7) sort the paths according to the numerical value of each row in the PPM matrix, and return the reliability critical path RCP.

[0112] The present application proposes the above method, which not only helps circuit designers to timely master the reliability level of the designed product in the specified application environment and the sensitivity of each path in the circuit design stage, so as to make reasonable choices and decisions, and to reduce costs as much as possible while improving the overall reliability of the circuit, but also helps to provide decision-making for fault troubleshooting in the product operation and maintenance stage.

[0113] The preferred embodiments of the present application have been described above in detail. It should be understood that modifications and variations to the present application can be affected by those skilled in the art without departing from the scope of the application. Accordingly, it is intended that all possible modifications and alterations be included within the scope of the present application as defined by the following claims.

Claims

1. A method for identifying critical paths to gate-level circuit reliability, characterized in that, The method comprises the following steps: S1, parsing the netlist, extracting the basic gate information of the circuit, constructing the circuit integrity chain table based on the basic gate information, identifying all paths existing in the circuit, and generating an input vector, calculating the output signal of each gate facing the input vector, and storing the output signal in the circuit integrity chain table; S2, calculating the input probability distribution and output signal change probability of each gate based on the circuit integrity chain table, and constructing a local probability matrix based on the input probability distribution and output probability distribution; S3, constructing a circuit adjacency matrix based on the input type of each gate in the circuit integrity chain table; S4, multiplying the local probability matrix and the circuit adjacency matrix to obtain a local adjacency probability matrix; S5, obtaining the local adjacency probability corresponding to each gate in the local adjacency probability matrix, and obtaining a global probability matrix based on the local adjacency probability; S6, reading all paths, constructing a path adjacency matrix based on all paths, multiplying the path adjacency matrix and the global probability matrix to obtain a reliable value matrix of each path, and sorting the paths according to the numerical value of each row of the reliable value matrix to obtain a reliability critical path.

2. The gate-level circuit reliability critical path identification method of claim 1, wherein, The specific steps of S1 include: S1.1, parsing the netlist, extracting the basic gate information of the circuit, constructing the circuit integrity chain table based on the basic gate information, and storing the number of all basic gates, the type of input of each gate, and the input and output signal value of each gate in the circuit integrity chain table; S1.2, identifying all paths existing in the circuit through depth-first traversal of the graph; S1.3, generating an input vector with uniform non-Bernoulli characteristics; S1.4, calculating the output signal of each gate based on the sine optimization algorithm facing the input vector, and storing the output signal in the circuit integrity chain table.

3. The gate-level circuit reliability critical path identification method of claim 2, wherein, The specific steps of S2 include: S2.1, constructing a local probability matrix with a size of GN×1, GN being the number of all basic gates contained in the circuit integrity chain table, initializing the local probability matrix to 0, and setting the first iteration variable i1 to 1; S2.2, reading the set of input and output signal values of the i1th gate from the circuit integrity chain table; S2.3, calculating the input probability distribution of the i1th gate based on the set of inputs of the i1th gate; S2.4, reading the type of the i1th gate from the circuit integrity chain table, and analyzing the output signal change probability of the gate under the input probability distribution of S2.3; S2.5, calculating the local probability of the i1th gate based on the output signal change probability of S2.4 and the input probability distribution of S2.3, assigning the local probability to the element of the first column of the i1th row of the local probability matrix, and updating the matrix; S2.6, determining whether all gates have been traversed, if yes, obtaining the updated local probability matrix, executing S2.7, if not, adding 1 to the value of the first iteration variable i1, and returning to S2.3; S2.7, diagonalizing the updated local probability matrix obtained in S2.6 to expand it into a diagonal matrix with a size of GN×GN; S2.8, outputting the local probability matrix after the matrix diagonalization expansion obtained in S2.

7.

4. The gate-level circuit reliability critical path identification method of claim 3, wherein, The specific steps of S3 include: S3.1, create a circuit adjacency matrix with size GN*GN, and initialize the circuit adjacency matrix to 0, and set the second iteration variable i2 to 1; S3.2, read the input j of the i2th gate from the circuit integrity chain table; S3.3, if the type of input j is spare or gain, continue to read the input k of input j, k is the predecessor information of j, and assign 1 to the kth row, the i2th element of the circuit adjacency matrix, otherwise assign 1 to the jth row, the i2th element of the circuit adjacency matrix, and update the matrix; S3.4, determine whether all gates have been traversed, if so, obtain the updated circuit adjacency matrix, execute S3.5, if not, add 1 to the value of the second iteration variable i2, and return to S3.2; S3.5, output the updated circuit adjacency matrix obtained in S3.

4.

5. The gate-level circuit reliability critical path identification method of claim 4, wherein, The specific steps of S5 are: S5.1, create a global probability matrix with size GN*1, and initialize the global probability matrix to 0, and set the third iteration variable i3 to GN; S5.2, read the set of gates directly connected to the original output terminal of the circuit from the circuit integrity chain table; S5.3, assign 1 to the corresponding position of the global probability matrix based on the set of gates directly connected to the original output terminal of the circuit; S5.4, read the local adjacency probability value of the i3th gate from the local adjacency probability matrix; S5.5, multiply the local adjacency probability value of the i3th gate with the global probability matrix obtained in S5.3 to obtain the global probability; S5.6, assign the global probability in S5.5 to the i3th row of the global probability matrix to update the global probability matrix; S5.7, determine whether all gates have been traversed in reverse, if so, obtain the updated global probability matrix, execute S5.8, if not, subtract 1 from the value of the third iteration variable i3, and return to S5.4; S5.8, output the updated global probability matrix obtained in S5.

7.

6. The gate-level circuit reliability critical path identification method of claim 3, wherein, The specific steps of S6 are: S6.1, read all paths in S1.2, and count the number of all paths pn; S6.2, construct a path adjacency matrix with size pn*GN, and initialize the path adjacency matrix to 0, and set the fourth iteration variable i4 to 1; S6.3, assign values to the path adjacency matrix according to all paths, for the i'th path passing through gate j', the element of the i'th row and j'th column of the path adjacency matrix is assigned to 1, and the path adjacency matrix is updated; S6.4, determine whether all paths have been traversed, that is, whether i4≥pn is satisfied, if so, obtain the updated path adjacency matrix, execute S6.5, if not, add 1 to the value of the fourth iteration variable i4, and return to S6.3; S6.5, construct a reliability value matrix of each path with size pn*1, and initialize the reliability value matrix to 0, multiply the path adjacency matrix and the global probability matrix, and assign the multiplication result to the reliability value matrix to obtain the updated reliability value matrix; S6.6, sort each path according to the numerical value of each row of the reliability value matrix to obtain the reliability critical path.

7. The gate-level circuit reliability critical path identification method of claim 2, wherein, The expression of the local probability of the i1th gate is: wherein, is the local probability of the ith gate, is the number of inputs of the ith gate in the circuit integrity chain, is the input probability distribution of the ith gate, is the output signal change probability of the ith gate, j1 is a serial number, and the expression of j1 is:

8. The gate-level circuit reliability critical path identification method of claim 4, wherein, In S2.6, judging whether all the gates have been traversed is specifically judging whether i1≥GN is true, if yes, all the gates have been traversed, otherwise, all the gates have not been traversed, in S3.4, judging whether all the gates have been traversed is specifically judging whether i2≥GN is true, if yes, all the gates have been traversed, otherwise, all the gates have not been traversed.

9. The gate-level circuit reliability critical path identification method of claim 5, wherein, Judging whether all the gates have been traversed in reverse is specifically judging whether i3<1 is true, if yes, all the gates have been traversed in reverse, otherwise, all the gates have not been traversed in reverse.

10. The gate-level circuit reliability critical path identification method of claim 3, wherein, The size of the local adjacency probability matrix is GN×GN.

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