Solid-state imaging device and distance measuring device

Abstract

The solid-state imaging device has a plurality of pixel circuits (1) arranged in a matrix, wherein the pixel circuit (1) comprises: a photodiode (APD); a first charge storage unit (C1) for storing charge; a floating diffusion region (FD) for storing charge; a second charge storage unit (C2) for storing charge; a first transfer transistor (2) for transferring charge from the photodiode (APD) to the first charge storage unit (C1); a second transfer transistor (3) for transferring charge from the first charge storage unit (C1) to the floating diffusion region (FD); a first reset transistor (4) for resetting the floating diffusion region (FD); and an accumulation transistor (7) for accumulating charge of the floating diffusion region (FD) in the second charge storage unit (C2), wherein the capacitance of the first charge storage unit (C1) is larger than the capacitance of the floating diffusion region (FD), and the capacitance of the second charge storage unit (C2) is larger than the capacitance of the floating diffusion region (FD).

Description

Technical Field

[0001] The present invention relates to a solid-state imaging device and a distance measuring device. Background Art

[0002] Patent Document 1 discloses a solid-state imaging element including pixels having avalanche photodiodes (hereinafter referred to as APDs), which detects weak light.

[0003] Patent Document 2 discloses a MOS-type solid-state imaging device having a global shutter function.

[0004] Patent document 3 discloses a solid-state imaging element having a photoelectric conversion element and a signal output circuit, wherein the photoelectric conversion element includes a pair of electrodes stacked above a semiconductor substrate and a photoelectric conversion layer sandwiched by the pair of electrodes, and the signal output circuit outputs a signal corresponding to the charge generated in the photoelectric conversion layer.

[0005] (Prior art literature)

[0006] (Patent Document)

[0007] Patent Document 1: International Publication No. 2018 / 216400

[0008] Patent Document 2: Japanese Patent Application Laid-Open No. 2008-283615

[0009] Patent Document 3: Japanese Patent Application Laid-Open No. 2009-147067

[0010] However, the conventional technology has a problem in that a through current may flow through the photodiode due to the generation of charge, and the bias voltage of the photodiode is affected by the through current, causing the operation to become unstable. Summary of the Invention

[0011] An object of the present disclosure is to provide a solid-state imaging device and a distance measuring device that suppress a through-current of a photodiode and stabilize the operation.

[0012] One embodiment of the present disclosure relates to a solid-state imaging device having a plurality of pixel circuits arranged in a matrix, wherein the pixel circuits include: a photodiode; a first charge storage unit for storing charge; a floating diffusion region for storing charge; a second charge storage unit for storing charge; a first transfer transistor for transferring charge from the photodiode to the first charge storage unit; a second transfer transistor for transferring charge from the first charge storage unit to the floating diffusion region; a first reset transistor for resetting the floating diffusion region; and an accumulation transistor for accumulating the charge of the floating diffusion region in the second charge storage unit, wherein the capacitance of the first charge storage unit is greater than that of the floating diffusion region, and the capacitance of the second charge storage unit is greater than that of the floating diffusion region.

[0013] A distance measuring device according to one aspect of the present disclosure includes the above-mentioned solid-state imaging device.

[0014] Furthermore, these general or specific aspects may be implemented by a system, a method, an integrated circuit, or by any combination of a system, a method, an integrated circuit, a computer program, and a recording medium.

[0015] According to the solid-state imaging device and the distance measuring device of the present disclosure, it is possible to suppress the through current of the photodiode and achieve stable operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 This is a diagram showing an example of a pixel circuit in Embodiment 1.

[0017] Figure 2 This is a block diagram showing a configuration example of a solid-state imaging device in Embodiment 1.

[0018] Figure 3 This is a timing chart showing a driving example of the pixel circuit in the first embodiment.

[0019] Figure 4 1 is an explanatory diagram showing the operation of the potential and charge of each part of the pixel circuit in Embodiment 1.

[0020] Figure 5 This is a diagram showing a circuit example of a pixel circuit in the second embodiment.

[0021] Figure 6 This is a timing chart showing a driving example of the pixel circuit in the second embodiment.

[0022] Figure 7 This is an operation explanatory diagram showing an example of potentials of various parts of the pixel circuit in the second embodiment.

[0023] Figure 8 This is a block diagram showing a configuration example of a distance measuring device in a third embodiment.

[0024] Figure 9 1 is a diagram showing a pixel circuit as a comparative example in which a through current may occur.

[0025] Figure 10 1 is a timing chart showing an operation example of a pixel circuit according to a comparative example during one frame period. DETAILED DESCRIPTION

[0026] (Insights that form the basis of this disclosure)

[0027] The present inventors have discovered a problem with the solid-state imaging device described in the background art, namely, the possibility of unstable operation due to through-current. Regarding this problem, a pixel circuit example as a comparative example will be described.

[0028] Figure 9 1 is a diagram showing a pixel circuit 100 as a comparative example in which a through current may occur. Figure 10 1 is a timing chart showing an operation example of the pixel circuit 100 of the comparative example in one frame period.

[0029] exist Figure 9 The photodiode APD has two operating modes: a Geiger multiplication mode with avalanche multiplication and a linear multiplication mode in which charge is generated in proportion to the amount of incident light. To operate in the Geiger multiplication mode, a reverse bias voltage VSUB (e.g., 25V) is applied to the anode of the photodiode APD.

[0030] The reset transistor 102 is a transistor for resetting the charge accumulated in the cathode of the photodiode APD in accordance with the reset control signal OVF.

[0031] The transfer transistor 103 is a transistor for transferring the charge accumulated in the cathode of the photodiode APD to the floating diffusion region FD in accordance with a transfer control signal TRN.

[0032] The reset transistor 104 is a transistor for resetting the charge accumulated in the floating diffusion region FD in response to a reset control signal RST.

[0033] The amplifier transistor 105 is a transistor for converting the amount of charge accumulated in the floating diffusion region FD into a voltage.

[0034] The selection transistor 106 outputs the voltage converted by the amplifier transistor 105 to the transistor of the vertical signal line 109 while the selection control signal SEL is active.

[0035] The accumulation transistor 107 transfers the charge in the floating diffusion FD to the charge accumulation section C by connecting the floating diffusion FD and the charge accumulation section C in accordance with the accumulation control signal CT.

[0036] The charge accumulation unit C accumulates the charge transferred multiple times from the floating diffusion FD via the accumulation transistor 107 , thereby functioning as an analog memory.

[0037] First, an operation example of the pixel circuit 100 of the comparative example configured as described above will be described.

[0038] exist Figure 10 During the period T1, in the pixel circuit 100, the reset transistor 104 and the accumulation transistor 107 are turned on, thereby resetting the floating diffusion FD and the charge accumulation unit C. In other words, in order to discharge the charge in the floating diffusion FD and the charge accumulation unit C, the floating diffusion FD and the charge accumulation unit C are reset to the reset voltage RSD2.

[0039] During period T2, the reset control signal OVF is high, and reset transistor 102 resets photodiode APD to reset voltage RSD1. In other words, the charge in photodiode APD is discharged to the power supply line for reset voltage RSD1. Subsequently, when photons enter photodiode APD during exposure, the charge amplified by avalanche multiplication is collected at the cathode of photodiode APD.

[0040] During the period T3 , the charges collected at the cathode of the photodiode APD are distributed to the floating diffusion FD via the transfer transistor 103 .

[0041] Thereafter, during a period T4 , the charge is distributed to the charge accumulation unit C via the accumulation transistor 107 .

[0042] By repeating the sequence from period T2 to period T4 N times, the charge storage unit C functions as an analog memory that accumulates charge each time the accumulation transistor 107 is turned on. In other words, as photons enter the APD in each sequence, charge is gradually accumulated in the analog memory. N is an integer, for example, approximately 100.

[0043] From period T6 to period T10, the charge accumulated in the charge storage unit C, which functions as an analog memory, returns to the floating diffusion FD, where it is converted into a voltage by the amplifier transistor 105 and output to the vertical signal line 109. In other words, during period T6, the floating diffusion FD is reset. During period T7, the charge is transferred from the charge storage unit C to the floating diffusion FD. During period T8, the signal level is output to the vertical signal line 109. During period T9, the floating diffusion FD is reset. During period T10, the reset level is output to the vertical signal line 109.

[0044] So in Figure 10In the example operation, reset transistor 104 is set to a semi-conducting state from period T2 to period T4. Furthermore, transfer transistor 103 is set to a semi-conducting state during period T3. This is to suppress excess charge in photodiode APD due to avalanche multiplication. Specifically, avalanche multiplication may generate excess charge exceeding the saturation charge capacity in photodiode APD. To discharge this excess charge, the potential barrier of reset transistor 102 is set very low, and the excess charge is discharged to the power supply line of reset voltage RSD2 via transfer transistor 103 and reset transistor 104.

[0045] As described above, even in a configuration that directs excess charge generated in the photodiode APD to the power supply line for the reset voltage RSD1, the charge distributed from the cathode of the photodiode APD to the floating diffusion FD does not necessarily reach a certain level. For example, if the charge increases due to avalanche multiplication during the period of charge distribution from the cathode of the photodiode APD to the floating diffusion FD, the amount of charge accumulated in the floating diffusion FD after distribution may vary. This variation can, for example, cause variations (ranging errors) when generating a distance image based on signals from each pixel circuit 100. To reduce this variation in the amount of charge accumulated in the floating diffusion FD, the reset transistor 104 and transfer transistor 103 in the pixel circuit 100 are controlled to a half-on state. Of the charge accumulated in the floating diffusion FD from the cathode of the photodiode APD via the transfer transistor 103, any charge exceeding a certain level is discharged from the reset transistor 104 to the power supply line for the reset voltage RSD2. This reduces the variation in the amount of charge accumulated in the floating diffusion.

[0046] Next, specific problems that may arise from the above-mentioned through-current will be described.

[0047] exist Figure 9 In the pixel circuit example, when the charge increases rapidly due to avalanche multiplication in the photodiode APD, a through current may be generated in two paths. One of the two paths is Figure 10 During period T2, the power flows from the power supply line of the reset voltage RSD1 to the photodiode APD via the reset transistor 102. During period T3, the power flows from the power supply line of the reset voltage RSD2 to the photodiode APD via the reset transistor 104 and the transfer transistor 103.

[0048] The through-current can cause problems such as fluctuations in the bias voltage of the photodiode (APD), affecting the APD's operating characteristics. For example, during the APD's reset or exposure, avalanche multiplication generates a large amount of charge, which causes a through-current to flow through the APD. This through-current causes fluctuations in the bias voltage, leading to malfunctions such as the APD failing to switch from linear to Geiger multiplication mode or switching from Geiger multiplication mode to linear multiplication mode. Such malfunctions can lead to decreased sensitivity and degradation of the APD's signal-to-noise ratio (S / N), resulting in degraded brightness or range image quality.

[0049] Therefore, the present disclosure provides a solid-state imaging device and a distance measuring device that suppress the through-current of a photodiode and stabilize the operation.

[0050] In order to solve the above-mentioned problem, a scheme disclosed herein involves a solid-state imaging device having a plurality of pixel circuits arranged in a matrix, wherein the pixel circuit comprises: a photodiode; a first charge storage unit for storing charge; a floating diffusion region for storing charge; a second charge storage unit for storing charge; a first transfer transistor for transferring charge from the photodiode to the first charge storage unit; a second transfer transistor for transferring charge from the first charge storage unit to the floating diffusion region; a first reset transistor for resetting the floating diffusion region; and an accumulation transistor for accumulating the charge of the floating diffusion region in the second charge storage unit, wherein the capacitance of the first charge storage unit is larger than that of the floating diffusion region, and the capacitance of the second charge storage unit is larger than that of the floating diffusion region.

[0051] This structure suppresses the photodiode's through-current, achieving stable operation. In other words, this configuration makes it difficult for a through-current path to form. Specifically, the first and second transfer transistors are connected in series between the first reset transistor and the photodiode (APD), making it difficult for a through-current path to form. For example, even when the first reset transistor is in a semi-conducting state, a rapid increase in charge due to avalanche multiplication makes it difficult for a through-current path to form.

[0052] Furthermore, a distance measuring device according to one aspect of the present disclosure includes the solid-state imaging device described above.

[0053] In addition, these general or specific forms can be implemented by systems, methods, integrated circuits, etc., or by any combination of systems, methods, or integrated circuits.

[0054] Hereinafter, embodiments and the like will be described with reference to the drawings.

[0055] In addition, the embodiments described below are all examples of the general or specific nature of the present disclosure. The numerical values, shapes, materials, components, configuration positions of components, connection forms, and operation sequences shown in the following embodiments are all examples and are not intended to limit the present disclosure.

[0056] (Implementation Method 1)

[0057] [1.1 Pixel Circuit Structure]

[0058] Figure 1 This is a diagram showing an example of the pixel circuit 1 in the first embodiment.

[0059] The pixel circuit 1 includes a photodiode APD, a first charge storage unit C1, a floating diffusion region FD, a second charge storage unit C2, a first transfer transistor 2, a second transfer transistor 3, a first reset transistor 4, an amplifier transistor 5, a selection transistor 6, and an accumulation transistor 7. Figure 1 Also shown in the figure are vertical signal lines 9 provided for each column of the plurality of pixel circuits 1 arranged in a matrix.

[0060] A photodiode (APD) is an avalanche photodiode that amplifies electrons (charges) generated by incident photons to a saturation charge through avalanche multiplication. APDs have two operating modes: a Geiger multiplication mode, which involves avalanche multiplication, and a linear multiplication mode, which generates charge proportional to the amount of incident light. To operate in Geiger multiplication mode, a higher reverse bias voltage (VSUB) (e.g., 25V) is applied to the photodiode (APD) than in linear multiplication mode.

[0061] The first charge storage unit C1 stores charge transferred from the photodiode APD via the first transfer transistor 2. One of the two electrodes of the first charge storage unit C1 is connected to ground. The other of the two electrodes of the first charge storage unit C1 is connected to the drain or source of the first transfer transistor 2 and to the drain or source of the second transfer transistor 3. The capacitance of the first charge storage unit C1 can be greater than the capacitance of the floating diffusion FD. While this example shows one of the two electrodes of the first charge storage unit C1 connected to ground, it can also be connected to a wiring with a different potential than ground.

[0062] The floating diffusion FD accumulates the charge transferred from the first charge storage unit C1 via the second transfer transistor 3 .

[0063] The second charge storage unit C2 accumulates charge transferred from the floating diffusion FD via the accumulation transistor 7. Accumulation here refers not only to retaining charge transferred once by the accumulation transistor 7 but also to accumulating charge transferred multiple times as an analog memory. One of the two electrodes of the second charge storage unit C2 is connected to ground. The other of the two electrodes of the second charge storage unit C2 is connected to the drain or source of the second transfer transistor 3 and to the floating diffusion FD. While this example shows one of the two electrodes of the second charge storage unit C2 connected to ground, it can also be connected to a wiring with a different potential than ground. Furthermore, the capacitance of the second charge storage unit C2 can be greater than that of the floating diffusion FD. As an example of capacitance, the photodiode APD can be set to 1.5 fF, the first charge storage unit C1 to 20 fF, the second charge storage unit C2 to 20 fF, and the floating diffusion FD to 2 fF.

[0064] The first transfer transistor 2 transfers charge from the photodiode APD to the first charge accumulation unit C1 in accordance with the transfer control signal TR1. Specifically, the transfer control signal TR1 is input to the gate of the first transfer transistor 2. One of the drain and source of the first transfer transistor 2 is connected to the cathode of the photodiode APD. The other of the drain and source of the first transfer transistor 2 is connected to the first charge accumulation unit C1. For example, the first transfer transistor 2 is turned on when the transfer control signal TR1 is at a high level, and is turned off when the transfer control signal TR1 is at a low level. The charge transfer performed by the first transfer transistor 2 can be, for example, a partial transfer distributed through the capacitance of the photodiode APD and the first charge accumulation unit C1, or a complete transfer from the photodiode APD to the first charge accumulation unit.

[0065] The second transfer transistor 3 transfers charge from the first charge accumulation unit C1 to the floating diffusion FD in accordance with a transfer control signal TR2. Specifically, the transfer control signal TR2 is input to the gate of the second transfer transistor 3. One of the drain and source of the second transfer transistor 3 is connected to the first charge accumulation unit C1. The other of the drain and source of the second transfer transistor 3 is connected to the floating diffusion FD. The transfer control signal TR2 is not a binary signal but a three-valued signal. That is, the transfer control signal TR2 is a three-valued signal having a half-level in addition to a high level and a low level. For example, when the transfer control signal TR2 is at a high level, the second transfer transistor 3 is in the on state. When the transfer control signal TR2 is at a low level, the second transfer transistor 3 is in the off state. When the transfer control signal TR2 is at a half-level, the second transfer transistor 3 is in the half-on state. Here, the half-on state means that the second transfer transistor 3 is not fully on, and a potential barrier is formed under the gate of the second transfer transistor 3. Through this potential barrier, charges exceeding a certain amount in the first charge storage unit C1 are transferred from the second transfer transistor 3 to the floating diffusion FD, while charges within a certain amount in the first charge storage unit C1 remain in the first charge storage unit C1.

[0066] The first reset transistor 4 resets the floating diffusion FD in accordance with the reset control signal RS0, that is, resets the potential of the floating diffusion FD to the reset voltage RD0. Furthermore, in addition to its reset function, the first reset transistor 4 also limits the charge accumulated in the floating diffusion FD to below a specified level. This function is called charge leveling, or leveling. Therefore, the reset control signal RS0 is not a binary signal but a three-valued signal. That is, the transfer control signal TR2 is a three-valued signal with a half-level value in addition to a high level and a low level. For example, when the reset control signal RS0 is high, the first reset transistor 4 is in the on state. When the reset control signal RS0 is low, the first reset transistor 4 is in the off state. When the reset control signal RS0 is half-level, the first reset transistor 4 is in the half-on state. The term "half-on" here refers to a state in which the first reset transistor 4 is not fully on and forms a potential barrier, thus enabling the aforementioned leveling function. Charges exceeding a predetermined amount in the floating diffusion FD pass through this potential barrier and are discharged to the drain of the reset voltage RD0 via the first reset transistor 4. As a result, the charge in the floating diffusion FD is suppressed to not exceed a predetermined amount by the leveling operation.

[0067] The amplifier transistor 5 and the current source connected to the vertical signal line 9 together form a source tracking circuit. Specifically, when the select transistor 6 is off, the amplifier transistor 5 is inactive. However, when the select transistor 6 is on, the amplifier transistor 5 is connected to the current source, forming a source tracking circuit. In other words, when the select transistor 6 is on, the amplifier transistor 5 converts the charge in the floating diffusion FD into a voltage and outputs it as a pixel signal to the vertical signal line 9.

[0068] The selection transistor 6 connects the amplifier transistor 5 to the vertical signal line 9 in accordance with a selection control signal SEL. The selection control signal SEL is a signal provided for each row of the plurality of pixel circuits 1 arranged in a matrix.

[0069] The accumulation transistor 7 connects the floating diffusion FD to the second charge accumulation section C2 in accordance with the accumulation control signal CT, thereby transferring the charge in the floating diffusion FD to the second charge accumulation section C2.

[0070] In addition, Figure 1 2 shows an example in which the first transfer transistor 2 , the second transfer transistor 3 , the first reset transistor 4 , the amplifying transistor 5 , the selecting transistor 6 , and the accumulating transistor 7 are each formed of an NMOS transistor, but they may also be formed of a PMOS transistor.

[0071] In addition Figure 1 The example of a pixel circuit in which the photodiode APD is an avalanche photodiode is shown, but the present disclosure is not limited thereto. That is, the present disclosure is also applicable to a pixel circuit having a normal photodiode that generates an amount of charge corresponding to the amount of received light.

[0072] [1.2 Structure of Solid-State Imaging Device]

[0073] Next, the configuration of a solid-state imaging device including the pixel circuit 1 will be described.

[0074] Figure 2 1 is a block diagram showing a configuration example of a solid-state imaging device in Embodiment 1. The solid-state imaging device in this figure includes a pixel array 10 , a row selection circuit 20 , a control circuit 30 , and a column selection circuit 40 .

[0075] The pixel array 10 includes a plurality of pixel circuits 1 arranged in a matrix. The pixel circuits 1 can be connected to Figure 1 same.

[0076] The row selection circuit 20 outputs a selection control signal SEL for reading pixel signals for each row of the pixel circuits 1. The pixel signals may be read out by a scrolling operation in units of rows.

[0077] The control circuit 30 generates a transfer control signal TR1, a transfer control signal TR2, a reset control signal RS0, and an accumulation control signal CT to control the exposure operation of the pixel circuits 1. The exposure operation is a global operation that exposes all pixel circuits 1 simultaneously.

[0078] The column select circuit 40 receives row-by-row pixel signals, sequentially selects and outputs pixel signals. For example, pixel signals can have two types: reset level and signal level. The column select circuit 40 includes a CDS (correlated double sampling) circuit for each column and outputs the pixel signals after CDS. The CDS circuit can perform either analog or digital processing on the pixel signals.

[0079] [1.3 Action]

[0080] The operation of the pixel circuit 1 and the solid-state imaging device according to the first embodiment configured as described above will be described.

[0081] Figure 3 This is a timing chart showing a driving example of the pixel circuit 1 in the first embodiment. Figure 3 The horizontal axis is the time axis. The vertical axis corresponds to the reset control signal RS0, the transmission control signal TR1, the transmission control signal TR2, the accumulation control signal CT, and the selection control signal SEL. Figure 3 The period T0 to period T4 corresponds to a global operation P1 for exposing all pixel circuits 1 simultaneously. The period T5 to period T10 corresponds to a scrolling operation P2 for reading pixel circuits 1 in units of rows. Figure 4 1 is an operation explanatory diagram showing the potential and charge of each part of the pixel circuit 1 in the first embodiment. Figure 4 (a) to (r) schematically show Figure 3 The potential and charge at the corresponding time from time t0a to time t11b. Figure 4 In the example, "TR1(gate)" represents the potential of the transmission control signal TR1, that is, the potential at the gate of the first transfer transistor 2. "TR2(gate)" represents the potential of the transmission control signal TR2, that is, the potential at the gate of the second transfer transistor 3. "RS0(gate)" represents the potential of the reset control signal RS0, that is, the potential at the gate of the first reset transistor 4. "CT(gate)" represents the potential of the accumulation control signal CT, that is, the potential at the gate of the accumulation transistor 7. The lower the position in the figure, the greater the potential.

[0082] In addition, Figure 4 The shaded area in the figure schematically represents the charge accumulated between the valleys of the potential barrier. The range from Vq to Vr of the cathode voltage Va of the photodiode APD represents the avalanche operation region, in other words, the Geiger multiplication mode.

[0083] Figure 3 The period T1 to the period T4 in FIG. 4 represents N repetitive operations for accumulating charge in the second charge accumulation unit C2. N may be 100, for example. Figure 4 (a) to (k) represent the first operation of the repeated operation, which is based on the premise that exposure is always performed and incident light exists.

[0084] Figure 4 (a) time t0a, that is Figure 3 The beginning of period T0 corresponds to the initial state. In the initial state, "TR1 (gate)", "TR2 (gate)", "RS0 (gate)", and "CT (gate)" are all low. In other words, the first transfer transistor 2, the second transfer transistor 3, the first reset transistor 4, and the accumulation transistor 7 are all off. In other words, the pixel circuit 1 is in the initial state.

[0085] Figure 4 (b) at the moment t0b, that is Figure 3 The middle part of the period T0 corresponds to the reset action of the floating diffusion region FD and the second charge accumulation portion C2 in the first action of the repeated action. In this reset action, "TR1 (gate)" is low level, "TR2 (gate)", "RS0 (gate)" and "CT (gate)" are high level. The high level in the figure is Vr. As a result, the first transfer transistor 2 is in the off state, and the second transfer transistor 3, the first reset transistor 4 and the accumulation transistor 7 are all in the on state. In other words, in Figure 4 In (b), Figure 4 Compared to (a), the second transfer transistor 3, the first reset transistor 4, and the accumulation transistor 7 are turned from off to on. As a result, the floating diffusion region FD and the second charge accumulation unit C2 are reset to the reset voltage RD0. At this time, the first charge accumulation unit C1 is also reset to the reset voltage RD0. In this figure, the reset voltage RD0 is Vr. Figure 4 In the reset operation of (b), no path for a through current to flow through the photodiode APD is formed, so that fluctuations in the bias voltage of the photodiode APD can be suppressed, and stable operation can be achieved.

[0086] Figure 4 (c) at time t1a, i.e. Figure 3The beginning of period T1 corresponds to the state immediately after the floating diffusion FD and the second charge accumulation unit C2 are reset during the first repetitive operation. In this state, the first transfer transistor 2, the second transfer transistor 3, and the accumulation transistor 7 are in the off state. Furthermore, the first reset transistor 4 is not in the off state, but in a semi-on state. This semi-on state of the first reset transistor 4 is then maintained from period T2 to period T4. Thus, the first reset transistor 4 performs charge leveling operation P3. In other words, any charge in the floating diffusion FD that exceeds the specified amount is discharged to the power supply line for the reset voltage RD0 via the first reset transistor 4. In other words, the charge accumulated in the floating diffusion FD is suppressed so that it does not exceed the specified amount.

[0087] Figure 4 (d) time t1b, that is Figure 3 The middle part of the period T1 corresponds to the action of resetting the first charge storage unit C1 in the first action of the repeated action. In this reset action, the first transfer transistor 2 and the accumulation transistor 7 are in the off state, and the second transfer transistor 3 and the first reset transistor 4 are in the half-on state. In other words, in Figure 4 In (d), Figure 4 Compared with the state of (c), the second transfer transistor 3 changes from the cut-off state to the semi-conducting state. Figure 4 As shown in (d), in the first repetitive action, the first charge storage unit C1 only maintains the reset state in (b) of the figure, so the reset action is meaningless, but the reset action after the second time is meaningful. In this reset action, instead of directly setting the potential of the first charge storage unit C1, the second transfer transistor 3 is made semi-conductive, thereby resetting the first charge storage unit C1 to a state where a certain amount of charge is accumulated. This certain amount is set by the height of the potential barrier under the gate of the second transfer transistor 3, in other words, the potential of half the level of the transmission control signal TR2. In addition, in Figure 4 (d), the potential of the half level of the transmission control signal TR2 is set to be lower than the potential of the half level of the reset control signal RS0. In other words, the potential barrier of the half level of the transmission control signal TR2 is set to be higher than the potential barrier of the half level of the reset control signal RS0. In the example of the figure, the potential of the half level of the transmission control signal TR2 is approximately Vr / 2, which is lower than the potential of the half level of the reset control signal RS0. In other words, the potential barrier of the second transfer transistor 3 is set to be higher than the potential barrier of the first reset transistor 4. The potential barrier of the second transfer transistor 3 is set to be higher than the potential barrier of the first reset transistor 4 in order to realize the charge backflow prevention action P4, which prevents the charge from the floating diffusion area FD from flowing back to the first charge storage unit C1. Its effect does not appear in the first action of the repeated action, but appears in the actions after the second time. In this way Figure 4 In the reset operation of (d), a path for a through current to flow is not formed in the photodiode APD, so that fluctuations in the bias voltage of the photodiode APD can be suppressed, and stable operation can be achieved.

[0088] Figure 4 (e) at the time t2a, that is Figure 3 The start of period T2 corresponds to the state immediately after the first charge accumulator C1 is reset in the first repetitive operation. In this state, the first transfer transistor 2, the second transfer transistor 3, and the accumulation transistor 7 are off, and the first reset transistor 4 is half-on. The charge in the first charge accumulator C1 is cleared in the first reset operation, but is reset to a level not exceeding a certain value in the second and subsequent reset operations.

[0089] Figure 4 At the moment t2b of (f), that is Figure 3 The middle portion of the period T2 corresponds to the charge transfer from the photodiode APD to the first charge accumulation unit C1 in the first operation of the repeated operation. In this charge transfer, the first transfer transistor 2 is in the on state, the second transfer transistor 3 and the accumulation transistor 7 are in the off state, and the first reset transistor 4 is in the half-on state. In other words, Figure 4 (f), and Figure 4 Compared to (e), the first transfer transistor 2 changes from the off state to the on state. Since the first transfer transistor 2 is in the on state, the potential barrier between the photodiode APD and the first charge storage unit C1 disappears, and the charge of the photodiode APD is transferred to the first charge storage unit C1, reaching the same potential.

[0090] To explain in more detail, in this operation example, light is always incident on the photodiode APD, so the photodiode APD, which receives the incident light, generates a large amount of charge through avalanche multiplication. Avalanche multiplication stops when the photodiode APD reaches the quenching potential Vq. As a result, Figure 4 As in (f), the photodiode APD and the first charge storage unit C1 are fully charged to the Vq potential.

[0091] Here, while the first transfer transistor 2 is in the on state, the second transfer transistor 3 is in the off state, thereby preventing the formation of a current path that could generate a through-current in the photodiode APD. This suppresses the through-current caused by avalanche multiplication, stabilizing the operation of the photodiode APD.

[0092] Figure 4 (g) time t3a, that is Figure 3The start of period T3 corresponds to the state immediately after charge transfer from the photodiode APD to the first charge accumulation unit C1 in the first cycle of the repetitive operation. In this state, the first transfer transistor 2, the second transfer transistor 3, and the accumulation transistor 7 are off, and the first reset transistor 4 is half-on. Charge is accumulated in the photodiode APD to the Vq potential. Furthermore, charge is also accumulated in the first charge accumulation unit C1 to the Vq potential.

[0093] Figure 4 At the moment t3b of (h), that is Figure 3 The middle portion of the period T3 corresponds to the charge transfer from the first charge accumulation unit C1 to the floating diffusion region FD in the first operation of the repeated operation. In this charge transfer, the first transfer transistor 2 and the accumulation transistor 7 are in the off state, and the second transfer transistor 3 and the first reset transistor 4 are in the half-on state. In other words, Figure 4 (h), and Figure 4 Compared with (g), the second transfer transistor 3 changes from the cut-off state to the semi-conducting state. The second transfer transistor 3 is in the semi-conducting state, so Figure 4 The charges exceeding a certain amount in the first charge storage unit C1 stored in (g) are transferred to the floating diffusion region FD. Figure 4 Similarly, the potential barrier formed by the half-on state of the second transfer transistor 3 is set slightly higher than the potential barrier formed by the half-on state of the first reset transistor 4. Furthermore, since the first reset transistor 4 is also half-on, the leveling action causes any charge transferred from the first charge storage unit C1 that exceeds a predetermined amount to be discharged to the power supply line for the reset voltage RD0. In other words, the charge accumulated in the floating diffusion FD is suppressed to a predetermined amount.

[0094] Figure 4 (i) time t4a, that is Figure 3 The beginning of the period T4 corresponds to the state immediately after the charge transfer from the first charge accumulation unit C1 to the floating diffusion region FD in the first operation of the repeated operation is completed. In this state, the first transfer transistor 2, the second transfer transistor 3, and the accumulation transistor 7 are in the off state, and the first reset transistor 4 is in the half-on state. In other words, Figure 4 (i), and Figure 4 Compared to (h), the second transfer transistor 3 changes from a half-on state to an off state. In this state, the charge transferred from the first charge storage unit C1 is accumulated in the floating diffusion region FD. In addition, the first charge storage unit C1 accumulates no more than a certain amount of charge.

[0095] Figure 4 (j) at the moment t4b, that is Figure 3The middle portion of period T4 corresponds to the charge transfer from the floating diffusion region FD to the second charge accumulation portion C2 in the first operation of the repeated operation. In this charge transfer, the first transfer transistor 2 and the second transfer transistor 3 are in the off state, the first reset transistor 4 is in the half-on state, and the accumulation transistor 7 is in the on state. In other words, Figure 4 (j), and Figure 4 Compared to (i), the accumulation transistor 7 switches from the off state to the on state. Consequently, the floating diffusion FD and the second charge accumulation unit C2 reach the same potential, and the charge is distributed across the capacitor. In other words, a portion of the charge accumulated in the floating diffusion FD is transferred to the second charge accumulation unit C2.

[0096] Figure 4 The moment t5a of (k), that is Figure 3 The start of period T5 corresponds to the state immediately after the charge transfer from the floating diffusion region FD to the second charge accumulation portion C2 in the first operation of the repeated operation is completed. In this state, the first transfer transistor 2, the second transfer transistor 3, and the accumulation transistor 7 are in the off state, and the first reset transistor 4 is in the half-on state. In other words, Figure 4 (k), and Figure 4 Compared with (j), the accumulation transistor 7 changes from the on state to the off state. In this state, the second charge accumulation unit C2 accumulates the charge transferred from the floating diffusion FD.

[0097] Figure 4 (a) to (k) show the first action among the N repeated actions performed in the global action P1.

[0098] In subsequent operations, the same operations as the first operation are repeated. By repeating the period T1 to period T4 N times, the pixel signals based on the N exposures are accumulated in the second charge accumulation unit C2. This improves the SN ratio and accuracy of the pixel signals.

[0099] After the global operation P1 including repeating the period T1 to the period T4 N times, the scroll operation P2 of reading pixel signals in units of rows is performed.

[0100] Figure 3 The period T5 is a transition period from the global action P1 to the scroll action P2. The scroll action P2 includes the period T6 to the period T11.

[0101] In the period T6, the floating diffusion region FD is reset. In addition, in the period T6, the resetting of the floating diffusion region FD may be omitted.

[0102] During the period T7 , the charges accumulated in the second charge storage unit C2 are transferred to the FD.

[0103] During the period T8, the charge in the floating diffusion region FD is converted into a voltage by the amplifier transistor 5. The converted voltage is output to the vertical signal line 9 as a signal level in the pixel signal.

[0104] During the period T9 , the floating diffusion FD and the second charge storage unit C2 are reset to the reset voltage RD0 .

[0105] During the period T10, the reset charge of the floating diffusion region FD is converted into a voltage by the amplifier transistor 5. The converted voltage is output to the vertical signal line 9 as a reset level in the pixel signal.

[0106] The period T11 is a transition period to the next frame period.

[0107] The solid-state imaging device involved in embodiment 1 described above has a plurality of pixel circuits arranged in a matrix, and the pixel circuit 1 has: a photodiode APD; a first charge storage unit C1 for storing charge; a floating diffusion region FD for storing charge; a second charge storage unit C2 for storing charge; a first transfer transistor 2 for transferring charge from the photodiode APD to the first charge storage unit C1; a second transfer transistor 3 for transferring charge from the first charge storage unit C1 to the floating diffusion region FD; a first reset transistor 4 for resetting the floating diffusion region FD; and an accumulation transistor 7 for accumulating the charge of the floating diffusion region in the second charge storage unit, wherein the capacitance of the first charge storage unit C1 is larger than that of the floating diffusion region FD, and the capacitance of the second charge storage unit C2 is larger than that of the floating diffusion region FD.

[0108] This configuration suppresses the through-current in the photodiode, stabilizing its operation. Specifically, the configuration makes it difficult for a through-current path to form. Specifically, the first and second transfer transistors are connected in series between the first reset transistor and the photodiode (APD), making it difficult for a through-current path to form.

[0109] Further in Figure 9 In the comparative example, the charge discharged from the power supply line for the reset voltage RSD1 and the power supply line for the reset voltage RSD2 flows into adjacent pixels as noise, causing the adjacent pixels to whiten, etc., resulting in poor characteristics. The solid-state imaging device according to the first embodiment has the effect of improving this problem.

[0110] Here, the solid-state imaging device may further include a control circuit 30 that resets the first charge storage unit C1 by turning off the first transfer transistor 2 and the accumulation transistor 7 and turning on the first reset transistor 4 and the second transfer transistor 3 .

[0111] This makes it difficult for a through-current path to form, thereby suppressing the through-current of the photodiode and achieving stable operation. For example, when the first reset transistor is in a half-on state, the through-current of the photodiode can be suppressed and the operation can be stabilized.

[0112] Here, the solid-state imaging device may further include a control circuit 30. During a first period for resetting the floating diffusion region FD and the second charge storage unit C2, the control circuit 30 turns off the first transfer transistor 2 and turns on the first reset transistor 4, the second transfer transistor 3, and the accumulation transistor 7. During a second period for resetting the first charge storage unit C1, the control circuit 30 turns off the first transfer transistor 2 and the accumulation transistor 7 and turns off the first reset transistor 4 and the second transfer transistor 3. Figure 3 The second period corresponds to the period T0. Figure 3 Corresponding to period T1.

[0113] As described above, when the first reset transistor 4 and the second transfer transistor 3 are in the half-on state, a through-current path is less likely to be formed, so that the through-current of the photodiode can be suppressed, and the operation can be stabilized.

[0114] Here, the control circuit 30 may control a global action P1 including simultaneous exposure of a plurality of pixel circuits 1 and a rolling action P2 including reading signals from the plurality of pixel circuits 1 in row units during one frame period, wherein the global action P1 includes a first period and a second period, and the control circuit 30 maintains the first reset transistor 4 in a semi-conducting state after the second period during the period of the global action P1.

[0115] As described above, even if charges are rapidly generated by avalanche multiplication in the global operation P1 , charges exceeding a certain amount in the floating diffusion FD can be discharged through the first reset transistor 4 , so that the excess charges can be appropriately controlled.

[0116] Here, the solid-state imaging device may further include a control circuit 30 , and the control circuit 30 may place the first reset transistor 4 in a half-conducting state.

[0117] As described above, the charge exceeding a certain amount in the floating diffusion FD is discharged through the first reset transistor 4 , so that the excess charge can be appropriately controlled.

[0118] Here, the solid-state imaging device may further include a control circuit 30 , and the control circuit 30 may place the second transfer transistor 3 in a half-conducting state.

[0119] As described above, among the charges in the first charge storage unit C1 , charges exceeding a certain amount can be transferred to the floating diffusion FD.

[0120] Here, the control circuit 30 may control the transfer of charge from the photodiode APD to the first charge accumulation unit C1 during the third period, control the transfer of charge from the first charge accumulation unit C1 to the floating diffusion region FD during the fourth period, and control the accumulation of charge from the floating diffusion region FD to the second charge accumulation unit C2 during the fifth period. From the second period to the fifth period, the first reset transistor 4 is maintained in a half-on state. Figure 3 Corresponding to the period T2 to T4.

[0121] As described above, even if charges are rapidly generated due to avalanche multiplication from the second period to the fourth period, charges of a certain amount or more are discharged by the first reset transistor 4 , thereby enabling the charge amount to be appropriately controlled.

[0122] Here, the control circuit 30 may turn off the first transfer transistor 2 and the accumulation transistor 7 and turn on the second transfer transistor 3 in the half-conducting state during the fourth period T3.

[0123] Here, in the fourth period, the potential barrier formed at the gate of the second transfer transistor 3 may be higher than the potential barrier formed at the gate of the first reset transistor 4 .

[0124] As described above, in the charge transfer from the first charge storage unit C1 to the floating diffusion FD, the reverse flow of the charge can be suppressed.

[0125] Here, the control circuit 30 may repeat the second to fifth periods a plurality of times after the first period ends within one frame period.

[0126] As a result, the amount of signal obtained by exposure can be significantly increased, so the SN ratio of the pixel signal and the accuracy of the pixel signal can be improved.

[0127] Furthermore, a distance measuring device according to one aspect of the first embodiment includes the above-mentioned solid-state imaging device.

[0128] This configuration suppresses the through-current in the photodiode, stabilizing its operation. Specifically, the configuration makes it difficult for a through-current path to form. Specifically, the first and second transfer transistors are connected in series between the first reset transistor and the photodiode APD, making it difficult for a through-current path to form.

[0129] (Implementation Method 2)

[0130] In the first embodiment, an example was shown in which the charge was reset to a certain level by turning the second transfer transistor 3 into a half-conductive state during the reset operation of the first charge storage unit C1. In contrast, in the second embodiment, an example configuration is described in which the first charge storage unit C1 is directly reset to a predetermined reset potential without relying on the second transfer transistor 3.

[0131] The solid-state imaging device of embodiment 2 can be used with Figure 2 The structure is the same.

[0132] [2.1 Pixel Circuit Structure]

[0133] Figure 5 This is a diagram showing a circuit example of the pixel circuit 1 in the second embodiment. Figure 5 and Figure 1 The difference is that the second reset transistor 8 is added. The following description will not be repeated for the same points, but will focus on the differences.

[0134] The second reset transistor 8 resets the first charge accumulator C1 in response to the reset control signal RS1, that is, resets the potential of the first charge accumulator C1 to the reset voltage RD1. The drain of the second reset transistor 8 is connected to the power supply line for the reset voltage RD1. The reset control signal RS1 is input to the gate of the second reset transistor 8. The source of the second reset transistor 8 is connected to the first charge accumulator C1, one of the source and drain of the first transfer transistor 2, and one of the source and drain of the second transfer transistor 3.

[0135] The reset control signal RS1 is a binary signal having a high level and a low level. Therefore, the second reset transistor 8 has two states: an on state and an off state.

[0136] [2.2 Action]

[0137] The operation of the pixel circuit 1 according to the second embodiment configured as described above will be described.

[0138] Figure 6 This is a timing chart showing a driving example of the pixel circuit 1 in the second embodiment. Figure 6 and Figure 3 The main difference is that the reset control signal RS1 is added, and the waveforms of the transmission control signals TR1 and TR2 are different. Figure 7 1 is an explanatory diagram showing the operation of the potential and charge of each part of the pixel circuit 1 in the second embodiment. Figure 7 and Figure 4 The main differences are the addition of "RS1 (gate)" and the difference in potential at each stage. The following description focuses on these differences.

[0139] Figure 7 "RS1 (gate)" represents the potential of the reset control signal RS1 input to the gate of the second reset transistor 8, that is, the potential under the gate of the second reset transistor 8. Figure 7 (a) to (k) represent the first operation of the repeated operation, which is based on the premise that exposure is always performed and incident light exists.

[0140] Figure 7 (a) at the moment t0a, that is Figure 6 The beginning of period T0 corresponds to the initial state. In the initial state, "TR1(gate)", "RS1(gate)", "TR2(gate)", "RS0(gate)", and "CT(gate)" are all low. In other words, the first transfer transistor 2, the second reset transistor 8, the second transfer transistor 3, the first reset transistor 4, and the accumulation transistor 7 are all off. In other words, the pixel circuit 1 is in the initial state.

[0141] Figure 7 (b) at the moment t0b, that is Figure 6 The middle part of the period T0 corresponds to the reset operation of the floating diffusion region FD and the second charge accumulation portion C2 in the first operation of the repeated operation. In this reset operation, the first transfer transistor 2, the second reset transistor 8, and the second transfer transistor 3 are in the off state, and the first reset transistor 4 and the accumulation transistor 7 are in the on state. In other words, in Figure 7 In (b), Figure 7 Compared to (a), the first reset transistor 4 and the accumulation transistor 7 are turned from the off state to the on state. As a result, the floating diffusion FD and the second charge storage unit C2 are reset to the reset voltage RD0.

[0142] Figure 7 (c) at time t1a, i.e. Figure 6 The beginning of period T1 corresponds to the state immediately after the floating diffusion FD and the second charge accumulation unit C2 are reset during the first repetitive operation. In this state, the first transfer transistor 2, the second reset transistor 8, the second transfer transistor 3, and the accumulation transistor 7 are in the off state. Furthermore, the first reset transistor 4 is not in the off state but in a semi-on state. This semi-on state of the first reset transistor 4 is then maintained from period T2 to period T4. Thus, the first reset transistor 4 performs charge leveling operation P3. In other words, any charge in the floating diffusion FD that exceeds the specified amount is discharged to the power supply line for the reset voltage RD0 via the first reset transistor 4. In other words, the charge accumulated in the floating diffusion FD is suppressed so that it does not exceed the specified amount.

[0143] Figure 7 (d) at time t1b, that is Figure 6 The middle part of the period T1 corresponds to the action of resetting the first charge storage unit C1 in the first action of the repeated action. In this reset action, the first transfer transistor 2, the second transfer transistor 3 and the accumulation transistor 7 are in the off state, the second reset transistor 8 is in the on state, and the first reset transistor 4 is in the half-on state. In other words, in Figure 7 In (d), Figure 7 Compared to (c), the second reset transistor 8 changes from the off state to the on state. As a result, the charge of the first charge storage unit C1 is discharged to the power supply line of the reset voltage RD1 through the second reset transistor 8. In this example, the reset voltage RD1 is Vr. The first charge storage unit C1 is reset to the potential Vr. In this reset action, the first transfer transistor 2 is in the off state, so no path for the through current of the photodiode APD is formed. In addition, Figure 7 The reset operation of the first charge storage unit C1 in (d) is the same as Figure 4 Compared with (1), when the first charge storage unit C1 is set to the reset potential, the intervention of the second transfer transistor 3 is not required and the reset can be performed directly, so it can be performed at high speed and high precision.

[0144] Figure 7 (e) at the moment t2a, that is Figure 6 The start of period T2 corresponds to the state immediately after the first charge storage unit C1 is reset in the first repetitive operation. In this state, the first transfer transistor 2, the second reset transistor 8, the second transfer transistor 3, and the accumulation transistor 7 are off, and the first reset transistor 4 is half-on. The first charge storage unit C1 is reset to the reset voltage RD1.

[0145] Figure 7 At the moment t2b of (f), that is Figure 6 The middle portion of the period T2 corresponds to the charge transfer from the photodiode APD to the first charge accumulation unit C1 in the first operation of the repeated operation. In this charge transfer, the first transfer transistor 2 is in the on state, the second reset transistor 8, the second transfer transistor 3 and the accumulation transistor 7 are in the off state, and the first reset transistor 4 is in the half-on state. In other words, Figure 7 (f), and Figure 7 Compared to (e), the first transfer transistor 2 changes from the off state to the on state. Since the first transfer transistor 2 is in the on state, the potential barrier between the photodiode APD and the first charge storage unit C1 disappears, and the charge is transferred from the photodiode APD to the first charge storage unit C1, reaching the same potential.

[0146] To explain in more detail, in this operation example, light is always incident on the photodiode APD, so the photodiode APD, which receives the incident light, generates a large amount of charge through avalanche multiplication. Avalanche multiplication stops when the photodiode APD reaches the quenching potential Vq. As a result, Figure 7 As in (f), the photodiode APD and the first charge storage unit C1 are filled with charges up to the Vq potential.

[0147] Here, while the first transfer transistor 2 is in the on state, the second transfer transistor 3 is in the off state, and the second reset transistor 8 is also in the off state. Therefore, a current path that could generate a through-current is not formed in the photodiode APD. Therefore, the through-current caused by avalanche multiplication can be suppressed, and the operation of the photodiode APD is stabilized.

[0148] Figure 7 At the moment t3a of (g), that is Figure 6 The start of period T3 corresponds to the state immediately after charge transfer from the photodiode APD to the first charge accumulation unit C1 in the first cycle of the repetitive operation. In this state, the first transfer transistor 2, the second reset transistor 8, the second transfer transistor 3, and the accumulation transistor 7 are in the off state, and the first reset transistor 4 is in the half-on state. Charge is accumulated in the photodiode APD to the Vq potential. Furthermore, charge is also accumulated in the first charge accumulation unit C1 to the Vq potential.

[0149] Figure 7 At the moment t3b of (h), that is Figure 6 The middle portion of the period T3 corresponds to the charge transfer from the first charge accumulation unit C1 to the floating diffusion region FD in the first operation of the repeated operation. In this charge transfer, the first transfer transistor 2, the second reset transistor 8, and the accumulation transistor 7 are in the off state, and the second transfer transistor 3 and the first reset transistor 4 are in the half-on state. In other words, Figure 7 (h), and Figure 7 Compared with (g), the second transfer transistor 3 changes from the cut-off state to the semi-conducting state. The second transfer transistor 3 is in the semi-conducting state, so Figure 7 The charge exceeding a predetermined amount of the charge stored in the first charge storage unit C1 in (g) is transferred to the floating diffusion FD. Furthermore, the potential barrier formed by the half-on state of the second transfer transistor 3 is set slightly higher than the potential barrier formed by the half-on state of the first reset transistor 4. Furthermore, since the first reset transistor 4 is also half-on, the leveling action causes the charge exceeding the predetermined amount of charge transferred from the first charge storage unit C1 to be discharged to the power supply line for the reset voltage RD0. In other words, the charge accumulated in the floating diffusion FD is suppressed to a predetermined amount.

[0150] Figure 7 (i) time t4a, that is Figure 6 The beginning of the period T4 corresponds to the state immediately after the charge transfer from the first charge accumulation unit C1 to the floating diffusion region FD in the first operation of the repeated operation is completed. In this state, the first transfer transistor 2, the second reset transistor 8, the second transfer transistor 3, and the accumulation transistor 7 are in the off state, and the first reset transistor 4 is in the half-on state. In other words, Figure 7 (i) and Figure 7 Compared to (h), the second transfer transistor 3 changes from a half-on state to an off state. In this state, the charge transferred from the first charge storage unit C1 is accumulated in the floating diffusion region FD. In addition, the first charge storage unit C1 accumulates no more than a certain amount of charge.

[0151] Figure 7 (j) at the moment t4b, that is Figure 6 The middle portion of the period T4 corresponds to the charge transfer from the floating diffusion region FD to the second charge accumulation portion C2 in the first operation of the repeated operation. In this charge transfer, the first transfer transistor 2, the second reset transistor 8, and the second transfer transistor 3 are in the off state, the first reset transistor 4 is in the half-on state, and the accumulation transistor 7 is in the on state. In other words, Figure 7 (j) and Figure 7 Compared to (i), the accumulation transistor 7 changes from the off state to the on state. Consequently, the floating diffusion FD and the second charge accumulation unit C2 reach the same potential, and the charge is distributed across the capacitor. A portion of the charge accumulated in the floating diffusion FD is transferred to the second charge accumulation unit C2. In other words, a portion of the charge accumulated in the floating diffusion FD is transferred to the second charge accumulation unit C2.

[0152] Figure 7 The moment t5a of (k), that is Figure 6 The beginning of the period T5 corresponds to the state immediately after the charge transfer from the floating diffusion region FD to the second charge accumulation portion C2 in the first operation of the repeated operation is completed. In this state, the first transfer transistor 2, the second reset transistor 8, the second transfer transistor 3, and the accumulation transistor 7 are in the off state, and the first reset transistor 4 is in the half-on state. In other words, Figure 7 (k) and Figure 7 Compared with (j), the accumulation transistor 7 changes from the on state to the off state. In this state, the second charge accumulation unit C2 accumulates the charge transferred from the floating diffusion FD.

[0153] Figure 7 (a) to (k) show the first action among the N repeated actions in the global action P1.

[0154] In subsequent operations, the same operation as the first operation is repeated. By repeating the period T1 to period T4 N times, the pixel signals based on the N exposures are accumulated in the second charge accumulation unit C2. This improves the SN ratio and accuracy of the pixel signals.

[0155] After the global operation P1 including repeating the period T1 to the period T4 N times, a scroll operation P2 for reading pixel signals in units of rows is performed.

[0156] Figure 6 The period T5 is a transition period from the global action P1 to the scroll action P2. The scroll action P2 includes the period T6 to the period T11.

[0157] In the period T6, the floating diffusion region FD is reset. In addition, in the period T6, the resetting of the floating diffusion region FD may be omitted.

[0158] During the period T7 , the charges accumulated in the second charge storage unit C2 are transferred to the FD.

[0159] During the period T8, the charge in the floating diffusion region FD is converted into a voltage by the amplifier transistor 5. The converted voltage is output to the vertical signal line 9 as a signal level in the pixel signal.

[0160] During the period T9 , the floating diffusion FD and the second charge storage unit C2 are reset to the reset voltage RD0 .

[0161] During the period T10, the reset charge of the floating diffusion region FD is converted into a voltage by the amplifier transistor 5. The converted voltage is output to the vertical signal line 9 as a reset level in the pixel signal.

[0162] The period T11 is a transition period to the next frame period.

[0163] As described above, the solid-state imaging device according to the second embodiment further includes the second reset transistor 8 for resetting the first charge storage unit C1 .

[0164] As described above, the through current is suppressed during resetting, and the first charge storage unit C1 is directly reset. Therefore, the noise level of the reset level can be reduced, the SN ratio can be improved, and the accuracy of the pixel signal can be improved.

[0165] Here, the solid-state imaging device may further include a control circuit 30, which resets the first charge storage unit C1 by turning off the first transfer transistor 2, the second transfer transistor 3, and the accumulation transistor 7, turning on the second reset transistor 8, and turning on the first reset transistor 4.

[0166] As described above, the first charge storage unit C1 can be directly reset, and a through current can be suppressed during the reset.

[0167] Here, the solid-state imaging device may further include a control circuit 30, and during a first period T0 for resetting the floating diffusion region FD and the second charge accumulation unit C2, the control circuit 30 turns off the second reset transistor 8, the first transfer transistor 2, and the second transfer transistor 3, and turns on the first reset transistor 4 and the accumulation transistor 7, and during a second period T1 for resetting the first charge accumulation unit C1, the control circuit 30 turns off the first transfer transistor 2, the second transfer transistor 3, and the accumulation transistor 7, turns on the second reset transistor 8, and turns on the first reset transistor 4, and puts the first reset transistor 4 into a semi-conducting state.

[0168] As described above, even when the first reset transistor 4 is in a half-on state, a through-current path is unlikely to be formed, so that the through-current of the photodiode can be suppressed, and the operation can be stabilized.

[0169] Here, the control circuit 30 may control the global action P1 for simultaneously exposing all pixel circuits and the rolling action P2 for reading signals from the pixel circuits in row units during one frame period, wherein the global action P1 includes a first period and a second period, and the control circuit 30 maintains the first reset transistor 4 in a semi-conducting state after the second period during the period of the global action P1.

[0170] As described above, even if charges are rapidly generated by avalanche multiplication in the global operation P1 , charges exceeding a certain amount in the floating diffusion region FD can be discharged by the first reset transistor 4 , thereby appropriately controlling the excess charges.

[0171] (Implementation Method 3)

[0172] In the third embodiment, a configuration example of a distance measuring device will be described as an application example of the solid-state imaging device of the first and second embodiments.

[0173] [3.1 Structure of the distance measuring device]

[0174] Figure 8 This is a block diagram showing a configuration example of a distance measuring device in a third embodiment.

[0175] This distance measuring device includes a light projecting device 50 and an imaging device 60. The light projecting device 50 projects light toward a target area and includes a light source 51 and a light emission control unit 52.

[0176] The imaging device 60 receives reflected light from an object in a target area of the light emitted from the light projecting device 50. Therefore, the imaging device 60 includes a solid-state imaging device 61, an imaging control unit 62, and a signal processing unit 63.

[0177] The light source 51 is composed of a laser light source or an LED (Light Emitting Diode), and emits light of a predetermined wavelength.

[0178] The light emission control unit 52 causes the light source 51 to emit pulse light under the control of the signal processing unit 63 .

[0179] The solid-state imaging device 61 is the solid-state imaging device of Embodiment 1 or Embodiment 2, and receives reflected light of the light emitted from the light projecting device 50 after being reflected by an object.

[0180] The imaging control unit 62 drives the solid-state imaging device 61 under the control of the signal processing unit 63 .

[0181] The signal processing unit 63 calculates the distance to the object by controlling the light emission control unit 52 and the imaging control unit 62. Specifically, the signal processing unit 63 causes the light source 51 to emit pulsed light via the light emission control unit 52. The solid-state imaging device 61 receives reflected light from this pulsed light. Furthermore, the signal processing unit 63 measures the distance to the object located at a position in the target area corresponding to each pixel circuit 1 based on the time difference between the timing of the pulsed light emission and the timing of the reflected light reception in each pixel circuit 1.

[0182] When the solid-state imaging device 61 includes the pixel circuit 1 of Embodiment 1, the area of the pixel array 10 on the semiconductor substrate can be reduced compared to when the solid-state imaging device 61 includes the pixel circuit 1 of Embodiment 2. In other words, the pixel circuit 1 does not include the second reset transistor 8, so the area can be reduced.

[0183] Furthermore, when the solid-state imaging device 61 includes the pixel circuit 1 of Embodiment 2, the SN ratio and accuracy of the pixel signal can be improved, and the speed can be further increased, compared to when the pixel circuit 1 of Embodiment 1 is included. Because the reset state of the first charge storage unit C1 is not a reset state in which a certain amount of charge is accumulated in the first charge storage unit C1, but a state in which the device is directly reset by the reset voltage RD1, the device is less susceptible to the influence of noise.

[0184] in addition, Figure 8 The distance measuring device generates not only a distance image but also a brightness image. Figure 2 The control circuit 30 may be provided on the same semiconductor substrate as the solid-state imaging device, or may be provided on a semiconductor substrate different from the solid-state imaging device.

[0185] In addition, all or part of the components in each of the above embodiments may be formed by dedicated hardware, or implemented by executing software programs suitable for each component. Some of the components may be implemented by a program execution unit such as a CPU or processor reading and executing a software program stored in a recording medium such as a semiconductor memory.

[0186] The solid-state imaging device and ranging device according to one or more embodiments have been described above based on embodiments. However, the present disclosure is not limited to these embodiments. Within the scope of the present disclosure, various modifications that can be imagined by those skilled in the art to the present embodiment and the embodiments formed by combining components from different embodiments are also included within the scope of one or more embodiments of the present disclosure.

[0187] The solid-state imaging device and the distance measuring device according to the present disclosure can be used in a video camera, for example.

[0188] Explanation of symbols

[0189] 1,100 pixel circuit

[0190] 2 1st transfer transistor

[0191] 3 Second transfer transistor

[0192] 4 1st reset transistor

[0193] 5,105 amplifier transistor

[0194] 6,106 Select transistor

[0195] 7,107 Accumulator transistor

[0196] 8 2nd reset transistor

[0197] 9,109 vertical signal line

[0198] 10-pixel array

[0199] 20 row selection circuit

[0200] 30 Control circuit

[0201] 40 column selection circuit

[0202] 50 light projection device

[0203] 51 Light Source

[0204] 52 Lighting control unit

[0205] 60 Camera

[0206] 61 Solid-state imaging device

[0207] 62 Camera Control Unit

[0208] 63 Signal Processing Unit

[0209] 102, 104 reset transistor

[0210] 103 Pass transistor

[0211] APD photodiode

[0212] C Charge storage unit

[0213] C1 First charge storage unit

[0214] C2 Second charge storage unit

[0215] CT accumulation control signal

[0216] FD floating diffusion region

[0217] RD0, RD1, RSD1, RSD2 reset voltage

[0218] RS0, RS1, RST, OVF reset control signals

[0219] SEL selection control signal

[0220] TR1, TR2, TRN transmission control signals.

Claims

1. A solid-state imaging device comprising a plurality of pixel circuits arranged in a matrix. The pixel circuit comprises: Photodiode; a first charge storage unit for storing charge; Floating diffusion region, which accumulates charge; a second charge storage unit for storing charge; a first transfer transistor for transferring charge from the photodiode to the first charge storage unit; a second transfer transistor for transferring charge from the first charge storage portion to the floating diffusion region; a first reset transistor for resetting the floating diffusion region; and an accumulation transistor for accumulating the charge of the floating diffusion region in the second charge accumulation portion, The capacitance of the first charge storage unit is larger than the capacitance of the floating diffusion region. The capacitance of the second charge storage unit is larger than the capacitance of the floating diffusion region. The solid-state imaging device further includes a control circuit that places the second transfer transistor in a half-conducting state.

2. The solid-state imaging device according to claim 1, The control circuit resets the first charge storage unit by turning off the first transfer transistor and the accumulation transistor and turning on the first reset transistor and the second transfer transistor.

3. The solid-state imaging device according to claim 1, In a first period for resetting the floating diffusion region and the second charge storage unit, the control circuit turns off the first transfer transistor and turns on the first reset transistor, the second transfer transistor, and the accumulation transistor. During a second period for resetting the first charge storage unit, the control circuit turns off the first transfer transistor and the accumulation transistor, and turns on the first reset transistor and the second transfer transistor.

4. The solid-state imaging device according to claim 3, The control circuit controls a global operation including simultaneous exposure of the plurality of pixel circuits and a scrolling operation including reading out signals from the plurality of pixel circuits in units of rows within one frame period. The global action includes the first period and the second period, The control circuit maintains the first reset transistor in a half-on state after the second period within the global operation period.

5. The solid-state imaging device according to claim 1, The solid-state imaging device further includes a second reset transistor configured to reset the first charge storage unit.

6. The solid-state imaging device according to claim 1 or 5, The control circuit puts the first reset transistor into a half-conducting state.

7. The solid-state imaging device according to claim 5, The control circuit resets the first charge storage unit by turning off the first transfer transistor, the second transfer transistor, and the accumulation transistor, turning on the second reset transistor, and turning on the first reset transistor.

8. The solid-state imaging device according to claim 5, During a first period for resetting the floating diffusion region and the second charge storage unit, the control circuit turns off the second reset transistor, the first transfer transistor, and the second transfer transistor, and turns on the first reset transistor and the accumulation transistor. During a second period for resetting the first charge storage unit, the control circuit turns off the first transfer transistor, the second transfer transistor, and the accumulation transistor, turns on the second reset transistor, and turns on the first reset transistor.

9. The solid-state imaging device according to claim 8, The control circuit controls a global operation for simultaneously exposing all pixel circuits and a rolling operation for reading signals from the pixel circuits in units of rows within one frame period. The global action includes the first period and the second period, The control circuit maintains the first reset transistor in a half-on state after the second period within the global operation period.

10. The solid-state imaging device according to claim 4 or 8, The control circuit, During a third period, control is performed to transfer charges from the photodiode to the first charge storage unit. In a fourth period, control is performed to transfer charges from the first charge storage unit to the floating diffusion region. In a fifth period, control is performed to store charges from the floating diffusion into the second charge storage unit. From the second period to the fifth period, the first reset transistor is maintained in a half-on state.

11. The solid-state imaging device according to claim 10, The control circuit turns off the first transfer transistor and the accumulation transistor and turns on the second transfer transistor in the semi-conducting state during the fourth period.

12. The solid-state imaging device according to claim 11, During the fourth period, the potential barrier formed at the gate of the second transfer transistor is higher than the potential barrier formed at the gate of the first reset transistor.

13. The solid-state imaging device according to claim 10, The control circuit repeats the second to fifth periods a plurality of times after the first period ends within one frame period. 14 . A distance measuring device comprising the solid-state imaging device according to claim 1 .

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