Multi-channel digital isolator with integrated PWM interlock protection

Abstract

A multi-channel digital isolator includes a digital isolator (120B) and an interlock circuit (250). The isolator includes a transmitter (305) having a transmitter output, a receiver (310) having a receiver input and a receiver output, an isolation barrier (220) coupled between the transmitter output and the receiver input, and an output buffer (360A) having a buffer input and configured to output an isolated signal. The transmitter is configured to transmit an input signal across the isolation barrier. The interlock circuit has an interlock input coupled to the receiver output and an interlock output coupled to the buffer input. The interlock module is configured to prevent overlapping valid states between a first isolated signal and a complementary isolated signal. In some embodiments, the digital isolator further includes a dead time insertion circuit.

Description

Background Art

[0001] Power drives may include circuitry that provides power to recharge a battery or drive an electric motor. Therefore, power drives typically operate at higher voltages and / or higher currents than the logic circuitry that drives them. For example, a power drive may be controlled by a controller that turns transistors in the power drive on and off. One technique for turning these transistors on and off is pulse width modulation (PWM).

[0002] Many power drives use complementary PWM control signals to ensure that the high-side and low-side transistors are not on at the same time, which would result in shoot-through current that could damage or degrade the performance of the power drive and any motor or other system coupled to it. Some power drives are electrically isolated from the digital controller that generates the PWM control signals to convert voltage levels, prevent destructive ground loops, and / or for the electrical safety of any system users from high voltages.

[0003] However, during power-up or power-down of the digital controller (e.g., before PWM initialization) or due to faults in the digital controller's software, the isolator's hardware, or the board traces carrying the PWM control signals on the isolated side of the system, the complementary PWM control signals may overlap (e.g., both PWM control signals will be at logic high). Interlock circuits can prevent overlap between the complementary PWM control signals, but they must be implemented on the system's logic side, thus only correcting for software faults. Additionally, these discrete interlock circuits increase the area, cost, and bill of materials of these systems. Summary of the Invention

[0004] A multi-channel digital isolator includes a digital isolator and an interlock circuit. The digital isolator includes a transmitter having a transmitter output, a receiver having a receiver input and a receiver output, an isolation barrier coupled between the transmitter output and the receiver input, and an output buffer having a buffer input and configured to output an isolated signal. The transmitter is configured to transmit an input signal across the isolation barrier. The interlock circuit has an interlock input coupled to the receiver output and an interlock output coupled to the buffer input.

[0005] The interlock circuit is configured to prevent overlapping valid states between the isolated signal and the complementary isolated signal. In some embodiments, the digital isolator further includes an inverter and a complementary output buffer. The inverter has an inverter input coupled to the receiver output and an inverter output coupled to the complementary input of the interlock circuit. The complementary output buffer has a complementary buffer input coupled to the complementary interlock output of the interlock circuit and is configured to output the complementary isolated signal.

[0006] In some embodiments, a digital isolator includes a complementary transmitter having complementary transmitter outputs, a complementary receiver having complementary receiver inputs and complementary receiver outputs, and a complementary output buffer having complementary buffer inputs and configured to output complementary isolated signals. An isolation barrier is further coupled between the complementary transmitter outputs and the complementary receiver inputs. The complementary transmitters are configured to transmit the complementary input signals across the isolation barrier.

[0007] The interlock circuit has a complementary interlock input coupled to the complementary receiver output and a complementary interlock output coupled to the complementary buffer input. The multi-channel digital isolator may also include a dead time insertion circuit configured to insert a dead time between a falling edge of the first isolated signal and a rising edge of the complementary isolated signal or between a rising edge of the first isolated signal and a falling edge of the complementary isolated signal.

[0008] In some embodiments, the interlock circuit includes an exclusive-OR (XOR) logic gate, a first AND logic gate, and a second AND logic gate. The XOR logic gate has a first input coupled to an interlock input, a second input coupled to a complementary interlock input, and an XOR output. The first AND logic gate has a first input coupled to the interlock input, a second input coupled to the exclusive-OR output, and an output coupled to the interlock output. The second AND logic gate has a first input coupled to the complementary interlock input, a second input coupled to the exclusive-OR output, and an output coupled to the complementary interlock output.

[0009] In some embodiments, the output buffer includes a buffer output, and the complementary output buffer includes a complementary buffer output. The interlock circuit has a feedback input coupled to the complementary buffer output and a complementary feedback input coupled to the buffer output. The interlock circuit includes a first AND logic gate and a second AND logic gate. The first AND logic gate has an input coupled to the interlock input, an inverting input coupled to the feedback input, and an output coupled to the interlock output. The second AND logic gate has an input coupled to the complementary interlock input, an inverting input coupled to the complementary feedback input, and an output coupled to the complementary interlock output.

[0010] In some implementations, a digital isolator can include a dead time insertion circuit. The dead time insertion circuit has a first dead time input coupled to a complementary buffer output, a second dead time input coupled to the buffer output, a first dead time output coupled to a feedback input, and a second dead time output coupled to the complementary feedback input. The dead time insertion circuit includes a first delay circuit having an input coupled to the first dead time input and an output coupled to the first dead time output, and a second delay circuit having an input coupled to the second dead time input and an output coupled to the second dead time output.

[0011] In some embodiments, the output buffer has a buffer output and the complementary output buffer has a complementary buffer output. The interlock circuit has a feedback input coupled to the complementary buffer output and a complementary feedback input coupled to the buffer output. The interlock circuit includes an exclusive-OR logic gate, a first and-AND logic gate, and a second and-AND logic gate. The XOR logic gate has a first input coupled to the interlock input, a second input coupled to the complementary interlock input, and an XOR output.

[0012] The first AND logic gate has a first input coupled to the interlock input, a second input coupled to the XOR output, a first inverting input coupled to the feedback input, and an output coupled to the interlock output. The second AND logic gate has a third input coupled to the complementary interlock input, a fourth input coupled to the XOR output, a second inverting input coupled to the complementary feedback input, and an output coupled to the complementary interlock output. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] To describe various examples in detail, reference will now be made to the accompanying drawings, in which:

[0014] Figure 1A is a block diagram illustrating an example motor system with an isolator.

[0015] Figure 1B and Figure 1C It is an explanation Figure 1A A timing diagram of the control signals within the example motor system is shown.

[0016] Figure 2A and Figure 2B is a block diagram of an example of a multi-channel isolator with integrated interlock circuitry.

[0017] Figure 3A 、 Figure 3B and Figure 3C It is used to implement Figure 2B Circuit diagram of an example logic circuit for a multi-channel isolator with an interlock circuit as shown in FIG.

[0018] Figure 4A is a circuit diagram of an example logic circuit for a multi-channel isolator having an interlock circuit and a dead time insertion circuit;

[0019] Figure 4B is used for Figure 4A A circuit diagram of an example delay circuit of a multi-channel isolator;

[0020] Figure 4C yes Figure 4A Timing diagram of the input and output signals of a multi-channel isolator.

[0021] Figure 5 is a circuit diagram of an example logic circuit for a multi-channel isolator having an interlock circuit and a dead time insertion circuit, and Figure 3A-3C and Figure 4A The number of input pins is reduced compared to the example.

[0022] The same reference numbers are used in the drawings to indicate the same or similar (by function and / or structure) features. DETAILED DESCRIPTION

[0023] The described digital isolator includes an interlock circuit configured to prevent overlap between complementary pulse-width modulation (PWM) control signals input to and output from the isolator. The circuitry of some example embodiments corrects for software faults and faults in signal transmission across the isolation barrier and the traces carrying the PWM control signals output from the isolator. Additionally, the circuitry of some example embodiments occupies less area than conventional isolators and interlock circuits. In some examples, the digital isolator receives a single-ended PWM control signal and generates a complementary PWM control signal.

[0024] Figure 1A is a block diagram of a motor system 100 having an isolator 120 that isolates a voltage / ground on one side of the isolation from a voltage / ground on the other side of the isolation. Depending on the type of isolation used for the isolation 120, in order for a signal (or voltage) to pass through the isolation, it is modulated. Figure 1B and Figure 1C is a timing diagram of control signals within the motor system 100 . Figure 1A The illustrated motor system 100 includes a digital controller 110, an isolator 120, a power drive 130, and a motor 140. Any suitable type of motor may be used for the motor 140, such as a single-phase motor, a multi-phase motor (e.g., a three-phase motor), an AC induction motor, a permanent magnet synchronous motor, etc.

[0025] The controller 110 outputs the PWM control signals A0 and B0 to the isolator 120, which galvanically isolates the digital controller 110 from the power drive 130 and the motor 140 to convert the voltage levels to prevent destructive ground loops and / or electrical safety of any system users from high voltages. For example, the isolator 120 isolates the voltage level of the digital power supply voltage (e.g., 3.3 volts) for the PWM control signals A0 and B0 from the power supply voltage (e.g., 565 volts) for the isolated PWM control signals A1 and B1. The isolator 120 outputs the isolated PWM control signals A1 and B1 to the power drive 130 that drives the motor 140. An example of an isolator 120 is shown in FIG. Figure 2A-2B 、 Figure 3A-3C and Figure 4A The power driver 130 includes gate drivers 134 and 138 and transistors Q1 and Q2.

[0026] Transistors Q1-Q2 are bipolar junction transistors (BJTs), such as insulated gate bipolar transistors (IGBTs). In this example, Q1-Q2 are NPN-type BJTs. In other examples, one or more of Q1-Q2 are PNP-type BJTs or metal oxide semiconductor field effect transistors (MOSFETs). The BJT includes a base corresponding to the gate terminal of the MOSFET, and a collector and emitter corresponding to the drain and source terminals of the MOSFET. The base of the BJT and the gate terminal of the MOSFET are control inputs. The collector and emitter of the BJT and the drain and source terminals of the MOSFET are current terminals. In some examples, the current through Q1-Q2 can be as large as 500 amperes. In some example embodiments, there can be multiple Q1 transistors connected in parallel and multiple Q2 transistors connected in parallel.

[0027] Gate drivers 134 and 138 each have an input and an output. The output of isolator 120, which provides an isolated PWM control signal A1, is coupled to the input of gate driver 134, and the output of gate driver 134 is coupled to the base terminal of Q1. The collector of Q1 is coupled to a power supply voltage rail VDD 105 (e.g., 565 volts), and the emitter of Q1 is coupled to the output of power driver 130 and the collector of Q2. The output of isolator 120, which provides an isolated PWM control signal B1, is coupled to the input of gate driver 138, and the output of gate driver 138 is coupled to the base terminal of Q2. The emitter of Q2 is coupled to ground 190. Power driver 130 is a half-bridge driver in this example, but any suitable power driver may be used, such as a full-bridge driver, a two-stage (or more-stage) inverter, etc.

[0028] Isolator 120 outputs an isolated PWM control signal A1 to a first input 132 of a power driver 130 and outputs an isolated PWM control signal B1 to a second input 136 of the power driver 130. Gate driver 134 receives the isolated PWM control signal A1 and switches Q1 on and off in response to the amplitude of the isolated PWM control signal A1. Gate driver 138 receives the isolated PWM control signal B1 and switches Q2 on and off in response to the amplitude of the isolated PWM control signal B1. The output of power driver 130 is coupled to motor 140. Any suitable type of motor may be used, such as an AC induction motor or a permanent magnet synchronous motor.

[0029] Figure 1B-1C A timing diagram of PWM control signals A0 and B0 input to the isolator 120 and isolated PWM control signals A1 and B1 output from the isolator 120 is illustrated. Figure 1B-1CThe schematic diagram in FIG shows that the PWM control signals A0 and B0 and the isolated PWM control signals A1 and B1 are active high, but in other embodiments, the PWM control signals A0 and B0 and the isolated PWM control signals A1 and B1 can be active low. Figure 1B , the timing diagram 150 shows rising edges A0_R and B0_R and falling edges A0_F and B0_F of the PWM control signals A0 and B0 input from the controller 110 to the isolator 120 , respectively.

[0030] The PWM control signals A0 and B0 are configured to prevent shoot-through current in the power driver 130. Therefore, the rising edges A0_R and B0_R are offset from the falling edges A0_F and B0_F (a period of time referred to as "dead time") so that A0 and B0 are not simultaneously active high, and therefore Q1 and Q2 are not simultaneously on. In embodiments where A0 and B0 are active low, the falling edges A0_F and B0_F are offset from the rising edges A0_R and B0_R so that A0 and B0 are not simultaneously active low, and therefore Q1 and Q2 are not simultaneously on.

[0031] Timing diagram 160 shows rising edges A1_R and B1_R and falling edges A1_F and B1_F of isolated PWM control signals A1 and B1, respectively, output from isolator 120 to the first and second inputs of power driver 130. Although timing diagram 150 shows that controller 110 imposes a dead time between the activation of one signal A0 and B0 before the other, a fault in isolator 120 and a fault in the traces of isolated PWM control signals A1 and B1 can cause the falling edge B1_F of B1 to be delayed until after the rising edge A1_R for A1, causing A0 and B0 to be active high at the same time and Q1 and Q2 to be on at the same time, resulting in shoot-through current.

[0032] In implementations where A0 and B0 are active-low, the rising edge B1_R for B1 is delayed until after the falling edge A1_F for A1, causing A1 and B1 to be active-low simultaneously and Q1 and Q2 to be on simultaneously, leading to shoot-through current. For example, common-mode transients can cause isolator 120 to incorrectly interpret the isolated PWM control signals A1 and B1. As another example, parasitic capacitance in the traces of the isolated PWM control signals A1 and B1 can introduce a delay that causes A1 and B1 to overlap.

[0033] In addition to hardware faults in the isolator 120 and the traces, software faults in the controller 110 may cause the controller 110 to output overlapping control signals A0 and B0. Figure 1CIn the example, timing diagram 170 shows that the falling edge B0_F for B0 occurs after the rising edge A0_R for A0, and timing diagram 180 illustrates the isolated PWM control signals A1 and B1 output from isolator 120, which exhibit the same error: the falling edge B1_F for B1 occurs after the rising edge A1_R for A1. As a result, Q1 and Q2 are turned on simultaneously, generating a shoot-through current. Any software and / or hardware fault may cause shoot-through current and damage and / or degrade the performance of power drive 130 and / or motor 140. In the depicted embodiment, interlock circuitry is included in isolator 120 to prevent A1 and B1 from being logic high at the same time.

[0034] For example, to drive a three-phase motor, the power driver 130 includes a half-bridge driver for each phase of the motor and thus receives three pairs of isolated PWM control signals. Therefore, the isolator 120 provides a first pair of isolated PWM control signals A1 and B1, a second pair of isolated PWM control signals C1 and D1, and a third pair of isolated PWM control signals E1 and F1. Figure 2A-2B Multi-channel isolators 120A and 120B are each illustrated with an integrated interlock circuit 250. Thus, the interlock circuit 250 is located on the same semiconductor die as the multi-channel isolators 120. Each isolator 120 includes an isolation barrier 220 that separates a logic side 210 from an isolated side 230. The isolation barrier 220 can be implemented using a transformer, an optocoupler, capacitive isolation, or the like.

[0035] In this example, the multi-channel isolator 120 includes six channels for three channel pairs, but any number of channel pairs may be used. Figure 2A A six-channel isolator 120A is illustrated in which the interlock circuit 250 is arranged on the logic side 210 of the isolation barrier 220. While the isolator 120A can correct software faults that result in overlapping PWM control signals within a channel pair, it does not correct faults caused by the isolation barrier or the traces of the isolated PWM control signals from the isolator 120A to the power driver 130. In contrast, Figure 2B The six-channel isolator 120B includes an interlock circuit 250 disposed on the isolated side 230 of the isolator 120B. The isolator 120B is capable of correcting software faults, as well as faults caused by the isolation barrier and / or, in some embodiments, the traces of the isolated PWM control signals.

[0036] Figure 3A-3C Describes the use Figure 2B An example logic circuit for one channel of a multi-channel isolator 120B with an interlock circuit 250 is shown in FIG. Figure 3A, the isolator 120B includes isolated (ISO) transmitters (TX) 305A and 305B on the logic side 210 of the isolation barrier 220, as well as ISO receivers (RX) 310A and 310B, exclusive OR (XOR) gate 315, AND gates 320A and 320B, and output buffers 330A and 330B on the isolation side 230 of the isolation barrier 220. The ISO TXs 305A-305B receive input PWM control signals A0 and B0, respectively, and transmit them to the ISO RXs 310A-310B, respectively, across the isolation barrier 220. As shown in FIG3 , the ISO RXs 310A-310B output Figure 3A Intermediate signals A and B are shown. For example, ISO TX 305A-305B may be optical transmitters and output optical signals based on input PWM control signals A0 and B0, respectively. ISO RX 310A-310B may be photodiodes and receive optical signals transmitted by ISO TX 305A-305B.

[0037] ISO RX 310A outputs intermediate signal A to first input 320 of XOR gate 315 and first input 345A of AND gate 340A within interlock circuit 250A. ISO RX 310B outputs intermediate signal B to second input 325 of XOR gate 315 and first input 345B of AND gate 340B. Output 330 of XOR gate 315 is coupled to second input 350A of AND gate 340A and second input 350B of AND gate 340B. XOR gate 315 outputs intermediate signal C at a logic high in response to one (but not both) of intermediate signals A or B being at a logic high, indicating that intermediate signals A and B are complementary and do not overlap due to a fault (e.g., one or more software faults introduced within isolator 120B).

[0038] Output 355A of AND gate 340A provides intermediate signal A to input 365A of output buffer 360A outside interlock circuit 250A, while intermediate signal C from XOR gate 315 indicates that intermediate signals A and B do not overlap. Output 370A of output buffer 360A provides isolated PWM control signal A1 to first channel output 375A of isolator 120B. Output 355B of AND gate 340B provides intermediate signal B to input 365B of output buffer 360B outside interlock circuit 250A, while intermediate signal C from XOR gate 315 indicates that intermediate signals A and B do not overlap. Output 370B of output buffer 360B provides isolated PWM control signal B1 to second channel output 375B of isolator 120B.

[0039] Figure 3AThe interlock circuit 250A in can correct one or more software faults introduced in the ISO RX 310A-310B, but does not correct faults caused by the traces of the isolated PWM control signals A1 and B1. In addition, due to the propagation delay of the XOR gate 315, errors may exist in the isolated PWM control signals A1 and B1. Figure 3B In FIG. 2 , the interlock circuit 250B corrects for one or more software faults introduced in the ISO RXs 310A- 310B, as well as faults due to the output buffers 360A- 360B and the traces used to isolate the PWM control signals A1 and B1 . Figure 3B The interlock circuit 250B is omitted Figure 3A XOR gate 315. Conversely, output 370A of output buffer 360A is coupled to inverting input 380B of AND gate 340B and provides isolated PWM control signal A1, and output 370B of output buffer 360B is coupled to inverting input 380A of AND gate 340A and provides isolated PWM control signal B1.

[0040] Output 355A of AND gate 340A provides intermediate signal A to input 365A of output buffer 360A outside interlock circuit 250B while isolated PWM control signal B1 is logic low, thereby preventing errors caused by glitches in output buffers 360A-360B or the traces that isolate PWM control signals A1 and B1. Output 370A of output buffer 360A provides isolated PWM control signal A1 to first channel output 375A of isolator 120B and inverting input 380B of AND gate 340B. Similarly, output 355B of AND gate 340B provides intermediate signal B to input 365B of output buffer 360B outside interlock circuit 250B while isolated PWM control signal A1 is logic low, and output 370B of output buffer 360B provides isolated PWM control signal B1 to second channel output 375B of isolator 120B and inverting input 380A of AND gate 340A.

[0041] If intermediate signals A and B remain at logic high, the non-inverting inputs 345A-345B of AND gates 340A-340B remain logic high. The outputs 355A-355B of AND gates 340A-340B depend on the inverted values ​​of isolated PWM control signals B1 and A1. Propagation delays through output buffers 360A-360B and inverting inputs 380A-380B cause isolated PWM control signals B1 and A1 to switch continuously as they are inverted and input to AND gates 340A-340B.

[0042] Figure 3C The interlock circuit 250C in is similar to Figure 3B The interlock circuit 250B shown in FIG, but also includes Figure 3A XOR gate 315 in interlock circuit 250A shown in FIG2 is used to prevent continuous switching of isolated PWM control signals A1 and B1 if intermediate signals A and B remain at a logic high. Intermediate signal C, output from XOR gate 315, is provided to third non-inverting input 350A of AND gate 390A and third non-inverting input 350B of AND gate 390B. AND gate 390A outputs a logic high only when non-inverting inputs 345A and 350A are at a logic high and inverting input 380A is at a logic low. Therefore, output 355A of AND gate 390A provides intermediate signal A to input 365A of output buffer 360A external to interlock circuit 250C while isolated PWM control signal B1 is at a logic low, and intermediate signal C indicates that only one of intermediate signals A and B is at a logic high.

[0043] Similarly, AND gate 390B outputs a logic high only when non-inverting inputs 345B and 350B are logic high and inverting input 380B is logic low. Thus, output 355B of AND gate 390B provides intermediate signal B to input 365B of output buffer 360B external to interlock circuit 250C while isolated PWM control signal A1 is logic low and intermediate signal C indicates that only one of intermediate signals A and B is logic high. Intermediate signal C, output from exclusive-OR gate 315, is logic high in response to one (but not both) of intermediate signals A or B being logic high, indicating that intermediate signals A and B are complementary and do not overlap due to a fault (e.g., one or more software faults introduced within isolator 120B). If intermediate signals A and B remain logic high, exclusive-OR gate 315 outputs a logic low, effectively gating off the A1 and B1 signals. Figure 3A-3C The logic circuits shown in are examples only, and other logic gates and combinations of logic gates may be used.

[0044] As mentioned above, PWM controllers often insert dead time in the PWM control signals to a pair of transistors to prevent the transistors from being turned on simultaneously, which might otherwise occur due to propagation delays through the system and the fact that the transistors in the power driver turn off more slowly than they turn on. During the dead time, both PWM control signals A1 and B1 are inactive to keep the transistors in the off state (e.g., if the transistors are n-type, such as an NPN BJT or an nMOSFET, then A1 and B1 are logic low, and if the transistors are p-type, such as a PNP BJT or a pMOSFET, then A1 and B1 are logic high).

[0045] Some systems include separate dead-time insertion circuitry, increasing the area and cost of the integrated circuit die. Some systems program the dead-time into the PWM control signals A0 and B0, increasing the complexity of control signal generation. Figures 4A-4CIllustrated is a logic circuit for a multi-channel isolator 120C with an integrated interlock circuit 250 and a dead time insertion circuit 400. In some examples, the dead time insertion circuit 400 is integrated onto the same semiconductor die as the interlock circuit 250 and the multi-channel isolator 120C.

[0046] Figure 4A The isolator 120C shown in FIG. 1 includes a Figure 3C The interlock circuit 250 is shown as the interlock circuit 250C, although it may alternatively be used. Figure 3B or any suitable interlock circuit using A1 and B1 as feedback. In addition to the interlock circuit 250, Figure 4A The isolator 120C shown in FIG. 1 further includes a dead time insertion circuit 400 having two falling edge delay circuits 410A and 410B, which receive the isolated PWM control signals B1 and A1, respectively.

[0047] Input 490A of delay circuit 410A is coupled to output 370B of output buffer 360B, and output 495A of delay circuit 410A is coupled to inverting input 380A of AND gate 390A in interlock circuit 250. Falling-edge delay circuit 410A delays isolated PWM control signal B1 by a configurable dead time, e.g., 10 nanoseconds, and outputs delayed isolated PWM control signal B1_D. Similarly, input 490B of delay circuit 410B is coupled to output 370A of output buffer 360A, and output 495B of delay circuit 410B is coupled to inverting input 380B of AND gate 390B in interlock circuit 250. Falling-edge delay circuit 410B delays isolated PWM control signal A1 by a configurable dead time, e.g., 10 nanoseconds, and outputs delayed isolated PWM control signal A1_D.

[0048] The delayed, isolated PWM control signals A1_D and B1_D ensure that the isolated PWM control signal B1 becomes logic high after the inserted dead time has elapsed from the transition of the isolated PWM signal A1 to logic low, and the isolated PWM control signal A1 becomes logic high after the inserted dead time has elapsed from the transition of the isolated PWM signal B1 to logic high. Figure 4B An example falling edge delay circuit 410 is shown, which can be used to implement Figure 4A Either or both of the falling edge delay circuits 410A or 410B.

[0049] Delay circuit 410 includes transistors M1, M2, M3, and M4, a current source 430, and a capacitor C1 435. In this example, transistors M1 and M3 are P-type MOSFETs (PMOS), and transistors M2 and M4 are N-type MOSFETs (NMOS) (thus forming two inverters, M1 / M2 and M3 / M4). In other examples, one or more of transistors M1 and M3 are NMOS or BJTs, and / or one or more of transistors M2 and M4 are PMOS or BJTs. Current source 430 is coupled to a power supply voltage rail Vcc 415 (e.g., 3.3 volts) and outputs a current Idelay to the source terminal of M1.

[0050] The source terminal of M1 is coupled to the drain terminal of M2, and the source terminal of M2 is coupled to a common potential (e.g., ground) 420. The gate terminals of M1 and M2 are coupled to an input node 425 of a delay circuit 410, which receives the isolated PWM control signal A1 or B1. A first terminal of a capacitor C1 435 is coupled to the source terminal of M1, the drain terminal of M2, and the gates of M3 and M4. A second terminal of capacitor C1 435 is coupled to ground 420. The drain terminal of M3 is coupled to the power supply voltage rail 415, and the source terminal of M3 is coupled to the drain terminal of M4 and an output node 440 of the delay circuit 410, which outputs A1_D or B1_D. The source terminal of M4 is coupled to ground 420.

[0051] The signal (A1 or B1) on input node 425 is provided to the gates of M1 and M2, and the voltage across capacitor C1 435 is provided to the gates of M3 and M4. When the input node signal is logic high, M2 is turned on and M3 is turned off. In this state, any charge on capacitor C1 435 is discharged through M2, so the gate voltages of M3 and M4 are logic low, forcing M4 to turn off and M3 to turn on. With M3 on, the signal on output node 440 is pulsed high to Vcc.

[0052] However, the signal (A1 or B1) at the input node 425 transitions from a logic high to a logic low, causing M1 to turn on and M2 to turn off. With M1 turned on, current from the current source 430 flows to the capacitor C1 435 and charges the capacitor C1 435. The voltage across the capacitor C1 435 then begins to increase linearly. While the voltage across the capacitor C1 435 is still less than the threshold voltage (Vt) of the transistor, M3 remains on and M4 remains off, causing the signal at the output node 440 to remain at a logic high.

[0053] As the voltage across capacitor C1 435 increases above the threshold voltage of M4, M4 turns on and M3 turns off. When M4 turns on, the voltage on output node 440 is pulled to ground 420. Thus, current source 430 and capacitor C1 435 implement a delay between the high-to-low signal transition on the input node and the high-to-low signal transition on output node 440.

[0054] The capacitance of capacitor C1 435 and the current I from current source 430 may be selected DELAY Specifically, by selecting these values, the time it takes for capacitor C1 435 to charge above the threshold voltage is adjusted, thereby changing the delay before the signal at output node 440 becomes logic low. For example, to increase the delay, I can be reduced. DELAY The magnitude of and / or the capacitance of capacitor C1 435 can be increased. To reduce the delay, I DELAY The magnitude of the I2C can be reduced and / or the capacitance of capacitor C1 435 can be reduced. For example, the capacitance of capacitor C1 435 and I2C can be selected to be DELAY The size of is to achieve a 10 nanosecond delay, dead time, in the delayed, isolated PWM output signals A1_D and B1_D. Figure 4A The delay circuits 410A-410B and Figure 4B The delay circuit 410 shown in FIG is a falling edge delay circuit, but any suitable type of delay circuit may be used, such as a rising edge delay circuit, an RC time delay circuit, one or more series coupled flip-flops, etc.

[0055] Figure 4C Shows input to Figure 4A A timing diagram of the isolator 120B and the signals output therefrom is shown, wherein the isolator 120B has the interlock circuit 250 and the dead time insertion circuit 400. Figure 4C The timing diagram in FIG4 shows an example of PWM control signals A0 and B0, and isolated PWM control signals A1 and B1 being active high. However, in other embodiments, PWM control signals A0 and B0 and isolated PWM control signals A1 and B1 can be active low. Timing diagram 450 shows overlapping PWM control signals A0 and B0 input to isolator 120B. The falling edge B0_F of B0 occurs after the rising edge A0_R of A0, for example, due to a software glitch, causing A0 and B0 to be active high at the same time.

[0056] Timing diagram 460 shows the delayed, isolated PWM control signals A1 and B1 output from isolator 120B, correcting for overlapping active-high signals and inserting dead time 470 between B1's falling edge B1_F and A1's rising edge A1_R. In an embodiment where A0 and B0 are active-low, the rising edge B0_R for B0 occurs after the falling edge A0_F for A0, making A0 and B0 simultaneously active-low. In an active-low embodiment, isolator 120B corrects for overlapping active-low signals in A0 and B0 and inserts dead time 470 between B1's rising edge B1_R and A1's falling edge A1_F. The delay introduced by the charging and discharging of capacitor C1 435 and the switching of transistors M1 and M4 in delay circuit 410 also introduces a delay before AND gates 390A-390B output valid signals.

[0057] For example, the isolated PWM logic signal B1 transitions from active to inactive. Without the dead time insertion circuit 400, the inverting input 380A of the AND gate 390A would then transition from inactive to active, and the AND gate 390A would be enabled to output a valid signal if the intermediate signal A is active. With the dead time insertion circuit 400, the delay introduced by the charging of the capacitor C1435 and the switching of the transistors M1-M4 causes the inverting input 380A of the AND gate 390A to continue providing an inactive signal for the length of the inserted dead time (e.g., 10 nanoseconds) before transitioning to active and enabling the AND gate 390A to output a valid signal if the intermediate signal A is active.

[0058] Figure 5 An example logic circuit for one channel of the multi-channel isolator 120B having the interlock circuit 250 and the dead time insertion circuit 400 is illustrated, wherein the number of input pins is reduced. Figure 5 The interlock circuit 250 in is similar to Figure 3B , but instead of receiving the isolated PWM signals B1 and A1, the inverting input 380A of the AND gate 320A receives the delayed, isolated PWM signal B1_D from the falling edge delay circuit 410A in the dead time insertion circuit 400, and the inverting input 380B of the AND gate 320B receives the delayed isolated PWM signal A1_D from the falling edge delay circuit 410B in the dead time insertion circuit 400.

[0059] Figure 5The isolator 120B shown includes one ISO TX 305 and one ISO RX 310, and receives a single PWM control signal A0. The isolator 120B uses an inverter 510 to generate an intermediate signal B on the isolated side of the isolator 120B based on the intermediate signal A. An input 505 of the inverter 510 is coupled to the ISO RX 310, and an output 515 of the inverter 510 is coupled to an input 345B of an AND gate 340B. The inverter 510 outputs the complement of the intermediate signal A as the intermediate signal B.

[0060] The complementary signal B of the input PWM control signal A0 can be generated during the dead time introduced by the dead time insertion circuit 400, reducing the number of input pins on the isolator 120B and the size of the isolator 120B. However, generating the complementary signal B based on the input PWM control signal A0 eliminates the need for independent control of the transistors in the power driver, so the system 100 incorporates additional circuitry on the isolated side of the system to simultaneously turn off both the high-side and low-side transistors.

[0061] As used herein, the term "coupled" may encompass both direct and indirect connections, communications, or signal paths that achieve a functional relationship consistent with this specification. For example, if device A generates a signal to control device B to perform an action: (a) in the first example, device A is coupled to device B via a direct connection; or (b) in the second example, if the intermediate component C does not change the functional relationship between device A and device B, device A is coupled to device B via the intermediate component C, such that device B is controlled by device A via the control signal generated by device A.

[0062] A device that is "configured" to perform a task or function may be configured (e.g., programmed and / or hardwired) by the manufacturer to perform that function at the time of manufacture, and / or may be configured (or reconfigured) by a user after manufacture to perform that function and / or other additional or alternative functions. Configuration may be through firmware and / or software programming of the device, through the construction and / or layout of hardware components and the interconnection of the device, or a combination thereof.

[0063] The use of the phrase "ground voltage potential" in this specification includes chassis ground, earth ground, floating ground, virtual ground, digital ground, common ground, and / or any other form of ground connection that is applicable or suitable for the teachings of this specification. Unless otherwise specified, "about," "approximately," or "substantially" preceding a value means + / - 10% of the stated value.

[0064] As used herein, the terms "terminal," "node," "interconnect," "lead," and "pin" are used interchangeably. Unless specifically stated to the contrary, these terms are generally used to refer to an interconnection or termination between device elements, circuit elements, integrated circuits, devices, or other electronic devices or semiconductor components.

[0065] Circuits or devices described herein as including certain components may alternatively be adapted to be coupled to those components to form the described circuit systems or devices. For example, a structure described as including one or more semiconductor elements (e.g., transistors), one or more passive elements (such as resistors, capacitors, and / or inductors), and / or one or more sources (e.g., voltage and / or current sources) may alternatively include only semiconductor elements within a single physical device (e.g., a semiconductor die and / or integrated circuit (IC) package), and may be adapted to be coupled to at least some of the passive elements and / or sources, for example, by an end user and / or a third party during or after manufacture to form the described structure.

[0066] Although the use of specific transistors is described herein, other transistors (or equivalent devices) may be used instead. For example, a p-type metal oxide silicon field effect transistor ("MOSFET") may be used instead of an n-type MOSFET with little or no change to the circuit. In addition, other types of transistors (e.g., bipolar junction transistors (BJTs)) may be used.

[0067] The circuits described herein may be reconfigured to include additional or different components to provide functionality that is at least partially similar to the functionality that was available prior to component replacement. Unless otherwise noted, components shown as resistors generally represent any one or more elements coupled in series and / or in parallel to provide the amount of impedance represented by the resistor shown. For example, a resistor or capacitor shown and described herein as a single component may instead be multiple resistors or capacitors, respectively, coupled in parallel between the same nodes. For example, a resistor or capacitor shown and described herein as a single component may instead be multiple resistors or capacitors, respectively, coupled in series between the same two nodes as a single resistor or capacitor.

[0068] Modifications to the described embodiments are possible within the scope of the claims, and other embodiments are possible.

Claims

1. A multi-channel digital isolator comprising: Digital isolators, including: a transmitter having a transmitter output; a complementary transmitter having complementary transmitter outputs; a receiver having a receiver input and a receiver output; a complementary receiver having complementary receiver inputs and complementary receiver outputs; an isolation barrier coupled between the transmitter output and the receiver input and also coupled between the complementary transmitter output and the complementary receiver input, the transmitter being configured to transmit an input signal across the isolation barrier and the complementary transmitter being configured to transmit a complementary input signal across the isolation barrier; an output buffer having a buffer input, the output buffer being configured to output an isolated signal; and complementary output buffers having complementary buffer inputs, the complementary output buffers configured to output complementary isolated signals; and an interlock circuit having an interlock input coupled to the receiver output and an interlock output coupled to the buffer input, and further having a complementary interlock input coupled to the complementary receiver output and a complementary interlock output coupled to the complementary buffer input, the interlock circuit being configured to prevent overlapping active states between the isolated signal and the complementary isolated signal, The interlock circuit further comprises: an XOR logic gate having a first input coupled to the interlock input, a second input coupled to the complementary interlock input, and an XOR output; a first AND logic gate having a first input coupled to the interlock input, a second input coupled to the XOR output, and an output coupled to the interlock output; and A second AND logic gate has a first input coupled to the complementary interlock input, a second input coupled to the XOR output, and an output coupled to the complementary interlock output.

2. The multi-channel digital isolator according to claim 1, wherein: The output buffer includes a buffer output, and the complementary output buffer includes a complementary buffer output; The interlock circuit further includes a feedback input and a complementary feedback input; and The multi-channel digital isolator further includes a dead time insertion circuit, wherein the dead time insertion circuit has: a first input coupled to said complementary buffer output, a second input coupled to the buffer output, a first output coupled to the feedback input, and A second output is coupled to the complementary feedback input. 3 . The multi-channel digital isolator of claim 2 , wherein the dead time insertion circuit is configured to insert a dead time between a falling edge of the isolated signal and a rising edge of the complementary isolated signal. 4 . The multi-channel digital isolator of claim 2 , wherein the dead time insertion circuit is configured to insert a dead time between a rising edge of the isolated signal and a falling edge of the complementary isolated signal.

5. A multi-channel digital isolator comprising: Digital isolators, including: a transmitter having a transmitter output; a complementary transmitter having complementary transmitter outputs; a receiver having a receiver input and a receiver output; a complementary receiver having complementary receiver inputs and complementary receiver outputs; an isolation barrier coupled between the transmitter output and the receiver input and also coupled between the complementary transmitter output and the complementary receiver input, the transmitter being configured to transmit an input signal across the isolation barrier and the complementary transmitter being configured to transmit a complementary input signal across the isolation barrier; an output buffer having a buffer input, the output buffer being configured to output an isolated signal; and complementary output buffers having complementary buffer inputs, the complementary output buffers configured to output complementary isolated signals; and an interlock circuit having an interlock input coupled to the receiver output and an interlock output coupled to the buffer input, and further having a complementary interlock input coupled to the complementary receiver output and a complementary interlock output coupled to the complementary buffer input, the interlock circuit being configured to prevent overlapping active states between the isolated signal and the complementary isolated signal, wherein the output buffer comprises a buffer output, and the complementary output buffer comprises a complementary buffer output, the interlock circuit further comprising: a feedback input coupled to the complementary buffer output; a complementary feedback input coupled to the buffer output; a first AND logic gate having an input coupled to the interlock input, an inverting input coupled to the feedback input, and an output coupled to the interlock output; and A second AND logic gate has an input coupled to the complementary interlock input, an inverting input coupled to the complementary feedback input, and an output coupled to the complementary interlock output.

6. The multi-channel digital isolator according to claim 5, further comprising a dead time insertion circuit, wherein the dead time insertion circuit comprises: a first dead time input coupled to the complementary buffer output; a second dead time input coupled to the buffer output; a first dead time output coupled to the feedback input; a second dead time output coupled to the complementary feedback input; a first delay circuit having an input coupled to the first dead time input and an output coupled to the first dead time output; as well as A second delay circuit has an input coupled to the second dead time input and an output coupled to the second dead time output.

7. A multi-channel digital isolator comprising: Digital isolators, including: a transmitter having a transmitter output; a complementary transmitter having complementary transmitter outputs; a receiver having a receiver input and a receiver output; a complementary receiver having complementary receiver inputs and complementary receiver outputs; an isolation barrier coupled between the transmitter output and the receiver input and also coupled between the complementary transmitter output and the complementary receiver input, the transmitter being configured to transmit an input signal across the isolation barrier and the complementary transmitter being configured to transmit a complementary input signal across the isolation barrier; an output buffer having a buffer input, the output buffer being configured to output an isolated signal; and complementary output buffers having complementary buffer inputs, the complementary output buffers configured to output complementary isolated signals; and an interlock circuit having an interlock input coupled to the receiver output and an interlock output coupled to the buffer input, and further having a complementary interlock input coupled to the complementary receiver output and a complementary interlock output coupled to the complementary buffer input, the interlock circuit being configured to prevent overlapping active states between the isolated signal and the complementary isolated signal, wherein the output buffer comprises a buffer output, and the complementary output buffer comprises a complementary buffer output, the interlock circuit further comprising: a feedback input coupled to the complementary buffer output; a complementary feedback input coupled to the buffer output; an XOR logic gate having a first input coupled to the interlock input, a second input coupled to the complementary interlock input, and an XOR output; a first AND logic gate having a first input coupled to the interlock input, a second input coupled to the XOR output, a first inverting input coupled to the feedback input, and an output coupled to the interlock output; and A second AND logic gate has a third input coupled to the complementary interlock input, a fourth input coupled to the XOR output, a second inverting input coupled to the complementary feedback input, and an output coupled to the complementary interlock output.

8. A device comprising: Digital isolators, including: a first transmitter having a first transmitter output; a first receiver having a first receiver input and a first receiver output; a second transmitter having a second transmitter output; a second receiver having a second receiver input and a second receiver output; an isolation barrier coupled between the first transmitter output and the first receiver input and between the second transmitter output and the second receiver input, the first transmitter configured to transmit a first input signal across the isolation barrier, and the second transmitter configured to transmit a second input signal across the isolation barrier; a first output buffer having a first buffer input, the first output buffer configured to output a first isolated signal; and a second output buffer having a second buffer input, the second output buffer configured to output a second isolated signal; and an interlock circuit configured to prevent overlapping active states between the first isolated signal and the second isolated signal, and comprising: an XOR gate having a first XOR input, a second XOR input, and an XOR output, the first XOR input being coupled to the first receiver output and the second XOR input being coupled to the second receiver output; a first AND gate having a first AND input coupled to the first receiver output, a second AND input coupled to the XOR output, and a first AND output coupled to the first buffer input; and A second AND gate has a third AND input coupled to the XOR output, a fourth AND input coupled to the second receiver output, and a second AND output coupled to the second buffer input.

9. The apparatus according to claim 8, wherein: The first output buffer includes a first buffer output, and the second output buffer includes a second buffer output; The first AND gate also has a fifth AND input; The second AND gate also has a sixth AND input; and The apparatus further includes a dead time insertion circuit, wherein the dead time insertion circuit has: a first dead time input coupled to the second buffer output; a second dead time input coupled to the first buffer output; a first dead time output coupled to the fifth AND input; as well as A second dead time output is coupled to the sixth AND input. 10 . The apparatus of claim 9 , wherein the dead time insertion circuit is configured to insert a dead time between a falling edge of the first isolated signal and a rising edge of the second isolated signal. 11 . The apparatus of claim 9 , wherein the dead time insertion circuit is configured to insert a dead time between a rising edge of the first isolated signal and a falling edge of the second isolated signal.

12. A digital isolator having a complementary pair of channels, comprising: The first channel comprises: a first receiver having a first receiver output and configured to receive a first input signal across the isolation barrier; and a first output buffer having a first buffer input and configured to output a first isolated signal; and The second channel includes: a second receiver having a second receiver output and configured to receive a second input signal across the isolation barrier; and a second output buffer having a second buffer input and configured to output a second isolated signal; and an interlock circuit having a first input coupled to the first receiver output, a second input coupled to the second receiver output, a first output coupled to the first buffer input, and a second output coupled to the second buffer input, the interlock circuit being configured to prevent overlapping active states between the first isolated signal and the second isolated signal, Wherein the interlock circuit comprises: a first feedback input and a second feedback input; a first AND logic gate having a first input coupled to the first input of the interlock circuit, a first inverting input coupled to the first feedback input, and a first output coupled to the first output of the interlock circuit; and A second AND logic gate has a second input coupled to the second input of the interlock circuit, a second inverting input coupled to the second feedback input, and a second output coupled to the second output of the interlock circuit.

13. The digital isolator of claim 12, wherein: The first output buffer includes a first buffer output, and the second output buffer includes a second buffer output; and The digital isolator further includes a dead time insertion circuit, wherein the dead time insertion circuit has: a first dead time input coupled to the second buffer output; a second dead time input coupled to the first buffer output; a first dead time output coupled to the first feedback input; as well as A second dead time output is coupled to the second feedback input.

14. The digital isolator of claim 13 , wherein the dead time insertion circuit comprises: a first delay circuit having an input coupled to the first dead time input and an output coupled to the first dead time output; as well as A second delay circuit has an input coupled to the second dead time input and an output coupled to the second dead time output.

15. A digital isolator having a complementary pair of channels, comprising: The first channel comprises: a first receiver having a first receiver output and configured to receive a first input signal across the isolation barrier; and a first output buffer having a first buffer input and configured to output a first isolated signal; and The second channel includes: a second receiver having a second receiver output and configured to receive a second input signal across the isolation barrier; and a second output buffer having a second buffer input and configured to output a second isolated signal; and an interlock circuit having a first input coupled to the first receiver output, a second input coupled to the second receiver output, a first output coupled to the first buffer input, and a second output coupled to the second buffer input, the interlock circuit being configured to prevent overlapping active states between the first isolated signal and the second isolated signal, Wherein the interlock circuit comprises: an XOR logic gate having a first input coupled to the first input of the interlock circuit, a second input coupled to the second input of the interlock circuit, and an XOR output; a first AND logic gate having a first input coupled to the first input of the interlock circuit, a second input coupled to the XOR output, a third inverting input coupled to a first feedback input, and an output coupled to the first output of the interlock circuit; and a second AND logic gate having a fourth input coupled to the second input of the interlock circuit, a fifth input coupled to the XOR output, a sixth inverting input coupled to a second feedback input, and an output coupled to the second output of the interlock circuit.

16. A motor driver having an output adapted to be coupled to a motor, the motor driver comprising: The multi-channel digital isolator according to any one of claims 1 to 7; or The device according to any one of claims 8 to 11; or A digital isolator according to any one of claims 12 to 15.

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