Training method of graph neural network using ternary content addressable memory and memory device applying same
By adopting the TCAM graph neural network training method, combined with an adaptive data reuse strategy and a dynamic fixed-point format, the feature acquisition, aggregation, and update stages are optimized, solving the problem of large data migration in in-memory computing technology and improving training efficiency and accuracy.
Patent Information
- Application Number
- CN202210262398.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Priority Date
- 2022-03-04
- Filing Date
- 2022-03-17
- Publication Date
- 2026-01-23
- Estimated Expiration
- 2042-03-17
AI Technical Summary
Existing in-memory computing technologies involve a large amount of data migration during training, which leads to reduced computing speed and insufficient training efficiency.
A graph neural network training method using a three-state content-addressable memory (TCAM) is adopted. By combining an adaptive data reuse strategy, a TCAM data processing strategy, and a dynamic fixed-point format, the amount of data migration is reduced and the training efficiency is improved through optimization of the feature acquisition, aggregation, and update stages.
It effectively reduces the amount of data migration, maintains training accuracy, and improves the training efficiency of in-memory computing technology.
Smart Images
Figure CN116167405B_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present disclosure relates to a training method of a graph neural network employing a ternary content addressable memory and a memory device applying the same, and in particular, to a training method of a graph neural network employing a ternary content addressable memory and a memory device applying the same. BACKGROUND
[0002] With the development of artificial intelligence technology, computing in memory technology has been applied to system-on-chip (SoC). Computing in memory technology can accelerate the training and recognition of artificial intelligence algorithms. Therefore, computing in memory technology has become an important research and development direction.
[0003] However, when training through memory, a large amount of data migration can reduce the operation speed. Researchers are working to improve the training efficiency of computing in memory technology. SUMMARY
[0004] The present disclosure relates to a training method of a graph neural network employing a ternary content addressable memory and a memory device applying the same, and in particular, to a training method of a graph neural network employing a ternary content addressable memory and a memory device applying the same.
[0005] According to an aspect of the present disclosure, a training method of a graph neural network employing a ternary content addressable memory (TCAM) is provided. The training method of the graph neural network employing the TCAM includes the following steps. Data is extracted from a data set. The graph neural network is trained according to the data of the data set. The step of training the graph neural network includes a feature extraction phase, an aggregation phase, and an update phase. In the aggregation phase, a TCAM crossbar matrix stores a plurality of edges corresponding to a vertex and outputs a hit vector to select part of the edges, and a multiply accumulate (MAC) crossbar matrix stores a plurality of features of the edges to perform a multiply accumulate operation according to the hit vector.
[0006] According to another aspect of the disclosure, a memory device is provided. The memory device includes a controller and a memory array. The memory array is connected to the controller. In the memory array, a ternary content addressable memory (TCAM) crossbar matrix stores a plurality of edges corresponding to a vertex and outputs a hit vector to select a portion of the edges, and a multiply accumulate (MAC) crossbar matrix stores a plurality of features of the edges to perform a multiply accumulate operation according to the hit vector.
[0007] For a better understanding of the above-described and other aspects of the disclosure, example embodiments are hereinafter described in detail with reference to the drawings. BRIEF DESCRIPTION OF DRAWINGS
[0008] Figure 1 An example of a graph applying a graph neural network is illustrated.
[0009] Figure 2 A flowchart of a training method of a graph neural network using a TCAM according to an embodiment is illustrated.
[0010] Figure 3 An example of performing step S110 is illustrated.
[0011] Figure 4 A feature collection stage, an aggregation stage, and an update stage are illustrated.
[0012] Figure 5 A crossbar matrix is illustrated.
[0013] Figure 6 A TCAM crossbar matrix and a multiply accumulate crossbar matrix are illustrated.
[0014] Figures 7-10 The TCAM crossbar matrix and the MAC crossbar matrix are illustrated.
[0015] Figures 11-13 Multiple batches of the TCAM crossbar matrix and the MAC crossbar matrix are illustrated.
[0016] Figure 14 A pipeline operation architecture of a TCAM data processing strategy is illustrated.
[0017] Figure 15 A dynamic fixed-point format is illustrated.
[0018] Figure 16 A booting method is illustrated.
[0019] Figure 17 Explain the graph partitioning method.
[0020] Figure 18 Explain the non-uniform pull boot method.
[0021] Figure 19 Draw a flowchart of an adaptive data reuse strategy according to an embodiment.
[0022] Figure 20 Draw a memory device using the above training method.
[0023] Explanation of reference numerals
[0024] 900: data set
[0025] 1000: memory device
[0026] 100: controller
[0027] 200: memory array
[0028] a1, a2, a3: coefficient
[0029] A3111, A3211, A3121, A3221, A3112, A3212, A3122, A3222: memory area
[0030] B1, B2, Bk, BC1, BC2, BC3, BC4, BC11, BC12, BC13, BC21, BC22, BC23, BCq: batch
[0031] BL1, BL2, BL3: bit line
[0032] egij, eg111, eg121, eg212, eg222, eg11, eg21: edge line
[0033] G0, G1: group
[0034] GP: graph
[0035] HV, HV1, HV2, HVt: hit vector
[0036] L0, L1: level
[0037] MX: crossbar matrix
[0038] MX1, MX21, MX311, MX312, MX41, MXm1: TCAM crossbar matrix
[0039] MX2, MX22, MX321, MX322, MX42, MXm2: MAC crossbar matrix
[0040] Nj, N1, N2, N3, N4, N5, N6, N8, N11, N12, N13, N14, N21, N22, N23, N24, N25, N31, N32, N33, N34: node
[0041] P1: feature collection phase
[0042] P2: aggregation phase
[0043] P3: update phase
[0044] pt21, pt22: segment
[0045] S110, S111, S112, S113, S114, S115, S120: step
[0046] SV1, SV2, SV3, SV4, SVt: search vector
[0047] T1, T2, T3: time point
[0048] u1, u2, u11, u12, u21, u22: node
[0049] U11, U12, U21, U22: feature
[0050] U1(1), U2(1), v1, v2, v3: product and result
[0051] VTi, VT1, VT31, VT32, VT33, VT34, VT35, VT36: vertex
[0052] WL1, WL2, WL3: word line
[0053] wt1, wt2: weight
[0054] X1, X2, X3: node
[0055] x11, x12, x13, x21, x22, x23, x31, x32, x33: feature DETAILED DESCRIPTION
[0056] In an embodiment of the present disclosure, a training method of a graph neural network employing a ternary content addressable memory (TCAM) is provided. Please refer to Figure 1This diagram illustrates an example of a graph GP (Graph Generalized System) applying a graph neural network. A graph GP consists of multiple vertices (VTi) and multiple nodes (Nj). Vertices (VTi) and nodes (Nj) can represent individuals, organizations, or departments. The edges between vertices (VTi) and nodes (Nj) store their features. Graph neural networks can be used to identify or analyze the relationships between two vertices (VTi).
[0057] The training method for graph neural networks using TCAM can improve the training efficiency of in-memory computing techniques. Please refer to [link / reference]. Figure 2 The diagram illustrates a flowchart of a training method for a graph neural network using TCAM according to an embodiment. In step S110, data is extracted from a dataset 900. Please refer to... Figure 3 This illustrates an example of executing step S110. Figure 3 In this process, multiple batches of BCq are used to perform several iterations of the training steps.
[0058] In step S120, the graph neural network is trained based on the data in dataset 900. Step S120 includes a feature extraction phase P1, an aggregation phase P2, and an update phase P3. Please refer to... Figure 4 This describes the feature acquisition phase (P1), aggregation phase (P2), and update phase (P3). In feature acquisition phase P1, features are acquired from edges and nodes. In aggregation phase P2, several operations, such as multiplying and summing, are performed. In update phase P3, the weights are updated. Aggregation phase P2 is a dense input / output operation, which can easily lead to a large amount of data transfer; therefore, the bottleneck in training efficiency usually occurs in aggregation phase P2.
[0059] To improve training efficiency, an adaptive data reusing policy was adopted in step S110, which extracts data from dataset 900. Furthermore, the TCAM data processing strategy and dynamic fixed-point formatting were employed in the aggregation phase P2. The TCAM data processing strategy and dynamic fixed-point formatting will be explained first, followed by the adaptive data reusing policy.
[0060] The TCAM data processing strategy applied in the aggregation stage P2 includes an intra-vertex parallelism architecture and an inter-vertex parallelism architecture. Please refer to Figure 5 which illustrates a crossbar matrix MX. In this embodiment, a plurality of features x11, x12, x13, x21, x22, x23, x31, x32, x33 can be stored in the crossbar matrix MX. The crossbar matrix MX is, for example, a resistive random-access memory (ReRAM). The crossbar matrix MX includes a plurality of word lines WL1, WL2, WL3, a plurality of bit lines BL1, BL2, BL3, and a plurality of storage units. The storage units store the features x11, x12, x13, x21, x22, x23, x31, x32, x33, instead of storing weights. In the aggregation stage P2, a plurality of coefficients a1, a2, a3 are input to the word lines WL1, WL2, WL3, and a plurality of product-sum results v1, v2, v3 can be obtained from the bit lines BL1, BL2, BL3. 0 or 1 can be used to select any node X1, X2, X3. As shown in Figure 4 [1, 0, 1] is a hit vector HV that selects the nodes X1, X3.
[0061] Please refer to Figure 6 which illustrates a TCAM crossbar matrix MX1 and a MAC crossbar matrix MX2. In the aggregation stage P2, the TCAM crossbar matrix MX1 stores a plurality of edges eg111, eg121, eg212, eg222, … corresponding to the vertex VT1 and outputs a hit vector HV that selects partial edges eg111, eg121, eg212, eg222, …. The edge eg111 includes a source node u11 and a destination node u1. The edge eg121 includes a source node u12 and a destination node u1. The edge eg212 includes a source node u21 and a destination node u2. The edge eg222 includes a source node u22 and a destination node u2.
[0062] Under the intra-vertex parallelism architecture, the MAC crossbar matrix MX2 stores features U11, U12, U21, U22, … of the edges eg111, eg121, eg212, eg222, … to perform product-sum operations according to the hit vector HV. The following illustrates a plurality of examples by diagrams.
[0063] Please refer to Figures 7-10 which illustrates the TCAM crossbar matrix MX1 and the MAC crossbar matrix MX2. As shown inFigure 7 As shown, a search vector SV1 is input to the TCAM cross-link matrix MX1. The content of search vector SV1 is the target node u1. The target node u1 of edge eg111 matches the search vector SV1, so the output is 1. The target node u1 of edge eg121 matches the search vector SV1, so the output is 1. The target node u2 of edge eg212 does not match the search vector SV1, so the output is 0. The target node u2 of edge eg222 does not match the search vector SV1, so the output is 0. Therefore, the hit vector HV1 with the content [1, 1, 0, 0] is input to the MAC cross-link matrix MX2.
[0064] The hit vector HV1 is input to the MAC crossbar matrix MX2 to select features U11 and U12. For example... Figure 7 As shown, a product sum result U1(1) was obtained (product sum result U1(1) = feature U11 + feature U12).
[0065] like Figure 8 As shown, a search vector SV2 is input to the TCAM cross-link matrix MX1. The content of search vector SV2 is the target node u2. The target node u1 of edge eg111 does not match the search vector SV2, so the output is 0. The target node u1 of edge eg121 does not match the search vector SV2, so the output is 0. The target node u2 of edge eg212 matches the search vector SV2, so the output is 1. The target node u2 of edge eg222 matches the search vector SV2, so the output is 1. Therefore, the hit vector HV2 with the content [0, 0, 1, 1] is input to the MAC cross-link matrix MX2.
[0066] The hit vector HV2 is input to the MAC crossbar matrix MX22 to select features U21 and U22. For example... Figure 8 As shown, the product sum result U2(1) was obtained (product sum result U2(1) = feature U21 + feature U22).
[0067] like Figure 9As shown, a TCAM cross-link matrix MX21 can also store vertices VT1, ..., levels L0, L1, ... and edges eg11, eg21. Edges eg111, eg121, eg212, eg222 correspond to vertices VT1 and levels L0. Edges eg11, eg21 correspond to vertices VT1 and levels L1. A search vector SV3 is input to the TCAM cross-link matrix MX21. The content of the search vector SV3 is vertex VT1 and level L0. Vertex VT1, level L0, and their corresponding edges eg111, eg212 match the search vector SV3, so the output is 1. Vertex VT1, level L0, and their corresponding edges eg121, eg222 match the search vector SV3, so the output is 1. Vertex VT1, level L1, and their corresponding edge eg11 do not match the search vector SV3, so the output is 0. Vertex VT1, level L1, and their corresponding edge eg21 do not match the search vector SV3, so the output is 0. Therefore, the hit vector HV3 with the content [1, 1, 0, 0] is output to the MAC crossbar matrix MX22.
[0068] The hit vector HV3 is input to the MAC crossbar matrix MX22 to select features U11 and U21, and features U12 and U22. For example... Figure 9 As shown, the product and results U1(1) and U2(1) were obtained.
[0069] like Figure 10 As shown, the MAC cross-link matrix MX22 also stores the product and results U1(1) and U2(1) corresponding to edges eg11 and eg21. A search vector SV4 is input to the TCAM cross-link matrix MX21. The content of the search vector SV4 is vertex VT1 and level L1. Vertex VT1, level L0 and the corresponding edges eg111 and eg212 do not match the search vector SV4, so the output is 0. Vertex VT1, level L0 and the corresponding edges eg121 and eg222 do not match the search vector SV4, so the output is 0. Vertex VT1, level L1 and the corresponding edge eg11 match the search vector SV4, so the output is 1. Vertex VT1, level L1 and the corresponding edge eg21 match the search vector SV4, so the output is 1. Therefore, the hit vector HV4 with the content [0, 0, 1, 1] is output to the MAC cross-link matrix MX22.
[0070] The hit vector HV4 is input to the MAC crossbar matrix MX22 to select the product and results U1(1) and U2(1). Figure 10 As shown, the product and result were obtained.
[0071] In one embodiment, under the inter-vertex parallel computation architecture, the TCAM crossbeam matrix MX21 can also store the edge corresponding to another vertex. The search vector can be used to select vertices.
[0072] As mentioned above, under the inter-vertex parallel operation architecture, the bank / matrix level parallel architecture can be applied to the aggregate operation of different vertices. Under the intra-vertex parallel operation architecture, the width of the crossbar matrix can be efficiently utilized to distribute the aggregate operation.
[0073] Please refer to Figures 11-13 which illustrates the TCAM crossbar matrices MX311, MX312, … and the MAC crossbar matrices MX321, MX322, … of multiple batches B1, B2, …, Bk. As shown in Figure 11 , the multiple TCAM crossbar matrices MX311, MX312, … and the multiple MAC crossbar matrices MX321, MX322, … are arranged in multiple memory banks. For batch B1, the memory region A3111 is used to store the edges of vertex VT31, and the memory region A3211 is used to store the features of vertex VT31. The memory region A3121 is used to store the edges of vertex VT32, and the memory region A3221 is used to store the features of vertex VT32.
[0074] As shown in Figure 12 , for batch B2, the memory region A3112 is used to store the edges of vertex VT33, and the memory region A3212 is used to store the features of vertex VT33. The memory region A3122 is used to store the edges of vertex VT34, and the memory region A3222 is used to store the features of vertex VT34.
[0075] As shown in Figure 13 , for batch Bk, the memory region A3111 is used to store the edges of vertex VT35, and the memory region A3211 is used to store the features of vertex VT35. The memory region A3121 is used to store the edges of vertex VT36, and the memory region A3221 is used to store the features of vertex VT36. That is, the same memory region can be reused for different vertices, so that the memory can be efficiently utilized.
[0076] In some cases, the width of the MAC crossbar matrix may not be enough to store the features of a node or a vertex. In order to avoid speed degradation, a pipeline operation architecture can be used here. Please refer to Figure 14 which illustrates the pipeline operation architecture of the TCAM data processing strategy. As shown in Figure 14As shown, feature U11 is divided into two segments, pt21 and pt22, and stored in two columns. Edge line eg111 is stored in two columns of the TCAM crossbeam matrix MX41. The segments pt21 and pt22 are arranged independently. At time point T1, aggregation phase P2 is performed on segment pt21; at time point T2, update phase P3 can begin on segment pt21. At time point T2, aggregation phase P2 is performed on segment pt22; at time point T3, update phase P3 can begin on segment pt22.
[0077] Furthermore, in the aggregation phase P2, a dynamic fixed-point format can be further employed. The weights or features stored in the cross-link matrix may have a floating-point format. In this technique, the weights or features can be stored in the cross-link matrix using a dynamic fixed-point format. Please refer to... Figure 15 This describes the dynamic fixed-point format. As shown in Table 1, weights can be represented in floating-point format.
[0078] Table 1
[0079] Weight Floating point format Mantissa Exponent 0.2165 1.10111011x2^-3 10111011 2^-3 0.214 1.10110110x2^-3 10110110 2^-3 0.202 1.10011101x2^-3 10011101 2^-3 0.0096 1.00111010x2^-7 00111010 2^-7 0.472 1.11100011x2^-2 11100011 2^-2
[0080] The exponent ranges from 2^-0 to 2^-7. In this embodiment, the exponent can be divided into two groups, G0 and G1. Group G0 ranges from 2^-0 to 2^-3, and group G1 ranges from 2^-4 to 2^-7. For example... Figure 15 As shown, when the exponent falls in group G0, it is stored as "0"; when the exponent falls in group G1, it is stored as "1". To accurately represent "2^-0", the mantissa is shifted by 0 bits. To accurately represent "2^-1", the mantissa is shifted by 1 bit. To accurately represent "2^-2", the mantissa is shifted by 2 bits. To accurately represent "2^-3", the mantissa is shifted by 3 bits. To accurately represent "2^-4", the mantissa is shifted by 0 bits. To accurately represent "2^-5", the mantissa is shifted by 1 bit. To accurately represent "2^-6", the mantissa is shifted by 2 bits. To accurately represent "2^-7", the mantissa is shifted by 3 bits. For example, weight wt1 is "0.2165", its mantissa is "10111011", the last bit "0" indicates group G0, and the mantissa "10111011" is shifted by 3 bits to accurately represent "2^-3". Weight wt2 is "0.472", its mantissa is "11100011", the last bit "0" indicates group G0, and the mantissa "11100011" is shifted by 2 bits to accurately represent "2^-2".
[0081] According to the dynamic fixed-point format, the seven indices are classified into only two groups, G0 and G1, so the number of operation cycles can be reduced from 7 to 2, which greatly increases the operation speed.
[0082] Furthermore, the adaptive data reuse strategy for the 900 samples of the self-dataset in step S110 is further explained below. The adaptive data reuse strategy includes bootstrapping, graph partitioning, and non-uniform bootstrapping.
[0083] Please refer to Figure 16 This describes the bootstrap method. Each batch (BC1, BC2, BC3, BC4) is used for one iteration. Batch BC1 includes data from nodes N1, N2, and N5; batch BC2 includes data from nodes N1, N3, and N6; batch BC3 includes data from nodes N5, N3, and N6; and batch BC4 includes data from nodes N4, N3, and N2. Data from node N1 is reused in both batches BC1 and BC2. Data from node N3 is reused in both batches BC3 and BC4.
[0084] According to the bootstrap method, some data is reused in two batches, so the number of data transfers can be effectively reduced and training efficiency can be improved.
[0085] Please refer to Figure 17 This illustrates the graph segmentation method. In a graph, the graph size (i.e., the total number of nodes) is n, and the batch size (i.e., the number of nodes in a batch) is b. The reuse rate is b / n. If the reuse rate is too low, the bootstrap method will not achieve significant improvement; therefore, the graph needs further segmentation to increase the reuse rate. For example... Figure 17 As shown, the nodes within the graph are randomly divided into 3 partitions. This increases the reuse rate by 3 times. Data from nodes N11 to N145 is placed into batches BC11 to BC13. Data from nodes N12 and N14 is reused in batches BC11 and BC12. Data from nodes N13 and N14 is reused in batches BC12 and BC13.
[0086] Data from nodes N21 to N25 is sorted into batches BC21 to BC23. Data from nodes N23 and N25 is reused in batches BC21 and BC22. Data from node N21 is reused in batches BC22 and BC23.
[0087] According to the graphic segmentation method, the reuse rate can be improved, and even when the graphic is too large, the bootstrap method still has an effective improvement capability.
[0088] Please refer to Figure 18 This illustrates the non-uniform bootstrap method. In the bootstrap method, node data is reused, so some nodes may be sampled multiple times, affecting accuracy. For example... Figure 18As shown, the sampling probability of nodes is set to non-uniform. After several iterations, the number of samples taken from node N8 exceeds the limit, so the sampling probability of node N8 is reduced to 0.826% (lower than the sampling probabilities of other nodes).
[0089] According to the non-uniform bootstrap method, no node will be oversampled and accuracy can be maintained.
[0090] The aforementioned adaptive data reuse strategies—bootstrap, graph segmentation, and non-uniform bootstrap—can be implemented using the following flowchart. Please refer to... Figure 19 The diagram illustrates a flowchart of an adaptive data reuse strategy according to one embodiment. In step S111, it is determined whether the reuse rate is lower than a predetermined value. If the reuse rate is lower than the predetermined value, the process proceeds to step S112; if the reuse rate is not lower than the predetermined value, the process proceeds to step S113.
[0091] In step S112, the graphic segmentation method is performed.
[0092] In step S113, it is determined whether the number of samples for any node exceeds the limit. If the number of samples for any node exceeds the limit, proceed to step S114; if the number of samples for all nodes does not exceed the limit, proceed to step S115.
[0093] In step S114, the non-uniform bootstrap method is performed.
[0094] In step S115, the (uniform) boot pulling method is performed.
[0095] Furthermore, please refer to Figure 20 The diagram illustrates a memory device 1000 employing the aforementioned training method. The memory device 1000 includes a controller 100 and a memory array 200. The memory array 200 is connected to the controller 100. The memory array 200 includes at least one TCAM cross-link matrix MXm1 and at least one MAC cross-link matrix MXm2. The TCAM cross-link matrix MXm1 stores the edges egij corresponding to a vertex. After receiving the search vector SVt, the TCAM cross-link matrix MXm1 outputs a hit vector HVt to select a subset of edges egij. The MAC cross-link matrix MXm2 stores the features of the edges egij to perform a product sum operation based on the hit vector HVt.
[0096] According to the above embodiments, in the training method of a graph neural network using a TCAM tri-state content-addressable memory, an adaptive data reuse strategy is employed in the sampling step S110, and a TCAM data processing strategy and a dynamic fixed-point format are employed in the aggregation stage P2. Therefore, the amount of data migration can be significantly reduced while maintaining accuracy. The training efficiency of in-memory computing techniques (especially graph neural networks) can be effectively improved.
[0097] In summary, although this disclosure has been presented above with reference to embodiments, it is not intended to limit the scope of this disclosure. Those skilled in the art to which this disclosure pertains can make various modifications and refinements without departing from the spirit and scope of this disclosure. Therefore, the scope of protection of this disclosure shall be determined by the scope defined in the appended claims.
Claims
1. A training method for a graph neural network employing a three-state content-addressable memory, characterized in that, include: Extract data from a dataset; as well as Based on the data in this dataset, the graph neural network is trained, and the steps for training the graph neural network include: In the first feature acquisition stage, features on the edge lines and nodes are acquired. One aggregation stage; and In the first update phase, the weights are updated; In this aggregation phase, a ternary content-addressable memory crossbar matrix stores multiple edges corresponding to a vertex and outputs a hit vector to select portions of these edges. A product sum crossbar matrix stores multiple features of these edges to perform a product sum operation based on the hit vector.
2. The training method for a graph neural network using a three-state content-addressable memory according to claim 1, characterized in that, The three-state content-addressable memory crossbar matrix stores a source node and a destination node for each edge.
3. The training method for a graph neural network using a three-state content-addressable memory according to claim 2, characterized in that, The crossbar matrix also stores multiple edges corresponding to another vertex.
4. The training method for a graph neural network using a three-state content-addressable memory according to claim 1, characterized in that, Each of these features or weights has a mantissa and an index, each index being classified into one of two groups, and each mantissa being offset according to its index.
5. The training method for a graph neural network using a three-state content-addressable memory according to claim 1, characterized in that, In the step of extracting data from the dataset, data from at least one node is reused in two batches.
6. A memory device, characterized in that, include: One controller; as well as A memory array is connected to the controller, wherein in the memory array, a tri-state content-addressable memory crossbar matrix stores a plurality of edges corresponding to at least one vertex and outputs a hit vector to select a portion of these edges, and a product sum crossbar matrix stores a plurality of features of these edges so that the controller performs a product sum operation based on the hit vector.
7. The memory device according to claim 6, characterized in that, The three-state content-addressable memory crossbar matrix stores a source node and a destination node for each edge.
8. The memory device according to claim 7, characterized in that, The crossbar matrix also stores multiple edges corresponding to another vertex.
9. The memory device according to claim 6, characterized in that, Each of these features or weights has a mantissa and an index, each index being classified into one of two groups, and each mantissa being offset according to its index.
10. The memory device according to claim 6, characterized in that, The controller reuses data from at least one node in two batches.