Filtered Envelope Tracking

Abstract

Embodiments of circuits, apparatuses, and methods for envelope tracking are disclosed. In one example, a circuit for envelope tracking may include a digital predistorter that receives an input signal representing a signal to be transmitted. The circuit may also include a filtered envelope tracking generator that receives the input signal and provides one or more output signals. The one or more output signals may include a signal that is a filtered tracking envelope of the input signal. One of the one or more output signals may be provided to the digital predistorter. The circuit may also include an envelope tracker that receives the filtered tracking envelope and provides an envelope tracking input to a power amplifier.

Description

Background Art

[0001] Embodiments of the present disclosure relate to apparatuses and methods for filtering envelope tracking.

[0002] Wireless communication systems are widely deployed to provide various telecommunication services such as telephony, video, data, messaging, and broadcasting. In cellular communication, such as 4th-generation (4G) long term evolution (LTE) and 5th-generation (5G) new radio (NR), the 3rd-generation partnership project (3GPP) defines a protocol stack that includes a set of layers collectively referred to as Layer 2: from high to low in the stack are the packet data convergence protocol (PDCP) layer, the radio link control (RLC) layer, and the medium access control (MAC). These layers are above the physical layer (PHY) in the stack. The PHY is also referred to as Layer 1. Data to be transmitted can be generated by an application above the protocol stack, processed through Layer 2 and passed down to Layer 1 processing, and finally transmitted through one or more antennas. Summary of the Invention

[0003] Embodiments of apparatuses and methods for filtering envelope tracking are disclosed herein.

[0004] In one example, a circuit for envelope tracking may include a digital predistorter configured to receive an input signal representing a signal to be transmitted. The circuit may also include a filtered envelope tracking generator configured to receive the input signal and provide one or more output signals. The one or more output signals may include a signal that is a filtered tracking envelope of the input signal. One of the one or more output signals may be provided to the digital predistorter. The circuit may also include an envelope tracker configured to receive the filtered tracking envelope and provide an envelope tracking input to a power amplifier.

[0005] In another example, an envelope tracking method may include receiving an input signal at a digital predistortion. The input signal may represent a signal to be transmitted. The method may further include receiving the input signal at a filtered envelope tracking generator. The method may further include the filtered envelope tracking generator generating one or more output signals. The one or more output signals may include a filtered tracking envelope of the input signal. The method may further include receiving at least one of the one or more output signals at a digital predistorter. The method may further include receiving at least one of the one or more output signals at an envelope tracker. The method may further include providing an envelope tracking input from the envelope tracker to a power amplifier based on at least one of the one or more output signals received at the envelope tracker.

[0006] In another example, a radio frequency chip may include a digital front end that includes a digital predistorter for receiving an input signal representing a signal to be transmitted, wherein the digital front end further includes a filtered envelope tracking generator for receiving the input signal and providing one or more output signals. The one or more output signals may include signals that are filtered tracking envelopes of the input signal. One of the one or more output signals may be provided to the digital predistorter. The radio frequency chip may further include an envelope tracker for receiving the filtered tracking envelope and providing an envelope tracking input to a power amplifier. The radio frequency chip may further include a power amplifier. The power amplifier may be configured to receive the output of the digital predistorter and the filtered tracking envelope. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The drawings incorporated herein and forming a part of the specification illustrate embodiments of the present disclosure, and together with the description further serve to explain the principles of the present disclosure and enable those of ordinary skill in the art to make and use the present disclosure.

[0008] Figure 1A A constant level power tracker is shown.

[0009] Figure 1B A fast or real-time envelope tracker is shown.

[0010] Figure 1C A multi-level envelope tracker is shown.

[0011] Figure 2 A radio frequency (RF) chip according to certain embodiments of the present disclosure is shown.

[0012] Figure 3A A first option of a filtered ET generator according to certain embodiments is shown.

[0013] Figure 3BShows a first option of a filtered ET generator according to certain embodiments.

[0014] Figure 4 Shows a comparison of various tracking methods according to certain embodiments of the present disclosure.

[0015] Figure 5 Shows an envelope tracking method according to certain embodiments of the present disclosure.

[0016] Figure 6 Shows an example node in which some aspects of the present disclosure can be implemented according to certain embodiments of the present disclosure.

[0017] Figure 7 Shows a block diagram of a device including a baseband chip, an RF chip, and a host chip according to certain embodiments of the present disclosure.

[0018] Figure 8 Shows an example wireless network in which some aspects of the present disclosure can be implemented according to certain embodiments of the present disclosure.

[0019] Embodiments of the present disclosure will be described with reference to the accompanying drawings. Detailed Description

[0020] Although specific configurations and arrangements are discussed, it should be understood that this is for illustrative purposes only. Those skilled in the relevant art will recognize that other configurations and arrangements can be used without departing from the spirit and scope of the present disclosure. It will be apparent to those skilled in the relevant art that the present disclosure can also be used in a variety of other applications.

[0021] Note that references in the specification to "an embodiment", "embodiments", "example embodiments", "some embodiments", "certain embodiments", etc. indicate that the described embodiments may include specific features, structures, or characteristics, but each embodiment does not necessarily include the specific features, structures, or characteristics. Moreover, such phrases do not necessarily refer to the same embodiment. Additionally, when a specific feature, structure, or characteristic is described in connection with an embodiment, whether explicitly described or not, implementing such a feature, structure, or characteristic in connection with other embodiments is within the knowledge of those skilled in the relevant art.

[0022] Generally, terms may be understood, at least in part, from their usage in context. For example, the term "one or more" as used herein may be used to describe any feature, structure, or characteristic in a singular sense, or may be used to describe a combination of features, structures, or characteristics in a plural sense, depending at least in part on the context. Similarly, terms such as "a," "an," or "the" may be understood to convey a singular usage or to convey a plural usage, depending at least in part on the context. Additionally, the term "based on" may be understood to not necessarily convey a set of exclusive factors, but may allow for the existence of other factors that are not necessarily expressly described, again depending at least in part on the context.

[0023] Aspects of a wireless communication system will now be described with reference to various apparatus and methods. These apparatus and methods will be described in the detailed description below and illustrated in the drawings by various blocks, modules, units, components, circuits, steps, operations, processes, algorithms, etc. (collectively referred to as "elements"). These elements may be implemented using electronic hardware, firmware, computer software, or any combination thereof. Whether an element is implemented as hardware, firmware, or software depends upon the particular application and design constraints imposed on the overall system.

[0024] The techniques described herein may be used for various wireless communication networks such as code division multiple access (CDMA) systems, time division multiple access (TDMA) systems, frequency division multiple access (FDMA) systems, orthogonal frequency division multiple access (OFDMA) systems, single-carrier frequency division multiple access (SC-FDMA) systems, and other networks. The terms "network" and "system" are often used interchangeably. CDMA networks may implement radio access technologies (RATs) such as universal terrestrial radio access (UTRA), evolved UTRA (E-UTRA), CDMA 2000, etc. TDMA networks may implement RATs such as GSM. OFDMA networks may implement RATs such as LTE or NR. The techniques described herein may be used for the above-mentioned wireless networks and RATs as well as other wireless networks and RATs.

[0025] For example, in an OFDMA communication system including 5G NR, orthogonal frequency division multiplexing (OFDM) is used to provide efficient modulation for wireless communication. In an OFDM transmitter, a group of bits to be transmitted is converted into complex symbols and transformed into a time-domain waveform using, for example, inverse fast Fourier transform (IFFT). The generated digital waveform can be converted into an analog form, amplified, and wirelessly transmitted to a receiver.

[0026] Figure 1A A constant-level power tracker is shown. In this method, a digital front-end circuit (DFEC) 110 may include a crest factor reduction (CFR) circuit 120. The CFR circuit 120 can be used to reduce the peak-to-average-power-ratio (PAPR) of the signal to be transmitted. PAPR reduction can make the operation of the power amplifier more efficient.

[0027] Before the signal is provided to a digital pre-distorter (DPD) 140, a pre-DPD gain (PreDPDGain) amplifier 130 can amplify the signal. Predistortion is a class of techniques that can be used to improve the linearity of wireless transmitter amplifiers such as power amplifiers. If the amplifier is non-linear, an inaccurate representation of the input signal may be produced at the output. To address this non-linearity, the pre-distorter can compensate for the non-linearity such that the input of the pre-distorter is accurately represented by the output of the power amplifier. There may be multiple factors for distortion in a power amplifier, including but not limited to the amount of power used by the amplifier, and higher power levels generally result in greater distortion.

[0028] Meanwhile, a digitally pre-distorted version of the signal can be provided to a pre-digital-to-analog-conversion gain (PreDACGain) amplifier 150 to amplify the signal. A real and imaginary (IQ) digital-to-analog converter (DAC) 160 can convert the signal into an analog signal and provide the analog version of the signal to a power amplifier (PA) 170. The IQ DAC 160 can be included in a radio frequency (RF) – transmission (TX) chip 180.

[0029] The bias voltage Vcc of the power amplifier 170 can be provided by a switched mode power supply (SMPS) 192. The Vcc level is controlled by a Vcc level control 190 via a radio frequency front-end control interface (RFFE) command (not shown). The Vcc level can be kept constant within a symbol. It can change from symbol to symbol to track the power level. This method is called average power tracking (APT). If the Vcc is further reduced to improve the efficiency of the power amplifier 170 and DPDs 140 are used to compensate for the non-linearity of the power amplifier 170, this method can be called enhanced power tracking (EPT). The output of the power amplifier can ultimately be one or more antennas 199.

[0030] Figure 1A The method does not rely on envelope tracking (ET). Envelope tracking is a power tracking technique for improving the efficiency of power amplifiers. The signal to be amplified by the power amplifier may be a complex waveform with a large amount of bandwidth and variability. Appropriate envelope tracking can allow the power amplifier to operate effectively and appropriately.

[0031] The envelope tracker can be designed to immediately track the signal envelope and provide sufficient current to the envelope tracking power amplifier. Typically, the envelope bandwidth is three times the signal bandwidth. For fifth-generation (5G) wireless communications, to support signals with a bandwidth of up to 100 MHz, the envelope tracker typically tracks a one-sided signal of up to 150 MHz. This bandwidth poses various considerations in the design of the envelope tracker. These considerations can include trading efficiency for speed.

[0032] Figure 1B A fast or real-time envelope tracker is shown. This may be referred to interchangeably herein as "fast" or "real-time" because the envelope signal (sometimes simply referred to as the envelope) can be the absolute value of the original signal and thus can follow the original signal precisely and instantaneously. This may be contrasted with a "slow" or "filtered" envelope signal (these terms may also be used interchangeably herein), which, while based on the original signal and forming an envelope of the original signal, may not vary precisely and instantaneously with the original signal. These may be contrasted with a multilevel envelope, which, while not necessarily filtered, may still only track the original signal periodically. As described below, filtering can also be applied to the multilevel envelope, which can result in a slow or filtered envelope signal.

[0033] As Figure 1B shown, the DFEC 110 can include a CFR circuit 120, as Figure 1A shown. Before providing the signal to the DPD 140, the PreDPDGain amplifier 130 can amplify the signal. The ET path element 194 can read the signal before or after digital predistortion, or optionally before and after digital predistortion. The ET path element 194 can provide a fast or real-time tracking version of the signal to the envelope DAC (ENV DAC) 165. The analog output of the ENV DAC 165 can be provided to the continuous envelope tracker 196. In turn, the continuous envelope tracker 196 can provide a higher-amp version of the analog version of the fast-tracking or real-time envelope tracking to the power amplifier 170.

[0034] Meanwhile, also as Figure 1B shown, the digitally predistorted version of the signal can be provided to the PreDACGain amplifier 150 to amplify the signal. The IQ DAC 160 can convert the signal to an analog signal and provide the analog version of the signal to the power amplifier 170. Both the IQ DAC 160 and the ENV DAC 165 can be included in the RF-TX chip 180. The output of the power amplifier can ultimately be one or more antennas 199.

[0035] Figure 1C A multilevel envelope tracker is shown. As Figure 1CAs shown, the DFEC 110 may include a CFR circuit 120 that provides a crest factor reduction signal to a PreDPDGain amplifier 130. The output of the PreDPDGain amplifier 130 may be provided to a multilevel generator 197 and a DPD 140, and the DPD 140 may be a two-dimensional (2D) DPD. The multilevel generator 197 may provide signals to a multilevel envelope tracker 193 and a filtered envelope generator 198. The filtered envelope generator 198 may provide signals to the DPD 140. Otherwise, the multilevel envelope tracker 197 may be similar to the fast or real-time envelope tracker described above with reference to Figure 1B The fast or real-time envelope tracker described above with reference to

[0036] In contrast, some embodiments of the present disclosure slowly track the signal envelope and use more complex digital predistortion to compensate for side effects. In some embodiments, a relatively slow envelope tracker (e.g., a 4G envelope tracker) may provide an ET solution for faster signals (e.g., 5G 100 MHz).

[0037] Figure 2 A system according to some embodiments of the present disclosure is shown. As Figure 2 shown, a signal x(t) to be amplified by a power amplifier 170 may be processed in an RF chip 704 before reaching the power amplifier 170. The RF chip 704 may include a DFEC 110 and an RF-TRX 180, and the DFEC 110 and the RF-TRX 180 may be implemented on the same chip or different chips. Thus, for example, although the RF chip 704 is shown as a single chip, the RF chip 704 may be composed of multiple chips. The filtered ET generator 198 may process the signal and output a slow-tracking signal Vcc(t), which may also be referred to as a filtered tracking signal. It can be understood that through slow tracking, the change rate of the envelope Vcc(t) may not match the change rate of the original signal x(t).

[0038] The original signal x(t) and the filtered tracking signal Vcc(t) may be provided to the DPD 140 to provide a digital predistortion signal to the IQ DAC 160. The IQ DAC 160 may provide an analog signal to the power amplifier 170.

[0039] Meanwhile, the filtered tracking signal Vcc(t) may be provided to the ENV DAC 165. The ENV DAC 165 may provide an analog version of the filtered tracking signal to the ET tracker 210. The ET tracker 210 may generate a higher current version of the filtered tracking signal and provide it to the power amplifier 170. The power amplifier 170 may generate an amplified version of the digital predistortion signal to another RF circuit, ultimately terminating at one or more antennas.

[0040] Figure 2 The filtered ET generator 198 shown can be constructed in a variety of different ways. For example, a fast or real-time envelope tracking signal can be generated and then low-pass filtered to generate a filtered tracking signal. The fast or real-time envelope tracking signal can be the absolute value of the input signal. As an alternative, the filtered tracking signal can be generated by modeling a multi-level envelope tracking signal and then low-pass filtering it. The multi-level envelope tracking signal can generate a discrete stepped signal, but the low-pass filtering can smooth the transitions and reduce switching noise.

[0041] As described above, the filtered envelope tracking signal Vcc(t) can be provided to the ENV DAC 165 to drive the ET tracker 210. The analog signal from the ENV DAC 165 may have a relatively low amperage, but the signal to the power amplifier 170 may require up to 1 ampere - the ET tracker 210 can acquire the weak signal and amplify the signal to send to the power amplifier 170 - the amplified signal may have the same voltage but a higher current, and can be a separate chip. Since the ET tracker 210 only needs to follow a signal with a slower conversion rate to achieve more accurate tracking. Here, the conversion rate may be slower relative to the conversion rate of x(t). Thus, for example, the conversion rate may depend on the low-pass filtering used in the filtered ET generator 198, and the more signals filtered out, the lower the conversion rate may be.

[0042] As described above, the filtered envelope tracking signal Vcc(t) can also be provided to the DPD 140. The DPD 140 can compensate the input signal based on the input signal x(t) and the envelope tracking signal Vcc(t). Thus, the output of the DPD 140 may be based not only on Vcc(t) and the characteristics of the power amplifier 170, but also on the envelope information.

[0043] The DPD 140 can be implemented in different ways. In one example, the DPD 140 can include multiple DPD lookup tables (LUTs) corresponding to multiple traces of Vcc. The DPD 140 can select the closest value or interpolate between adjacent values. The values of Vcc in the lookup table can be various constant voltages (such as 1V, 2V, 3V, etc.).

[0044] In some embodiments, the DPD 140 can receive a discrete stepped signal and can perform low-pass filtering to provide the signal to the ENV DAC 165. This method can simplify the logic design of the DPD 140.

[0045] One effect of low-pass filtering Vcc is to reduce the bandwidth of the resulting signal. This in turn relaxes the requirements on the envelope tracker 210.

[0046] Some embodiments may impose further restrictions on Vcc to prevent Vcc from dropping below a minimum level. For example, the minimum level of Vcc can be set to 1V so that even if the low-pass filtered output drops below 1V, it can be maintained at 1V. As an alternative, the low-pass filtered output can be uniformly offset by 1V so that the output range is not 0 to X volts but 1 to X + 1 volts.

[0047] Figure 3A A first option of a filtered ET generator according to some embodiments is shown. As Figure 3A shown, an absolute value circuit 310 can provide the absolute value of signal x(t), and a low-pass filter 320 can provide a filtered envelope tracking signal Vcc(t). The filtered envelope tracking signal Vcc(t) can be provided to the DPD 140.

[0048] Figure 3B A first option of a filtered ET generator according to some embodiments is shown. As Figure 3B shown, a multilevel generator 197 can provide a step signal based on x(t), and a low-pass filter 320 can provide a filtered envelope tracking signal Vcc(t). The step signal can be provided to the DPD 140. The filtered envelope tracking signal Vcc(t) can also be provided to the DPD 140.

[0049] Figure 4 A comparison of various tracking methods is shown. As Figure 4 shown, a fast or real-time tracking signal 410 can correspond to the absolute value of the input signal. The horizontal axis can represent time, and the vertical axis can represent voltage, with zero voltage and an arbitrary starting time as Figure 4 the lower left corner of the graph in. The multilevel tracking signal 420 can periodically round up the value to the next half-volt level. As shown in this example, the filtered tracking signal 430 can be a low-pass filtered version of the multilevel tracking signal 420. As described above, there are other ways to generate the filtered tracking signal 430. It can be concluded from this graph that although the filtered tracking signal 430 may not precisely align with the absolute value of the original signal, the difference may be relatively small, for example, less than half a volt.

[0050] Figure 5 A method for envelope tracking according to some embodiments is shown. Figure 5 The method can be implemented, for example, by the circuit shown in Figure 2 As Figure 5 shown, one method can include, at 510, receiving an input signal at a digital predistorter, where the input signal represents a signal to be transmitted. This can be Figure 2 the signal x(t) in.

[0051] As Figure 5As shown, the method may further include, at 520, receiving an input signal at a filtered envelope tracking generator. This may also be the same signal x(t).

[0052] The method may further include, at 530, the filtered envelope tracking generator generating one or more output signals. The one or more output signals may include a filtered tracking envelope of the input signal. For example, Figure 2 Vcc(t) in is an example of a filtered tracking envelope of the input signal. The filtered tracking envelope may be a low-pass filtered form of the absolute value of the input signal or a low-pass filtered form of a multi-level stepped representation of the input signal.

[0053] As Figure 5 shown, the method may further include, at 540, receiving at least one of the one or more output signals at a digital pre-distorter. For example, Vcc(t) or an intermediate signal generated during the generation of Vcc(t) may be provided to the digital pre-distorter.

[0054] The method may further include, at 550, receiving at least one of the one or more output signals at an envelope tracker. The ET may be designed to provide a high-current (e.g., up to 1 ampere) version of the filtered tracking envelope.

[0055] Therefore, the method may further include, at 560, providing an envelope tracking input from the envelope tracker to a power amplifier based on at least one of the one or more output signals received at the envelope tracker. The envelope tracking input may be a current amplified version of Vcc(t).

[0056] As described above, the filtered envelope tracking generator may generate the one or more output signals using a fast or real-time envelope tracking generator (e.g., Figure 1B shown) and a low-pass filter. Similarly, as described above, as another alternative, the filtered envelope tracking generator may generate the one or more output signals using a multi-level envelope tracking generator (e.g., Figure 1C shown) and a low-pass filter.

[0057] A first output signal of the one or more output signals may be provided from the multi-level envelope tracking generator, and a second output signal of the one or more output signals may be provided from the low-pass filter. The first output signal may be provided to the digital pre-distorter, while the second output signal may be provided to the envelope tracker. In other words, the DPD may receive an intermediate stage of the ET generator, while the ET may receive a low-pass filtered version.

[0058] The method may further include, at 570, selecting a DPD lookup table. If used, a lookup table corresponding to the current level of the multilevel envelope tracking generator may be selected. As another alternative, the DPD may select a lookup table based on at least one of the one or more output signals provided to the digital predistorter. The LUT may be used in combination with information about the electrical characteristics of the power amplifier to determine the correct amount of predistortion to apply to the signal.

[0059] The method may further include, at 580, maintaining or increasing the voltage level of the ET signal. For example, a voltage regulation circuit or other mechanism may be used to maintain the voltage of the ET signal at a predetermined minimum voltage level or above the predetermined minimum voltage level. As another alternative, a boost circuit or other mechanism may be used to uniformly increase the voltage of the output signal of the ET generator so that the voltage never falls below a certain minimum level.

[0060] The method may further include, at 590, the digital predistorter compensating the input signal based on the characteristics of the power amplifier and the output signal among the one or more output signals from the filtered envelope tracking generator. In some cases, the DPD and the ET receive the same signal, and the ET signal generator outputs only one signal. In other cases, as described above, the ET signal generator may provide an intermediate signal (e.g., the output of the multilevel envelope tracking generator) and a low-pass filtered final signal. Other embodiments are also possible.

[0061] Figure 6 A node according to certain embodiments is shown. As Figure 6 shown, the node 600 may include a processor 602, a memory 604, and a transceiver 606. These components are shown interconnected by a bus 608, but other connection types are also permitted. When the node 600 is a user equipment 802 (see Figure 8 , described below), other components may also be included, such as a user interface (UI), sensors, etc. Similarly, when the node 600 is configured as a core network element 806 (see Figure 8 , described below), the node 600 may be implemented as a blade in a server system. Other implementations are also possible.

[0062] The transceiver 606 may include any suitable device for transmitting and / or receiving data. The transceiver 606 may include the circuitry shown in Figure 2 and may implement Figure 6The method. Although only one transceiver 606 is shown for simplicity of illustration, node 600 may include one or more transceivers. Antenna 610 is shown as a possible communication mechanism for node 600. Multiple antennas and / or antenna arrays may be utilized. Additionally, examples of node 600 may communicate using wired technologies instead of wireless technologies, or may communicate using wireless technologies in addition to wired technologies. For example, access node 804 may communicate wirelessly with user equipment 802 and may communicate with core network element 806 via a wired connection (e.g., via an optical fiber cable or coaxial cable). Other communication hardware such as a network interface card (NIC) may also be included.

[0063] As Figure 6 shown, node 600 may include a processor 602. Although only one processor is shown, it should be understood that multiple processors may be included. Processor 602 may include a microprocessor, a microcontroller, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a programmable logic device (PLD), a state machine, gate logic, discrete hardware circuits, and other suitable hardware for performing the various functions described in this disclosure. Processor 602 may be a hardware device having one or more processing cores. Processor 602 may execute software. Whether referred to as software, firmware, middleware, microcode, hardware description language, or other names, software should be broadly interpreted as instructions, instruction sets, code, code segments, program code, programs, subroutines, software modules, applications, software applications, software packages, routines, subroutines, objects, executable files, execution threads, processes, functions, etc. Software may include computer instructions written in an interpreted language, a compiled language, or machine code. Other techniques for instructing hardware may also fall under the broad category of software. Processor 602 may be a baseband chip, such as Figure 7 the baseband chip 702 in Figure 6 which is not shown. Node 600 may also include other processors not shown, such as the central processing unit, graphics processor, etc. of the device. Processor 602 may include internal memory (also referred to as local memory, Figure 6 not shown in which) that may be used as memory for L2 data. Processor 602 may include, for example, a radio frequency chip integrated in the baseband chip, or a radio frequency chip may be provided separately. Processor 602 may serve as a modem for node 600, or may be an element or component of a modem. Other arrangements and configurations are also permitted.

[0064] As Figure 6 shown, node 600 may also include a memory 604. Although only one memory is shown, it should be understood that multiple memories may be included. Memory 604 may broadly include memory and storage. For example, memory 604 may include random-access memory (RAM), read-only memory (ROM), SRAM, dynamic RAM (DRAM), ferro-electric RAM (FRAM), electrically erasable programmable ROM (EEPROM), CD-ROM, or other optical disc storage, hard disk drive (HDD), such as magnetic disk storage or other magnetic storage devices, flash drive, solid-state drive (SSD), or any other medium that can be used to carry or store the required program code in the form of instructions that can be accessed and executed by processor 602. Generally speaking, memory 604 may be implemented as any computer-readable medium, such as a non-transitory computer-readable medium. Memory 604 may be Figure 7 the external memory 708 in

[0065] Figure 7 A block diagram of a device 700 including a baseband chip 702, a radio frequency chip 704, and a host chip 706 is shown according to some embodiments of the present disclosure. Device 700 may be Figure 8 an example of any suitable node in a wireless network 800 in

[0066] As Figure 7 shown, device 700 may include a baseband chip 702, an RF chip 704, a host chip 706, and one or more antennas 710. In some embodiments, baseband chip 702 is implemented by processor 602 and memory 604, and RF chip 704 is implemented by processor 602, memory 604, and transceiver 606, as described above with respect to Figure 6As described above. In addition to the on-chip memory (also referred to as "internal memory" or "local memory", such as registers, buffers, or caches) on each of the chips 702, 704, or 706, the device 700 may also include an external memory 708 (e.g., system memory or main memory) that can be shared by each of the chips 702, 704, or 706 via the system / master bus. Although the baseband chip 702 is shown as an independent SoC in Figure 7 , it can be understood that, in one example, the baseband chip 702 and the radio frequency chip 704 can be integrated into one SoC; in another example, the baseband chip 702 and the host chip 706 can be integrated into one SoC; in another example, the baseband chip 702, the radio frequency chip 704, and the host chip 706 can be integrated into one SoC, as described above. Thus, for example Figure 2 the circuits shown can be implemented on the radio frequency chip 704 and the baseband chip 702, or on a single chip. Other implementations are possible.

[0067] For transmission (sometimes also referred to as uplink), the host chip 706 can generate raw data and send it to the baseband chip 702 for encoding, modulation, and mapping. The baseband chip 702 can also access the raw data generated by the host chip 706 and stored in the external memory 708, for example, using direct memory access (DMA). The baseband chip 702 can first encode the raw data (e.g., through source coding and / or channel coding) and modulate the encoded data using any suitable modulation technique such as multi-phase pre-shared key (MPSK) modulation or quadrature amplitude modulation (QAM). The baseband chip 702 can perform any other functions such as symbol or layer mapping to convert the raw data into a signal that can be used to modulate the carrier frequency for transmission. In the uplink, the baseband chip 702 can send the modulated signal to the radio frequency chip 704. The RF chip 704 can convert the modulated signal in digital form into an analog signal, i.e., a radio frequency signal, through a transmitter (Tx) and perform any suitable front-end radio frequency functions such as filtering, upconversion, or sample rate conversion. As described above, the RF chip 704 can include components such as RF-TX, DFEC, PA, and ET tracker. Thus, the RF chip 704 can implement Figure 7 the circuits shown and can perform Figure 5 the methods shown, and implement other circuits and other methods. The antenna 710 (e.g., antenna array) can transmit the radio frequency signal provided by the transmitter of the RF chip 704.

[0068] In the downlink, antenna 710 may receive a radio frequency signal and transfer the radio frequency signal to the receiver (Rx) of RF chip 704. RF chip 704 may perform any suitable front-end radio frequency functions, such as filtering, down-conversion, or sample rate conversion, and convert the radio frequency signal into a low-frequency digital signal (baseband signal) that can be processed by baseband chip 702. In the downlink, baseband chip 702 may demodulate and decode the baseband signal to extract the original data that can be processed by host chip 706. Baseband chip 702 may perform other functions, such as error checking, demapping, channel estimation, descrambling, etc. The original data provided by baseband chip 702 may be directly sent to host chip 706 or stored in external memory 708.

[0069] Figure 8 A wireless network according to some embodiments is shown. As Figure 8 shown, wireless network 800 may include a network of nodes, such as UEs 802, access nodes 804, and core network elements 806. User equipment 802 may be any terminal device, such as a mobile phone, a desktop computer, a laptop computer, a tablet computer, an in-vehicle computer, a gaming console, a printer, a positioning device, a wearable electronic device, a smart sensor, or any other device capable of receiving, processing, and sending information, such as any member of a vehicle to everything (V2X) network, a cluster network, a smart grid node, or an Internet of Things (IoT) node. It should be understood that user equipment 802 is shown as a mobile phone by way of illustration and not limitation.

[0070] Access node 804 may be a device that communicates with user equipment 802, such as a wireless access point, a base station (BS), a Node B, an enhanced Node B (eNodeB or eNB), a next-generation NodeB (gNodeB or gNB), a cluster master node, etc. Access node 804 may be wired to user equipment 802, wirelessly connected to user equipment 802, or any combination thereof. Access node 804 may be connected to user equipment 802 through multiple connections, and user equipment 802 may also be connected to other access nodes other than access node 804. Access node 804 may also be connected to other UEs. It should be understood that access node 804 is shown as a radio tower by way of illustration and not limitation.

[0071] The core network element 806 can serve the access node 804 and the user equipment 802 to provide core network services. Examples of the core network element 806 can include a home subscriber server (HSS), a mobility management entity (MME), a serving gateway (SGW), or a packet data network gateway (PGW). These are examples of core network elements of an evolved packet core (EPC) system, which is the core network of an LTE system. Other core network elements can be used in LTE and other communication systems. In some embodiments, the core network element 806 includes an access and mobility management function (AMF) device, a session management function (SMF) device, or a user plane function (UPF) device of the core network of an NR system. It should be understood that the core network element 806 is shown as a set of rack-mounted servers by way of illustration and not limitation.

[0072] The core network element 806 can be connected to a large network such as the Internet 808 or another IP network to transmit packet data over any distance. Thus, data from the user equipment 802 can be transmitted, for example, using a wired connection or a wireless connection to other UEs connected to other access points (including, for example, a computer 810 connected to the Internet 808), or to a tablet 812 wirelessly connected to the Internet 808 via a router 814. Accordingly, the computer 810 and the tablet 812 provide other examples of possible UEs, and the router 814 provides an example of another possible access node.

[0073] A general example of a rack-mounted server is provided as an illustration of the core network element 806. However, there can be multiple network elements in the core network, including database servers, such as database 816, and security and authentication servers, such as authentication server 818. For example, database 816 can manage data related to user subscriptions to network services. A home location register (HLR) is an example of a standardized database of subscriber information in a cellular network. Similarly, authentication server 818 can handle the authentication of users, sessions, etc. In an NR system, an authentication server function (AUSF) device can be a specific entity that performs user equipment authentication. In some embodiments, a single server rack can handle multiple such functions, such that the connections between core network element 806, authentication server 818, and database 816 can be local connections within a single rack.

[0074] Although the above description uses the uplink processing of signals in a UE as an example in various discussions, similar techniques can equally be applied to other processing directions and to processing in other devices such as access nodes and core network nodes. For example, any device that uses a power amplifier to transmit a signal can benefit from some embodiments of the present disclosure even if not specifically listed above or shown in the Figure 8 example network.

[0075] Figure 8 Each network element in the Figure 6 can be considered a node of the wireless network 800. More details regarding possible implementations of a node are provided by way of example in the description of node 600 in the above Figure 8 Node 600 can be configured as Figure 8 user equipment 802, access node 804, or core network element 806 in the

[0076] Similarly, node 600 can also be configured as Figure 6 Figure 8 computer 810, router 814, tablet 812, database 816, or authentication server 818 in the

[0076] In various aspects of the present disclosure, the functions described herein can be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions can be stored on a non-transitory computer-readable medium or encoded as instructions or code on a non-transitory computer-readable medium. A computer-readable medium includes a computer storage medium. The storage medium can be one that can be accessed by, for example, Figure 6Any available medium accessed by computing devices such as node 600 in []. Such computer-readable media can include, for example, but are not limited to, RAM, ROM, EEPROM, CD-ROM, or other optical disc storage, HDD, such as magnetic disk storage or other magnetic storage devices, flash drives, SSDs, or any other medium that can be used to carry or store the required program code in the form of instructions or data structures and can be accessed by a processing system (such as a mobile device or a computer). As used herein, magnetic disks and optical discs include CDs, laser discs, optical discs, DVDs, and floppy disks, where magnetic disks typically reproduce data magnetically, while optical discs reproduce data optically by laser. Combinations of the above should also be included within the scope of computer-readable media.

[0077] According to one aspect of the present disclosure, a circuit for envelope tracking may include a digital predistorter configured to receive an input signal representing a signal to be transmitted. The circuit may further include a filtered envelope tracking generator configured to receive the input signal and provide one or more output signals. The one or more output signals may include a signal that is a filtered tracking envelope of the input signal. One of the one or more output signals may be provided to the digital predistorter. The circuit may further include an envelope tracker configured to receive the filtered tracking envelope and provide an envelope tracking input to a power amplifier.

[0078] In some embodiments, the filtered envelope tracking generator may include a real-time envelope tracking generator and a low-pass filter.

[0079] In some embodiments, the filtered envelope tracking generator may include a multilevel envelope tracking generator and a low-pass filter.

[0080] In some embodiments, a first output signal of the one or more output signals may be provided from the multilevel envelope tracking generator. A second output signal of the one or more output signals may be provided from the low-pass filter. The first output signal may be provided to the digital predistorter, and the second output signal may be provided to the envelope tracker.

[0081] In some embodiments, the digital predistorter may be configured to select a look-up table corresponding to the current level of the multilevel envelope tracking generator.

[0082] In some embodiments, the digital predistorter may be configured to select a look-up table based on the output signal of the one or more output signals provided to the digital predistorter.

[0083] In some embodiments, the filtered envelope tracking generator may include a voltage regulation circuit configured to maintain one of the one or more output signals at a predetermined voltage or higher than the predetermined voltage.

[0084] In some embodiments, the filtered envelope tracking generator may include a boost circuit configured to boost the voltage of one of the one or more output signals by a predetermined voltage.

[0085] In some embodiments, a digital predistorter may be configured to compensate an input signal based on the characteristics of a power amplifier and the output signal of the one or more output signals from the filtered envelope tracking generator.

[0086] According to another aspect of certain embodiments of the present disclosure, an envelope tracking method may include receiving an input signal at a digital predistorter. The input signal may represent a signal to be transmitted. The method may further include receiving the input signal at a filtered envelope tracking generator. The method may further include the filtered envelope tracking generator generating one or more output signals. The one or more output signals may include a filtered tracking envelope of the input signal. The method may further include receiving at least one of the one or more output signals at the digital predistorter. The method may further include receiving at least one of the one or more output signals at an envelope tracker. The method may further include providing an envelope tracking input from the envelope tracker to a power amplifier based on the at least one of the one or more output signals received at the envelope tracker.

[0087] In some embodiments, the filtered envelope tracking generator may generate the one or more output signals using a real-time envelope tracking generator and a low-pass filter.

[0088] In some embodiments, the filtered envelope tracking generator may generate one or more output signals using a multilevel envelope tracking generator and a low-pass filter.

[0089] In some embodiments, a first output signal of the one or more output signals may be provided from the multilevel envelope tracking generator, and a second output signal of the one or more output signals may be provided from the low-pass filter. The first output signal may be provided to the digital predistorter, and the second output signal may be provided to the envelope tracker.

[0090] In some embodiments, the method may further include the digital predistorter selecting a look-up table corresponding to the current level of the multilevel envelope tracking generator.

[0091] In some embodiments, the method may further include the digital predistorter selecting a look-up table based on the at least one of the one or more output signals provided to the digital predistorter.

[0092] In some embodiments, the method may further include a voltage regulation circuit maintaining one of the one or more output signals at a predetermined voltage or higher than the predetermined voltage.

[0093] In some embodiments, the method may further include a boost circuit raising the voltage of one of the one or more output signals by a predetermined voltage.

[0094] In some embodiments, the method may further include a digital pre-distorter compensating an input signal based on the characteristics of a power amplifier and the output signal of the one or more output signals from a filtered envelope tracking generator.

[0095] According to another aspect of certain embodiments, a radio frequency chip may include a digital front end, the digital front end including a digital pre-distorter for receiving an input signal representing a signal to be transmitted, wherein the digital front end further includes a filtered envelope tracking generator for receiving the input signal and providing one or more output signals. The one or more output signals may include a signal that is a filtered tracking envelope of the input signal. One of the one or more output signals may be provided to the digital pre-distorter. The radio frequency chip may further include an envelope tracker for receiving the filtered tracking envelope and providing an envelope tracking input to a power amplifier. The radio frequency chip may further include a power amplifier. The power amplifier may be configured to receive the output of the digital pre-distorter and the filtered tracking envelope.

[0096] In some embodiments, the radio frequency chip may further include an I / Q modulator for converting the output of the digital pre-distorter into an analog form and providing the analog form of the output of the digital pre-distorter to the power amplifier. The radio frequency chip may further include an envelope tracking digital-to-analog converter for converting the filtered tracking envelope into an analog form and providing the analog form of the filtered tracking envelope to the envelope tracker.

[0097] The foregoing description of specific embodiments will so reveal the general nature of the present disclosure that others can, without departing from the general concept, readily modify and / or adapt various applications of such specific embodiments by applying knowledge within the skill of the art without undue experimentation. Therefore, such adaptations and modifications are intended to fall within the meaning and range of equivalents of the disclosed embodiments based on the teachings and guidance presented herein. It should be understood that the terminology or phraseology herein is for the purpose of description and not of limitation, and thus the terminology or phraseology of this specification will be interpreted by those skilled in the art in light of the teachings and guidance.

[0098] The embodiments of the present disclosure have been described above by means of functional building blocks that illustrate specific functions and their relationships. For ease of description, the boundaries of these functional building blocks are arbitrarily defined herein. Alternative boundaries can be defined as long as the specified functions and their relationships are properly performed.

[0099] The Summary of the Invention and the Abstract sections may set forth one or more, but not all, exemplary embodiments of the present disclosure as contemplated by the inventors, and are therefore not intended to limit the present disclosure and the appended claims in any way.

[0100] Various functional blocks, modules, and steps have been disclosed above. The particular arrangements provided are illustrative and not restrictive. Accordingly, the functional blocks, modules, and steps may be reordered or combined in a different manner than the examples provided above. Similarly, some embodiments include only a subset of the functional blocks, modules, and steps and any such subset is permitted.

[0101] The breadth and scope of the present disclosure should not be limited by any of the above exemplary embodiments, but should be defined only in accordance with the appended claims and their equivalents.

Claims

1. A circuit for envelope tracking, the circuit comprising: A digital pre-distorter for receiving an input signal representing a signal to be transmitted; A filtered envelope tracking generator for receiving the input signal and providing one or more output signals, wherein the one or more output signals include a signal that is a filtered tracking envelope of the input signal, and wherein one of the one or more output signals is provided to the digital pre-distorter, the filtered tracking envelope being a low-pass filtered form of the absolute value of the input signal or a low-pass filtered form of a multi-level stepped representation of the input signal; and An envelope tracker for receiving the filtered tracking envelope and providing an envelope tracking input to a power amplifier.

2. The circuit according to claim 1, wherein The filtered envelope tracking generator includes a real-time envelope tracking generator and a low-pass filter.

3. The circuit according to claim 1, wherein The filtered envelope tracking generator includes a multi-level envelope tracking generator and a low-pass filter.

4. The circuit according to claim 3, wherein A first output signal of the one or more output signals is provided from the multi-level envelope tracking generator, A second output signal of the one or more output signals is provided from the low-pass filter, The first output signal is provided to the digital pre-distorter, and The second output signal is provided to the envelope tracker.

5. The circuit according to claim 3, wherein The digital pre-distorter is configured to select a look-up table corresponding to the current level of the multi-level envelope tracking generator.

6. The circuit according to claim 1, wherein The digital pre-distorter is configured to select a look-up table based on one of the one or more output signals provided to the digital pre-distorter.

7. The circuit according to claim 1, wherein The filtered envelope tracking generator includes a voltage regulation circuit for maintaining one of the one or more output signals at a predetermined voltage or higher than the predetermined voltage.

8. The circuit according to claim 1, wherein, The filtered envelope tracking generator includes a boost circuit for boosting the voltage of one of the one or more output signals by a predetermined voltage.

9. The circuit according to claim 1, wherein The digital pre-distorter is configured to compensate the input signal based on the characteristics of the power amplifier and one of the one or more output signals from the filtered envelope tracking generator.

10. An envelope tracking method, the method comprising: Receiving an input signal at a digital pre-distorter, wherein the input signal represents a signal to be transmitted; Receiving the input signal at a filtered envelope tracking generator; The filtered envelope tracking generator generating one or more output signals, wherein the one or more output signals include the filtered tracking envelope of the input signal, the filtered tracking envelope being a low-pass filtered form of the absolute value of the input signal or a low-pass filtered form of a multi-level stepped representation of the input signal; Receiving at least one of the one or more output signals at the digital pre-distorter; Receiving at least one of the one or more output signals at the envelope tracker; and Providing an envelope tracking input from the envelope tracker to a power amplifier based on at least one of the one or more output signals received at the envelope tracker.

11. The method according to claim 10, wherein, The filtering envelope tracking generator generates the one or more output signals using a real-time envelope tracking generator and a low-pass filter.

12. The method according to claim 10, wherein: The filtering envelope tracking generator generates the one or more output signals using a multi-level envelope tracking generator and a low-pass filter.

13. The method according to claim 12, wherein: A first output signal among the one or more output signals is provided from the multi-level envelope tracking generator, a second output signal among the one or more output signals is provided from the low-pass filter, the first output signal is provided to the digital predistorter, and the second output signal is provided to the envelope tracker.

14. The method according to claim 12, further comprising: The digital predistorter selects a look-up table corresponding to the current level of the multi-level envelope tracking generator.

15. The method according to claim 10, further comprising: The digital predistorter selects a look-up table based on at least one of the one or more output signals provided to the digital predistorter.

16. The method according to claim 10, further comprising: The voltage regulation circuit maintains one of the one or more output signals at a predetermined voltage or higher than the predetermined voltage.

17. The method according to claim 10, further comprising: The boost circuit raises the voltage of one of the one or more output signals by a predetermined voltage.

18. The method according to claim 10, further comprising: The digital predistorter compensates the input signal based on the characteristics of the power amplifier and one of the one or more output signals from the filtering envelope tracking generator.

19. A radio frequency (RF) chip, the chip comprising: A digital front end including a digital predistorter for receiving an input signal representing a signal to be transmitted, wherein the digital front end further includes a filtering envelope tracking generator for receiving the input signal and providing one or more output signals, wherein the one or more output signals include a signal that is a filtered tracking envelope of the input signal, and wherein one of the one or more output signals is provided to the digital predistorter, and the filtered tracking envelope is a low-pass filtered form of the absolute value of the input signal or a low-pass filtered form of a multi-level step representation of the input signal; An envelope tracker for receiving the filtered tracking envelope and providing an envelope tracking input to a power amplifier; and A power amplifier for receiving the output of the digital predistorter and the filtered tracking envelope.

20. The RF chip according to claim 19, further comprising: A complex-to-real digital-to-analog converter for converting the output of the digital predistorter into an analog form and providing the analog form of the output of the digital predistorter to the power amplifier; And An envelope tracking digital-to-analog converter for converting the filtered tracking envelope into an analog form and providing the analog form of the filtered tracking envelope to the envelope tracker.

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