A HEMT device and its fabrication method

Abstract

This invention provides a HEMT device and its fabrication method. The HEMT device includes: a partially removed substrate layer; an epitaxial layer located on the substrate layer, the epitaxial layer including a nucleation layer in contact with the substrate layer; a source electrode region and a drain electrode region located on opposite sides above the epitaxial layer; and a patterned blank region provided in the drain electrode region, the blank region penetrating the epitaxial layer and extending to the portion of the substrate layer that has been removed. By partially removing the substrate layer, this invention avoids the formation of a conductive layer between the removed portion of the substrate layer and the nucleation layer, reducing parasitic resistance introduced by the substrate layer and decreasing radio frequency losses. Simultaneously, the blank region penetrating the source and drain electrode regions and the epitaxial layer improves the device's heat dissipation capability and controls thermal effects. Furthermore, by using a low-resistivity silicon substrate, the bending problem of high-resistivity silicon-based GaN epitaxial materials is avoided, thereby expanding the wafer size.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor integrated circuit manufacturing technology, and in particular relates to a HEMT device and its fabrication method. Background Technology

[0002] Gallium nitride (GaN) technology has attracted widespread attention in recent years for its applications in radio frequency and microwave fields. GaN-based devices possess superior material properties in two-dimensional electron gas channels, including a large bandgap (Eg = 3.42 eV), high electron saturation velocity (Vsat ~ 2.7 × 10⁷ cm / s), large breakdown field (Ec ~ 3.3 MV / cm), and high mobility (un ~ 2000 cm² / Vs), making them excellent candidate devices for realizing high-efficiency and high-output-power power amplifiers in wireless transmitters. Furthermore, recent advances in materials engineering have enabled the growth of high-quality GaN layers on large-scale silicon substrates, making it possible to realize low-cost and high-performance GaN-on-Silicon devices.

[0003] However, the significant lattice and thermal mismatch between silicon and GaN epitaxial layers is a major bottleneck restricting the development of silicon-based GaN technology. To address the mismatch issue, a thick gradient layer or superlattice layer is typically grown between the silicon substrate and the GaN buffer layer as a nucleation layer. However, a conductive layer easily forms at the interface between the substrate and the nucleation layer, introducing large parasitic resistance and capacitance, resulting in significant RF losses in the device at high frequencies, limiting output power and efficiency. Furthermore, GaNHEMT devices can use not only silicon substrates but also SiC substrates. SiC has a thermal conductivity three times that of silicon, providing better thermal performance, which necessitates consideration of thermal effects in silicon-based GaNHEMTs. Additionally, silicon-based GaN RF devices use high-resistivity (HR) silicon substrates, but compared to low-resistivity (LR) silicon substrates, growing high-strain GaN layers on HR substrates presents more severe bending problems. These bending issues also limit the development of GaN-on-Silicon technology to larger silicon substrates.

[0004] It should be noted that the above introduction to the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of this application and facilitating the understanding of those skilled in the art. It should not be assumed that the above technical solutions are known to those skilled in the art simply because these solutions have been described in the background section of this application. Summary of the Invention

[0005] In view of the shortcomings of the prior art, the purpose of this invention is to provide a HEMT device and its fabrication method to solve the problems of high radio frequency loss and significant thermal effects of silicon-based GaNHEMT devices in the prior art.

[0006] To achieve the above objectives, the present invention provides a HEMT device, the HEMT device comprising:

[0007] Substrate layer;

[0008] An epitaxial layer is located on the substrate layer, and the epitaxial layer includes a nucleation layer that is in contact with the substrate layer;

[0009] The source electrode region and the drain electrode region are located on both sides above the epitaxial layer;

[0010] In this process, at least a portion of the substrate layer corresponding to the drain electrode region is removed to form a notch corresponding to the drain electrode region.

[0011] Optionally, the drain electrode region is provided with a patterned blank area, which penetrates the epitaxial layer and extends to the notch.

[0012] Optionally, the width of the drain electrode region at both ends of the blank region along the gate width direction parallel to the line connecting the source electrode region and the drain electrode region is greater than 5 micrometers.

[0013] Optionally, the HEMT device further includes: an ohmic metal located above the source electrode region and the drain electrode region; a passivation layer covering the epitaxial layer and the ohmic metal; a gate electrode region located between the source electrode region and the drain electrode region; and a gate metal located above the gate electrode region.

[0014] Optionally, the substrate layer is a low-resistivity silicon substrate.

[0015] The present invention also provides a method for fabricating a HEMT device, the method being used to fabricate any of the above-described HEMT devices, the method comprising: providing a substrate layer, and growing an epitaxial layer on the surface of the substrate layer;

[0016] A source electrode region and a drain electrode region are formed on both sides of the surface of the epitaxial layer, and both the source electrode region and the drain electrode region are in contact with the epitaxial layer to form an ohmic contact.

[0017] The drain electrode region is graphically represented to form a blank region within the drain electrode region, and a portion of the surface of the epitaxial layer is exposed within the blank region.

[0018] The epitaxial layer exposed in the blank area is etched to expose the substrate layer;

[0019] The substrate layer exposed in the blank area is etched so that the blank area extends to a predetermined depth within the substrate layer;

[0020] The HEMT device thus formed is then bonded to the bonding substrate;

[0021] The surface of the substrate layer away from the bonding substrate is thinned until the blank area penetrates the substrate layer;

[0022] The bonded substrate is debonded.

[0023] Optionally, a passivation layer is deposited on the surface of the epitaxial layer, the source electrode region, and the drain electrode region; the passivation layer between the source electrode region and the drain electrode region is etched to form a strip gate trench, and a gate metal is disposed on the gate trench to form a gate electrode region.

[0024] Optionally, the width of the source electrode region and / or the drain electrode region along the gate width direction parallel to the line connecting the source electrode region and the drain electrode region is 20 micrometers to 500 micrometers; and / or the length of the source electrode region and / or the drain electrode region along the gate length direction parallel to the surface of the substrate and perpendicular to the line connecting the source electrode region and the drain electrode region is 15 micrometers to 50 micrometers.

[0025] Optionally, the blank area extends to a depth of 50 micrometers to 100 micrometers within the substrate layer.

[0026] Optionally, the method for thinning the surface of the substrate layer away from the bonding substrate may be mechanical grinding wheel thinning, polishing thinning, and / or chemical etching thinning.

[0027] As described above, the HEMT device and its fabrication method of the present invention have the following beneficial effects:

[0028] By partially removing the substrate layer, this invention avoids the formation of a conductive layer between the removed portion of the substrate layer and the nucleation layer, thereby reducing the parasitic resistance introduced by the substrate layer and reducing radio frequency losses.

[0029] This invention utilizes the blank areas penetrating the source and drain electrode regions and their epitaxial layers to improve the heat dissipation capacity of the device and control thermal effects.

[0030] The present invention sets the substrate layer to a low-resistivity silicon substrate to avoid the bending problem of high-resistivity silicon-based GaN epitaxial materials, thereby expanding the wafer size. Attached Figure Description

[0031] Figure 1 The diagram shown is a structural schematic of the HEMT device of the present invention.

[0032] Figure 2 The diagram shown is a schematic representation of an optional example of the HEMT device of the present invention.

[0033] Figure 3The diagram shown is a schematic representation of the structure of the epitaxial layer grown in step 1 of the optional example of the HEMT device fabrication method of the present invention.

[0034] Figure 4 The diagram shows the structure of the source electrode region and drain electrode region set in step 2 of the fabrication method of the HEMT device of the present invention.

[0035] Figure 5 The diagram shown is a schematic representation of the structure presented in step 2 of the optional example of the fabrication method of the HEMT device of the present invention, which involves setting a passivation layer.

[0036] Figure 6 The diagram shown is a schematic representation of the structure of the gate electrode region in an optional example of step 2 in the fabrication method of the HEMT device of the present invention.

[0037] Figure 7 The diagram shown is a schematic representation of the structure of the patterned drain electrode region in step 3 of the fabrication method of the HEMT device of the present invention.

[0038] Figure 8 The diagram shows the structure of the epitaxial layer etched in step 4 of the fabrication method of the HEMT device of the present invention.

[0039] Figure 9 The diagram shows the structure of the blank area extending to the substrate layer in step 5 of the HEMT device fabrication method of the present invention.

[0040] Figure 10 The diagram shown is a schematic representation of the structure of the HEMT device bonded to the bonding substrate in step 6 of the HEMT device fabrication method of the present invention.

[0041] Figure 11 The diagram shows the structure of the substrate thinning process in step 7 of the HEMT device fabrication method of the present invention.

[0042] Figure 12 The diagram shown is a structural schematic of step 8, debonding, in the fabrication method of the HEMT device of the present invention.

[0043] Figure 13 The diagram shown is a schematic representation of the structure of an HEMT device bonded to a bonding substrate, which is an optional example of the fabrication method of the HEMT device of the present invention.

[0044] Figure 14 The diagram shown is a schematic representation of the structure of a thinned substrate layer in an optional example of the fabrication method of the HEMT device of the present invention.

[0045] Figure 15 The diagram shown is a schematic representation of the structure obtained by removing a portion of the substrate layer in an optional example of the fabrication method of the HEMT device of the present invention.

[0046] Component designation explanation

[0047] 10. Substrate layer; 20. Epitaxial layer; 21. Nucleation layer; 22. Buffer layer; 23. Barrier layer; 31. Source electrode region; 32. Drain electrode region; 321. Blank region; 33. Gate electrode region; 331. Gate trench; 332. Gate metal; 40. Passivation layer; 51. Bonding substrate; 52. Bonding layer. Detailed Implementation

[0048] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0049] In the detailed description of embodiments of the present invention, for ease of explanation, the schematic diagrams illustrating the device structure may be partially enlarged without adhering to the general scale, and the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. Furthermore, in actual manufacturing, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0050] For ease of description, spatial relation terms such as “below,” “under,” “lower than,” “below,” “above,” and “upper” may be used herein to describe the relationship between one element or feature shown in the accompanying drawings and other elements or features. It will be understood that these spatial relation terms are intended to include directions other than those depicted in the accompanying drawings for devices in use or operation.

[0051] In the context of this application, the structure described above the first feature may include embodiments in which the first and second features are in direct contact, or embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0052] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0053] like Figure 1 As shown, the present invention provides a HEMT device, the HEMT device comprising:

[0054] Substrate layer 10;

[0055] Epitaxial layer 20, the epitaxial layer 20 is located on the substrate layer 10, the epitaxial layer 20 includes a nucleation layer 21, the nucleation layer 21 is in contact with the substrate layer 10;

[0056] Source electrode region 31 and drain electrode region 32 are located on both sides above the epitaxial layer 20;

[0057] In this process, at least a portion of the region of the substrate layer 10 that is perpendicular to the drain electrode region 32 is removed to form a notch that is perpendicular to the drain electrode region 32.

[0058] In silicon-based GaN HEMT devices, there is a significant lattice and thermal mismatch between the silicon substrate and the GaN epitaxial layer 20. To address this mismatch, a thick gradient layer or superlattice layer is typically grown between the silicon substrate and the GaN buffer layer 22 as a nucleation layer 21. However, a conductive layer easily forms at the interface between the substrate layer 10 and the nucleation layer 21, introducing large parasitic resistance and capacitance. Consequently, significant radio frequency losses occur at high frequencies, limiting the device's output power and operating efficiency. This invention reduces the mismatch between the substrate layer 10 and the nucleation layer 21 by removing a portion of the substrate layer 10. The conductive layer formed between 21 reduces the parasitic resistance caused by the conductive layer and reduces the RF loss of HEMT devices. At the same time, during the operation of silicon-based GaNHEMT devices, there is a strong heat point on the side of the gate near the drain. Due to the low thermal conductivity of silicon material, a large thermal effect will be generated, affecting the normal operation of the device. The present invention forms a heat conduction channel near the drain electrode region 32 from the drain electrode region 32, penetrates the epitaxial layer 20 and extends to the blank region 321 of the substrate layer 10. While forming the partially removed substrate layer 10, it realizes the heat conduction channel near the drain electrode region 32, thereby improving the heat dissipation capacity of the device and controlling the thermal effect.

[0059] In one embodiment, such as Figure 1 As shown, the epitaxial layer 20 also includes a buffer layer 22 and a barrier layer 23. The buffer layer 22 is disposed on the nucleation layer 21, and the barrier layer 23 is disposed on the buffer layer 22. Functional layers can also be added or removed in the epitaxial layer 20 as needed.

[0060] In one embodiment, the drain electrode region 32 is provided with a patterned blank region 321, which penetrates the epitaxial layer 20 and extends to the notch.

[0061] In one embodiment, such as Figure 2 As shown, only part of the substrate layer 10 can be removed without setting a blank area 321 in the drain electrode region 32 and the epitaxial layer 20. The resulting HEMT device can still reduce RF loss, but the heat dissipation capability will be greatly reduced.

[0062] In one embodiment, the width of the drain electrode region 32 at both ends of the blank region 321 along the gate width direction parallel to the line connecting the source electrode region 31 and the drain electrode region 32 is greater than 5 micrometers.

[0063] The present invention improves heat dissipation and reduces radio frequency loss by setting the width of the drain electrode region 32 on both sides of the blank region 321, while ensuring the normal operation of the drain electrode region 32.

[0064] In one embodiment, the HEMT device further includes: an ohmic metal located above the source electrode region 31 and the drain electrode region 32; a passivation layer 40 covering the barrier layer 23 and the ohmic metal; a gate electrode region 33 located between the source electrode region 31 and the drain electrode region 32; and a gate metal 332 located above the gate electrode region 33. Specifically, the passivation layer 40 and the gate electrode region 33 are configured as follows: Figure 1 As shown.

[0065] In one embodiment, the substrate layer 10 is a low-resistivity silicon substrate.

[0066] Silicon-based GaN radio frequency devices require high-resistivity (HR) silicon substrates. Growing a high-strain GaN epitaxial layer 20 on an HR substrate exacerbates bending issues and can even lead to wafer cracking, thus limiting the development of GaN-on-silicon technology to larger wafer sizes. This invention addresses this by using a low-resistivity silicon substrate 10, reducing the stress between the substrate 10 and the epitaxial layer 20, thereby alleviating the bending problem of the epitaxial material and enabling the expansion of silicon-based GaN technology to larger wafer sizes.

[0067] In one embodiment, the blank area 321 is a circular or polygonal hole surrounded by the drain electrode area 32.

[0068] Specifically, the blank area 321 can be a partial removal structure with different features such as grooves and holes.

[0069] Specifically, the blank area 321 can be circular, elliptical, polygonal or other planar shapes along a cross section parallel to the substrate layer 10, and can be designed according to specific performance requirements.

[0070] This invention provides a method for fabricating a HEMT device, the method being used to fabricate any of the HEMT devices described above, the method comprising:

[0071] Step 1: Provide a substrate layer 10, and grow an epitaxial layer 20 on the surface of the substrate layer 10;

[0072] Step 2: A source electrode region 31 and a drain electrode region 32 are formed on both sides of the surface of the epitaxial layer 20, respectively. Both the source electrode region 31 and the drain electrode region 32 are in contact with the epitaxial layer 20 and form an ohmic contact.

[0073] Step 3: Pattern the drain electrode region 32 to form a blank region 321 within the drain electrode region 32, in which a portion of the surface of the epitaxial layer 20 is exposed;

[0074] Step 4: Etch the epitaxial layer 20 exposed in the blank area 321 to expose the substrate layer 10;

[0075] Step 5: Etch the substrate layer 10 exposed in the blank area 321 so that the blank area 321 extends to a predetermined depth in the substrate layer 10;

[0076] Step 6: Bond the HEMT device formed so far to the bonding substrate 51;

[0077] Step 7: Thin the surface of the substrate layer 10 away from the bonding substrate 51 until the blank area 321 penetrates the substrate layer 10;

[0078] Step 8: Debond the bonded substrate 51.

[0079] The fabrication method of the HEMT device of the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that the above order does not strictly represent the fabrication order of the HEMT device protected by the present invention, and those skilled in the art can make changes according to the actual fabrication steps.

[0080] First, step 1 is performed, providing a substrate layer 10, and growing an epitaxial layer 20 on the surface of the substrate layer 10.

[0081] In one embodiment, the substrate layer 10 is a low-resistivity silicon substrate.

[0082] By setting the substrate layer 10 as a low-resistivity silicon substrate, the present invention reduces the stress between the substrate layer 10 and the epitaxial layer 20, thereby alleviating the bending problem of the epitaxial material and enabling silicon-based GaN technology to be extended to larger wafer sizes.

[0083] In one embodiment, such as Figure 3 As shown, the epitaxial layer 20 grown on the surface of the substrate layer 10 includes, from bottom to top, a nucleation layer 21, a buffer layer 22, and a barrier layer 23.

[0084] Then, as Figure 4As shown, in step 2, a source electrode region 31 and a drain electrode region 32 are formed on both sides of the surface of the epitaxial layer 20, respectively. Both the source electrode region 31 and the drain electrode region 32 are in contact with the epitaxial layer 20 and form an ohmic contact.

[0085] In one embodiment, such as Figure 5 As shown, the fabrication method further includes: depositing a passivation layer 40 on the surface of the epitaxial layer 20, the source electrode region 31, and the drain electrode region 32; as shown Figure 6 As shown, a passivation layer 40 is etched between the source electrode region 31 and the drain electrode region 32 to form a strip-shaped gate trench 331, and a gate metal 332 is disposed on the gate trench 331 to form a gate electrode region 33.

[0086] In one embodiment, the width of the source electrode region 31 and / or the drain electrode region 32 along the gate width direction parallel to the line connecting the source electrode region 31 and the drain electrode region 32 is 20 micrometers to 500 micrometers; and / or the length of the source electrode region 31 and / or the drain electrode region 32 along the gate length direction parallel to the surface of the substrate layer 10 and perpendicular to the line connecting the source electrode region 31 and the drain electrode region 32 is 15 micrometers to 50 micrometers.

[0087] Next, as Figure 7 As shown, in step 3, the drain electrode region 32 is graphically formed to create a blank region 321 within the drain electrode region 32, in which a portion of the surface of the epitaxial layer 20 is exposed.

[0088] Then, as Figure 8 As shown, step 4 is performed to etch the epitaxial layer 20 exposed in the blank area 321 to expose the substrate layer 10.

[0089] Next, as Figure 9 As shown, step 5 is performed to etch the substrate layer 10 exposed in the blank area 321, so that the blank area 321 extends to a predetermined depth in the substrate layer 10.

[0090] In one embodiment, the blank area 321 extends to a depth of 50 micrometers to 100 micrometers within the substrate layer 10.

[0091] By setting the blank area 321 to extend to a depth within the substrate layer 10, the present invention achieves the highest possible heat dissipation efficiency and the lowest possible device thickness while ensuring support strength.

[0092] Then, as Figure 10 As shown, step 6 is performed to bond the HEMT device formed thereto onto the bonding substrate 51.

[0093] Next, as Figure 11 As shown, in step 7, the surface of the substrate layer 10 away from the bonding substrate 51 is thinned until the blank area 321 penetrates the substrate layer 10.

[0094] In one embodiment, the method for thinning the surface of the substrate layer 10 away from the bonding substrate 51 is mechanical grinding wheel thinning, polishing thinning, and / or chemical etching thinning.

[0095] Finally, as Figure 12 As shown, step 8 is performed to debond the bonding substrate 51.

[0096] This invention reduces the conductive layer formed between the substrate layer 10 and the nucleation layer 21 by setting a blank region 321 that penetrates the drain electrode region 32 and the epitaxial layer 20 and extends to the substrate layer 10, thereby removing part of the substrate layer 10. This reduces the parasitic resistance caused by the conductive layer, reduces the RF loss of the HEMT device, and simultaneously establishes a heat conduction channel near the drain electrode region 32, thereby improving the device's heat dissipation capability and controlling thermal effects.

[0097] In another embodiment, after step 2, steps 3-5 can be skipped, and steps 6-8 can be performed directly, such as... Figure 13 As shown, the HEMT device formed after step 2 is bonded to the bonding substrate 51 for bonding; as Figure 14 As shown, the surface of the substrate layer 10 away from the bonding substrate 51 is thinned; as Figure 15 As shown, a portion of the substrate layer 10 is removed to reduce the contact area between the substrate layer 10 and the epitaxial layer 20; then the bonding substrate 51 is debonded.

[0098] In an optional example, such as Figures 13-15 As shown, before bonding the HEMT device to the bonding substrate 51, a bonding layer 52 is disposed on the surface of the HEMT device away from the substrate layer 10. The bonding layer 52 covers the surface of the HEMT device away from the substrate layer 10, and then bonding is performed. Debonding of the bonding substrate 51 is achieved by melting or glass bonding layer 52.

[0099] By setting a bonding layer 52 for bonding, the present invention can improve the efficiency of bonding and debonding, reduce the surface damage to the device caused by the bonding and debonding process, and improve the reliability of the device after debonding.

[0100] In one embodiment, the bonding layer 52 may be wax or other suitable material.

[0101] In summary, the HEMT device and its fabrication method of the present invention can avoid the formation of a conductive layer between the removed portion of the substrate layer and the nucleation layer by partially removing the substrate layer, thereby reducing the parasitic resistance introduced by the substrate layer and reducing radio frequency losses. At the same time, the blank areas penetrating the source and drain electrode regions and their epitaxial layers can improve the heat dissipation capacity of the device and control thermal effects. In addition, by setting the substrate layer to a low-resistivity silicon substrate, the bending problem of high-resistivity silicon-based GaN epitaxial materials is avoided, thereby expanding the wafer size.

[0102] Therefore, this invention effectively overcomes the various shortcomings of the prior art and has high industrial application value.

[0103] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A HEMT device, characterized in that, The HEMT device includes: Substrate layer; An epitaxial layer is located on the substrate layer, and the epitaxial layer includes a nucleation layer that is in contact with the substrate layer; The source electrode region and the drain electrode region are located on both sides above the epitaxial layer; wherein, at least a portion of the substrate layer corresponding to the drain electrode region is removed to form a notch corresponding to the drain electrode region, thereby reducing the conductive layer formed between the substrate layer and the nucleation layer.

2. The HEMT device according to claim 1, characterized in that, The drain electrode region is provided with a patterned blank area, which penetrates the epitaxial layer and extends to the notch.

3. The HEMT device according to claim 2, characterized in that, The width of the drain electrode region at both ends of the blank region along the gate width direction parallel to the line connecting the source electrode region and the drain electrode region is greater than 5 micrometers.

4. The HEMT device according to claim 1, characterized in that, The HEMT device also includes: Ohmic metal, wherein the ohmic metal is located above the source electrode region and the drain electrode region; A passivation layer covering the epitaxial layer and the ohmic metal; A gate electrode region, wherein the gate electrode region is located between the source electrode region and the drain electrode region; Gate metal, which is located above the gate electrode region.

5. The HEMT device according to claim 1, characterized in that, The substrate is a low-resistivity silicon substrate.

6. A method for fabricating a HEMT device, characterized in that, The fabrication method is used to fabricate the HEMT device according to any one of claims 1-5, and the fabrication method includes: providing a substrate layer and growing an epitaxial layer on the surface of the substrate layer; A source electrode region and a drain electrode region are formed on both sides of the surface of the epitaxial layer, and both the source electrode region and the drain electrode region are in contact with the epitaxial layer to form an ohmic contact. The drain electrode region is graphically represented to form a blank region within the drain electrode region, and a portion of the surface of the epitaxial layer is exposed within the blank region. The epitaxial layer exposed in the blank area is etched to expose the substrate layer; The substrate layer exposed in the blank area is etched so that the blank area extends to a predetermined depth within the substrate layer; The HEMT device thus formed is then bonded to the bonding substrate; The surface of the substrate layer away from the bonding substrate is thinned until the blank area penetrates the substrate layer; The bonded substrate is debonded.

7. The method for fabricating a HEMT device according to claim 6, characterized in that, The preparation method further includes: depositing a passivation layer on the surface of the epitaxial layer, the source electrode region, and the drain electrode region; A passivation layer is etched between the source electrode region and the drain electrode region to form a strip-shaped gate trench, and a gate metal is disposed on the gate trench to form a gate electrode region.

8. The method for fabricating a HEMT device according to claim 7, characterized in that, The width of the source electrode region and / or the drain electrode region along the gate width direction parallel to the line connecting the source electrode region and the drain electrode region is 20 micrometers to 500 micrometers; and / or the length of the source electrode region and / or the drain electrode region along the gate length direction parallel to the surface of the substrate and perpendicular to the line connecting the source electrode region and the drain electrode region is 15 micrometers to 50 micrometers.

9. The method for fabricating a HEMT device according to claim 6, characterized in that, The blank area extends to a depth of 50 micrometers to 100 micrometers within the substrate layer.

10. The method for fabricating a HEMT device according to claim 6, characterized in that, The methods for thinning the surface of the substrate layer away from the bonded substrate are mechanical grinding wheel thinning, polishing thinning, and / or chemical etching thinning.

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