Automatic Gain Control (AGC) for an On-Off Keying (OOK) Receiver

Abstract

The on-off keying (OOK) receiver has a discontinuous automatic gain control (AGC) that sets the gain at the start of each frame and locks the gain setting for the remainder of that frame, preventing the OOK data from causing instability in the AGC loop. The AGC controller initializes the gain settings of the low-noise amplifier (LNA), low-pass filter (LPF), and programmable gain amplifier (PGA) to maximum values. The LNA, LPF, and PGA are in series and provide an input signal to the rectifier, which produces a voltage output to the 1 / 0 data decision circuit. The level detector compares the voltage output with two thresholds. When either threshold is exceeded, the AGC controller steps down the gain setting until the voltage output is between the two thresholds, at which point the gain setting is locked for the remainder of the current frame. When a long string of 0 data is detected between frames, the frame detector resets the AGC controller between frames. The LNA gain is reduced last.

Description

Technical Field

[0001] The present invention relates to an Automatic Gain Control (AGC) circuit, and particularly to discontinuous AGC before On-Off Shift Keying (OOK) frame data.

Background Art

[0002] Data is usually transmitted using Amplitude-Shift Keying (ASK) modulation. A simplified form of ASK modulation is On-Off Shift Keying (OOK) modulation. When using OOK, a large-amplitude carrier is transmitted to represent signal 1, while no carrier is transmitted to represent signal 0.

[0003] OOK transceivers are particularly useful for battery-powered portable devices because transmission power is saved when sending data 0. Since the carrier is only transmitted during data 1, power consumption can be reduced by half or more, depending on the data being transmitted. OOK is commonly used for short-range wireless communication links.

[0004] Automatic Gain Control (AGC) is commonly used in OOK transceivers. AGC allows a wide range of input power that would otherwise saturate the receiver.

[0005] Figure 1A-1B Highlights the saturation problem of the OOK receiver. In Figure 1A , a high-amplitude carrier is transmitted during data 1, while no carrier is transmitted during data 0. During these data 0 time periods. Low-amplitude oscillations may occur.

[0006] The received signal is usually very weak, for example when the received signal is a radio frequency (RF) signal received from a small antenna. Such a weak RF received signal is usually amplified by the receiver. Figure 1B Shows a saturated and amplified received signal. The amplifier gain can be large enough that the high-amplitude signal during data 1 exceeds the range of the physical components of the amplifier or the power supply voltage. When saturation occurs, the peak of the received signal is clipped. Both the positive and negative peaks may be clipped.

[0007] Although no carrier is transmitted during data 0, noise can still be received during these periods and is amplified by the receiver. Therefore, the amplified signal during data 0 is greater than the RF input signal from the antenna. When saturation occurs, the amplitude during data 0 can approach the amplitude during data 1 and clip the peak during data 1. When such saturation occurs, it is difficult to distinguish between data 1 and data 0 periods.

[0008] In a portable communication system, the distance between the antennas of the transmitter and the receiver may vary, and the transmit power and other factors affecting the received signal strength may also vary. The input power range of the antenna can be quite large, depending on these factors that may differ. Due to the limited range of the receive amplifier and the need to obtain high gain under various conditions, this wide range of input power of the received signal can cause saturation.

[0009] Figure 2 Highlights the problem of continuous-time AGC in an OOK transceiver. The amplified received signal RIN has a gain setting to avoid saturation. This gain can be adjusted using an automatic gain control (AGC) circuit that operates continuously at the input to adjust the gain. The received signal RIN can be rectified and then input to the AGC as the signal AGC_IN. During high-amplitude data 1, AGC_IN rapidly drops with the first high-amplitude peak and continues to drift to a low level with other high-amplitude peaks received during data 1. When the data switches from 1 to 0, the low-amplitude peaks cause AGC_IN to increase rapidly and then drift to a high level with additional low-amplitude peaks that occur during data 0.

[0010] AGC_IN continuously drops during data 1 and rises during data 0, essentially oscillating with the OOK data cycle. When the output envelope is unstable, this oscillation can cause the AGC loop to be unstable. The rectifier output AGC_IN causes the AGC circuit to oscillate due to the oscillation of its input. This oscillation and instability are undesirable.

[0011] There is a need for an OOK receiver with a discontinuous automatic gain control (AGC) circuit. There is a need for an OOK receiver that adjusts the gain before the data payload in a frame. There is a need for an OOK receiver that performs gain adjustment in the frame header before the frame data to prevent oscillation and loop instability when using OOK modulation.

Description of the Drawings

[0012] Figure 1A-1B Highlights the saturation problem of the OOK receiver.

[0013] Figure 2 Highlights the problem of continuous-time AGC in an OOK transceiver.

[0014] Figure 3 Is a block diagram of an OOK receiver with frame-triggered AGC.

[0015] Figure 4 Highlights the voltage comparison of the gain setting.

[0016] Figure 5It is a function graph of the rectifier output voltage and the rectifier input power.

[0017] Figure 6 It shows an OOK frame.

[0018] Figure 7 It is the flowchart of the operation of the AGC controller.

[0019] Figure 8 It is the waveform diagram of the operation of an OOK receiver that sets the AGC at the start of each frame.

Detailed implementation manners

[0020] The present invention relates to an improvement of a discontinuous AGC circuit. The following description is for enabling a person of ordinary skill in the art to make and use the present invention in the context of a specific application and its requirements. Various modifications to the preferred embodiments will be apparent to those skilled in the art, and the general principles defined herein can be applied to other embodiments. Therefore, the present invention is not intended to be limited to the specific embodiments shown and described, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0021] Figure 3 It is a block diagram of an OOK receiver with frame-triggered AGC. An input signal, such as a radio frequency (RF) signal received from an antenna, is input to a low-noise amplifier (LNA) 20. The LNA 20 has a gain that can be adjusted using LNA_GAIN. The LNA 20 is designed to amplify weak signals without adding significant noise to the amplified signals to prevent signal distortion when strengthening weak input signals.

[0022] The output of the LNA 20 is applied to a mixer 18, and the mixer 18 also receives a waveform signal from a local oscillator 38, which generally oscillates at a frequency lower than the RF input. Thus, the mixer 18 converts the RF input to a lower frequency. The RF component is removed by a low-pass filter 22, and the remaining lower-frequency signal is applied to a programmable gain amplifier (PGA) 24. The low-pass filter 22 may include an amplifier to improve noise suppression, and its gain is set by LPF_GAIN. The gain of the PGA 24 is set by PGA_GAIN. The amplified output of the PGA 24 is the input RIN of the rectifier.

[0023] Rectifier 32 receives its full-wave RIN input and rectifies it to generate a rectified signal VOUT. This voltage VOUT is applied to decision circuit 34, which compares VOUT with a voltage threshold to determine when to output a binary 0 or binary 1 as received data. The generated output data DATA_OUT can be sent to other blocks, for example, to parse the data stream of fields within a frame, to save the data within a data payload, or to perform a cyclic redundancy check (CRC) to verify the data.

[0024] Frame detector 35 examines DATA_OUT to detect a frame. For example, a frame can be separated by a long string of data 0s, where no carrier is being sent for OOK modulation. When the carrier is being sent continuously, the start of an OOK frame may have a long string of all 1s. Frame detector 35 can detect a long string of 0s at the end of a frame and then activate a frame start signal when it detects the first 1 after a long string of 0s between frames. When it detects a long string of 0s at the end of a frame, frame detector 35 can also activate a reset signal AGC_RST.

[0025] Level detector 36 compares the voltage VOUT output by rectifier 32 with one or more voltage thresholds. The voltage comparison result of level detector 36 is input to AGC controller 30.

[0026] AGC controller 30 can be a controller, microcontroller, state machine, programmable logic, or other logic that executes a gain adjustment routine, as shown later in Figure 7 When frame detector 35 issues the AGC_RST signal at the end of a frame, AGC controller 30 is reset and activated to perform gain adjustment for the next new frame. When the next new frame starts with a sequence of all 1s, AGC controller 30 reads the voltage comparison result from level detector 36 and reduces the gain from the maximum value until VOUT is between the two voltage levels compared by level detector 36.

[0027] Once the gain is set for a new frame, AGC controller 30 locks the gain setting and becomes idle for the remainder of that frame. When the frame ends, frame detector 35 detects a long sequence of 0s between frames and activates AGC_RST to reset AGC controller 30 and trigger AGC controller 30 to activate when the next frame starts with a sequence of 1s.

[0028] After determining the gain settings at the start of each frame, the AGC controller 30 remains idle and does not further adjust the gain for the remainder of the frame. In particular, the gain is not adjusted during the OOK data payload or other fields in the OOK frame. Since the AGC controller 30 is disabled for most of the OOK frame, the AGC loop is interrupted during OOK data, preventing loop instability and oscillation that might occur if the AGC controller 30 were continuously enabled for OOK data.

[0029] The AGC controller 30 adjusts three different gains: the LNA GAIN of the LNA 20, the LPF GAIN of the low-pass filter 22, and the PGA GAIN of the PGA 24. Initially, at the start of a new frame, all three gains, LNA_GAIN, LPF_GAIN, and PGA_GAIN, are set to their maximum values. Instead of reducing all three gains simultaneously, the AGC controller 30 first reduces the PGA_GAIN, and then once the PGA_GAIN reaches its minimum value, the AGC controller 30 reduces the LPF_GAIN. If the LPF_GAIN also reaches its minimum value before VOUT is between two voltage thresholds, then finally, the AGC controller 30 reduces the LNA_GAIN. This sequence allows the LNA 20 to operate at its maximum gain as much as possible, helping to amplify weak RF input signals as much as possible while achieving good noise suppression.

[0030] Figure 4 The voltage comparison of the gain settings is highlighted. The rectifier 32 is inverting, and when RIN is high, the output voltage VOUT is low, which is sensed by the decision circuit 34 to generate the output data DATA_OUT, which is then parsed by the frame logic (not shown) to extract the data payload. The capacitor 46 can pass high-frequency signals while isolating the DC level from the decision circuit 34. The resistor 48 biases the non-inverting + input of the comparator 44 to the common-mode voltage VCM, allowing small-signal data to pass through the capacitor 46 and reach the + input of the comparator 44. The inverting - input of the comparator 44 is directly connected to VCM. The comparator 44 is inverting, so when VOUT is low, DATA_OUT is high to compensate for the inverting action of the rectifier 32.

[0031] VOUT from the rectifier 32 is also input to the level detector 36, where VOUT is applied to the non-inverting + inputs of the comparators 40, 42. Two different voltage references are applied to the inverting - inputs of the comparators 40, 42. The inverting input of the comparator 40 receives VREF2, while the inverting input of the comparator 42 receives the lower reference voltage VREF1. For example, VREF1 can be 120 mV, and VREF2 can be 220 mV, which is one of many possible examples.

[0032] When VOUT is greater than VREF2, the upper comparator 40 drives its output COMP_A high, and when VOUT is greater than VREF1, the lower comparator 42 drives its output COMP_B high. There are three possible combinations for COMP_A and COMP_B: 11 when VOUT > VREF2 and > VREF1, 01 when VOUT is between VREF2 and VREF1, and 00 when VOUT is lower than VREF2 and VREF1.

[0033] In this embodiment, the rectifier 32 is inverting. When a carrier is received and amplified, the rectifier input RIN is high, causing the rectifier 32 to drive its output VOUT low. When no carrier is received, the rectifier input RIN is low, causing the rectifier 32 to drive its output VOUT high. Thus, the rectifier 32 has a logic inversion function in this embodiment.

[0034] When PD_AGC is high, the comparators 40 and 42 are powered off. When powered off, the comparators 40 and 42 drive COMP_A and COMP_B low. After the AGC has set the gain at the start of each frame, power is saved by driving PD_AGC high because the comparators 40 and 42 do not switch when receiving data payloads and data in other frame fields.

[0035] Figure 5 is a graph of the rectifier output voltage as a function of the rectifier input power. In Figure 5 the voltage output VOUT of the rectifier 32 is plotted as a function of the input power on the rectifier 32's input RIN. In this embodiment, as Figure 4 shown, the rectifier 32 is inverting, so when no carrier is received and RIN is low power, VOUT is high, as Figure 5 shown on the left. When a carrier is received, such as data 1, RIN is high power and the rectifier 32 drives VOUT low, as Figure 5 shown on the right.

[0036] Figure 5 Each curve in Figure 5 is for a different combination of fast or slow or typical devices at different temperatures. These operating curves can be generated by simulating different device or process parameters and operating temperatures. The target values of the voltage references VREF1 and VREF2 in the level detector 36 can be determined according to the operating conditions of the rectifier 32, as

[0037] The system design can have a target for the rectifier input power, e.g., -6 dBm to -2 dBm, which determines the vertical dashed line rising from the x-axis. The horizontal dashed line is drawn from the intersection of the vertical line with the middle of the operating curve bundle. These horizontal dashed lines intersect the y-axis at the target threshold voltages, or at VREF2 and VREF1.

[0038] For low input power and low voltage of RIN, when no carrier is received, e.g., for data 0, the rectifier 32 drives VOUT high. When VOUT output by the rectifier 32 is greater than VREF1 and VREF2, COMP_B and COMP_A are 11.

[0039] When a carrier is received, e.g., for data 1, high input power and voltage are input to the rectifier 32, which drives VOUT low. When VOUT output by the rectifier 32 is less than VREF1 and VREF2, COMP_B and COMP_A are 00.

[0040] For intermediate voltages, when VOUT is between VREF1 and VREF2, COMP_B and COMP_A are 01.

[0041] The AGC controller 30 iteratively reduces the gain setting starting from the maximum gain value, which may cause saturation and high RIN power, making the rectifier 32 drive VOUT to a very low voltage. When VOUT is very low, COMP_B and COMP_A are 00.

[0042] As the gain setting is reduced, the input power of RIN also decreases, causing VOUT to rise. Eventually, VOUT rises above the lower threshold VREF1, COMP_B becomes 1, while COMP_A remains 0. This 01 situation detected by the level detector 36 causes the AGC controller 30 to stop adjusting the gain setting and lock these gain settings for the remainder of the current frame. Once the AGC controller 30 has completed the gain adjustment, VOUT should be between Figure 5 the horizontal dashed lines for data 1. The input power of the rectifier 32 should be between the vertical dashed lines, which is the target input power of the rectifier 32.

[0043] Figure 6Shows an OOK frame. The OOK frame 260 uses on-off keying (OOK), where 1 is generated by transmitting the carrier, and 0 is generated due to the absence of the carrier. No carrier is transmitted between frames, and it is received as a string of 0s. The OOK frame 260 starts with AGC synchronization 264, where the carrier is transmitted continuously for 128 μS and is received as a string of consecutive 1s. The AGC controller 30 operates during AGC synchronization 264 and locks the gain setting at the end of AGC synchronization 264. Then the gain setting remains unchanged for the remainder of the OOK frame 260.

[0044] Following AGC synchronization 264 is a series of alternating 1s and 0s in the RF settling field 266, which is also 128 μS. Then comes a 44-bit frame synchronization and Manchester field. Next is the link layer PDU 262, which has a header and a payload. The header can have an 8-bit frame length field, a 6-bit user ID, and a 2-bit frame type. The payload can be up to 255 bytes and can carry application data or control information. The cyclic redundancy check (CRC) field 268 is 3 bytes and follows the payload immediately, and a 3-bit termination field ends the OOK frame 260. No carrier is transmitted between frames, so there will be a long period of 0 values between frames, and then the next frame starts with a series of 1s of AGC synchronization 264.

[0045] The length of AGC synchronization 264 can be large enough to allow the AGC controller 30 to test all possible gain settings. For example, if each of the gain settings of the LNA 20, low-pass filter 22, and PGA 24 has 3 binary bits and there are 7 settings for each level, then in the worst case, it may be necessary to test 7 * 3 or 21 settings in total. If it takes 5 μS to stabilize after each gain setting adjustment, then the AGC controller 30 may need 5 μS * 21 = 105 μS to test all possible gain settings. Therefore, the 128 μS time of AGC synchronization 264 is sufficient.

[0046] Figure 7 Is the flowchart of the operation of the AGC controller. When the AGC controller 30 is initialized, for example, after power-on or reset, the gain setting is set to the maximum setting (step 502). The power-off AGC parameter PD_AGC is set to 0 so that the level detector 36 generates COMP_A and COMP_B, causing the AGC controller 30 to adjust the gain setting. The AGC controller 30 monitors the comparison results COMP_A, COMP_B from the level detector 36 (step 504). When VOUT is greater than VREF2, VREF1, then COMP_A, COMP_B are 11 (step 506). The maximum gain setting is retained (step 508).

[0047] Condition 11 occurs when no carrier is received just before the start of a new frame. When the new frame starts, a carrier is continuously received during AGC synchronization 264. The continuous carrier and the maximum gain setting cause high power to be applied to the RIN input of rectifier 32, which drives VOUT to a very low level.

[0048] When VOUT is less than both VREF2 and VREF1, COMP_A and COMP_B are 00 (step 510). The gain setting is decreased by one step, e.g., 3 dB (step 514). When the new gain setting is not the minimum gain setting (step 518), then continue monitoring (step 504), e.g., after a stabilization delay of 5 μS.

[0049] With each pass through the loop of steps 504, 510, 514, the gain decreases and VOUT rises. After sufficient gain decrease, VOUT rises between VREF2 and VREF1. Then COMP_A and COMP_B are 01 (step 512). The target gain has been reached. The gain adjustment stops, and PD_AGC is set to 1 to power down level detector 36 and end the gain search process performed by AGC controller 30 (step 516). When the minimum gain setting is reached (step 518), the gain adjustment also ends.

[0050] After waiting for a period of time (step 522), e.g., one period of the 38.4 MHz clock, check AGC_RST (step 520). When AGC_RST is not set, continue waiting (step 522).

[0051] When the end of the current frame is reached, frame detector 35 pulses AGC_RST high. Step 520 detects the rising edge of AGC_RST, while step 530 detects the falling edge of AGC_RST. When the AGC_RST pulse is high, wait in the loop of steps 532 and 530 until the pulse ends after a period of time. Then AGC controller 30 is reset to the maximum gain setting, PD_AGC is set to 0 to power level detector 36, and AGC controller 30 is re-enabled for the next frame (step 502).

[0052] After the AGC_RST pulse ends, before AGC synchronization 264 ( Figure 6 ), the data remains 0 because no carrier is being transmitted. Before the frame starts, COMP_A and COMP_B are 11 because VOUT is at a high level due to the inversion of rectifier 32.

[0053] Once the next frame starts and AGC synchronization 264 begins, the carrier is continuously transmitted and received as 1. VOUT drops. The level detector 36 can operate normally to allow step 504 to monitor COMP_A and COMP_B.

[0054] When PD_AGC is set in step 516, the final gain setting is locked and stored. This gain setting can have three parts: the gain setting of LNA 20, the gain setting of the low-pass filter 22, and the gain setting of PGA 24. This gain setting is used to set the gains of LNA 20, the low-pass filter 22, and PGA 24 for the remainder of the current frame.

[0055] Figure 8 This is the operating waveform diagram of the OOK receiver that sets AGC at the start of each frame. For OOK modulation, the rectifier input RIN of the rectifier 32 ( Figure 3 ) is empty between frames because no carrier is transmitted. At the start of each frame, a carrier is continuously transmitted during AGC synchronization 264. Then, during the data payload part of the frame, the carrier is transmitted for data 1 and not transmitted for 0.

[0056] The amplitude of the rectifier input RIN ( Figure 3 ) is initially high because the maximum gain setting is used, but as the gain setting is gradually reduced in each cycle of the AGC process in Figure 7 , this RIN amplitude gradually decreases and reduces. Once the AGC process ends, the gain setting is locked, and the RIN amplitude for data 1 remains unchanged for the remainder of the current frame. In Figure 8 , the data payload and other fields in the OOK frame 260 are not drawn to scale along the x-axis (time), but AGC synchronization 264 is magnified relative to the other parts of the OOK frame 260.

[0057] When no carrier is transmitted for a long time, AGC_RST is pulsed high by the frame detector 35 at the end of each frame. When PD_AGC is high to disable the comparators 40 and 42 ( Figure 4 ), both COMP_A and COMP_B are low. Once PD_AGC is low and the AGC_RST reset pulse ends, the level detector 36 can compare VOUT with a voltage threshold to generate COMP_A and COMP_B, which are both high (11) between frames because VOUT is high when no carrier is transmitted.

[0058] The gain settings are initialized to their maximum values. The gain settings have three parts. For PGA 24, PGA_GAIN is set to the maximum value of 6. For low-pass filter 22, LPF_GAIN is set to the maximum value of 7, and for setting the gain of LNA 20, LNA_GAIN is set to its maximum value of 15.

[0059] When the frame starts, the continuous carrier and the maximum gain setting in AGC synchronization 264 result in large amplitude fluctuations of RIN. The inversion in rectifier 32 causes VOUT to drop to a low value below VREF1 and VREF2. COMP_A and COMP_B switch to 00.

[0060] The AGC controller 30 reduces the gain by 3 dB for each cycle ( Figure 7 step 514 of), PGA_GAIN decreases from 6 to 5 to 4 to 3 to 2 to 1 and then to 0 in the next 6 cycles. LPF_GAIN and LNA_GAIN remain at the maximum values of 7 and 15. The amplitude of RIN gradually decreases as PGA_GAIN decreases, and VOUT gradually increases.

[0061] After PGA_GAIN reaches its minimum setting of 0, the AGC controller 30 reduces LPF_GAIN from 7 to 6, then to 5, 4, 3, and finally to 2, at which point COMP_B becomes 1 because VOUT rises above the lower voltage threshold VREF1. PD_AGC is set high by the AGC controller 30 to end the AGC gain adjustment, power off the level detector 36, which causes COMP_A and COMP_B to become low and remain low for the data payload and other parts of the current frame.

[0062] The final gain settings of PGA_GAIN = 0, LPF_GAIN = 2, and LNA_GAIN = 15 are locked and used for the remainder of the current frame. After AGC synchronization 264 ends, for other fields in the current frame, such as the data payload, 0s and 1s are transmitted. For 0s, no carrier is sent, so RIN has a null value or a zero amplitude signal for these 0s. When no carrier is sent for data 0, VOUT goes high, and when a carrier for data 1 is received, VOUT goes low.

[0063] The final first frame ends, and no carrier is sent between frames, causing VOUT to remain high. The frame detector 35 detects the absence of a carrier for a long period and pulses AGC_RST high. This resets the gain settings to their maximum settings of 6, 7, 15. Additionally, PD_AGC goes low, causing the level detector 36 to produce COMP_A, COMP_B, which are 11 because VOUT remains high when no carrier is received. Then, at the start of the second frame, for AGC synchronization 264, continuous carrier transmission begins, VOUT drops, and COMP_A, COMP_B drop to 00.

[0064] The AGC controller 30 reduces the gain by 3 dB for each cycle, and PGA_GAIN decreases from 6 to 5 to 4 to 3 to 2 to 1 over the next 6 cycles and then drops to 0. LPF_GAIN and LNA_GAIN remain at their maximum values of 7 and 15. The amplitude of RIN decreases as PGA_GAIN decreases, and VOUT gradually rises.

[0065] After PGA_GAIN reaches its minimum setting of 0, the AGC controller 30 reduces LPF_GAIN from 7 to 6, then 5, 4, 3, 2, and finally 1, at which point COMP_B becomes 1 because VOUT rises above the lower voltage threshold VREF1. PD_AGC is set high by the AGC controller 30 to end the AGC gain adjustment. PD_AGC also disables the level detector 36, causing COMP_A, COMP_B to go low. For data 0, VOUT rises, and for data 1, VOUT drops.

[0066] The final gain settings of PGA_GAIN = 0, LPF_GAIN = 1, and LNA_GAIN = 15 are locked in and used for the remainder of the second frame. Each subsequent frame will set its gains in a similar manner. As the circuit warms up, the AGC controller 30 will adjust the gain settings to compensate for temperature or any other drift, such as changes in received power due to variations in distance or orientation from the transmitter or atmospheric conditions.

[0067]

Alternative Embodiment

[0068] The inventors have also added several other embodiments. For example, various combinations, integrations, and variations of the decision circuit 34, level detector 36, rectifier 32, AGC controller 30, amplifier, filter, and other components are possible. Inverting can be added or removed, for example, by swapping the inverting and non-inverting inputs on a comparator or adding an inverting stage. Although an inverting rectifier 32 has been described, a non-inverting rectifier 32 can also be used, which drives VOUT to a low level for data 0 and to a high level for data 1. The decision circuit 34 can be a comparator, an analog-to-digital converter (ADC). It is also possible to compare currents instead of voltages.

[0069] When the frequency of the received signal is lower than the radio frequency (RF), the mixer and local oscillator can be removed.

[0070] Each gain setting can adjust the power gain by 3 dB or some other value. For example, PGA24 can adjust the gain in 3 dB steps between 18 dB and 0 dB. LNA 20 can also adjust the gain in 3 dB steps, but from 38 dB to 17 dB. The gain of each module can be set in software or by a programmable register, and this software setting can override the gain set by the AGC controller 30.

[0071] The gain settings of LNA 20, low-pass filter 22, and PGA 24 do not have to be equal or linear. As an example, there can be more possible gain settings for PGA24 than for LNA 20. As an example, the total gain of the gain combination of LNA20, low-pass filter 22, and PGA24 can be, for example, 20 - 80 dBm. As an example, the range of input power can be from -70 dBm to -20 dBm.

[0072] First reducing the gain of PGA24 and finally reducing the gain of LNA20 can make LNA 20 operate at the maximum possible gain, which is useful for amplifying the weak RF signal input to LNA 20. Other sequences can also be used instead, for example, adjusting the gains of PGA 24 and low-pass filter 22 simultaneously instead of adjusting the gain of PGA 24 before adjusting the gain of low-pass filter 22. The low-pass filter 22 can be an active RC filter with variable gain. Moreover, the gain of the low-pass filter 22 can be fixed, for example, when using a passive filter instead of an active filter.

[0073] Many frame, header, and payload structures can be replaced, and many variations and extensions are possible. Variable-length payloads are possible. Figure 7 The order, sequence, and arrangement of the steps can be adjusted in many different ways for various purposes. Figure 8The waveform can also vary for different specific embodiments and circuit and program variations.

[0074] Although on-off keying (OOK) has been described and has benefited greatly from the present invention, it can be replaced with other modulation schemes, such as amplitude-shift keying (ASK), and still benefit from the present invention. The AGC controller 30 can operate less frequently than setting the gain for each frame, for example, for a subset of frames, such as every 5 frames, or for the next frame after a timer has elapsed.

[0075] Some receivers can have additional or fewer components, or components can be combined, such as integrating the low-pass filter 22 with the PGA 24. The LNA 20 can have a fixed rather than variable gain. If the low-pass filter 22 is passive and has a fixed gain, then only the gain of the PGA 24 can be adjusted. Some embodiments can delete PD_AGC, not power off the comparators 40, 42 in the level detector 36, or can turn off COMP_A, COMP_B instead of powering off the comparators that generate them.

[0076] More complex buffers, level shifters, comparators, or other components can be replaced or added. Inversions can be added at different locations. Other delayed hysteresis and shaping of the output waveform can be added.

[0077] Different transistors, capacitors, resistors, and other device sizes can be used, and various layout arrangements can be used, such as multi-legged, circular, donut, or irregularly shaped transistors. The current can be positive or negative and flow in either direction. Many second-order and third-order circuit effects can exist and can be important, especially for smaller device sizes. Circuit simulation can be used during the design process to account for these secondary factors.

[0078] The device can be implemented using n-channel, p-channel, or bipolar transistors or junctions within these transistors. The gate length and spacing can be increased to provide better protection against damage. Complementary metal-oxide-semiconductor (CMOS), biCMOS, or bipolar processes can be used for amplifiers such as the LNA 20 and the PGA 24, as well as the rectifier 32.

[0079] Many variations of IC semiconductor manufacturing processes are possible. Various materials can be used.

[0080] Terms such as up, down, above, below, horizontal, vertical, internal, external, higher, lower are relative and depend on the viewing point and do not mean to limit the present invention to a specific angle. The device can be rotated so that vertical becomes horizontal and horizontal becomes vertical, so these terms depend on the viewer.

[0081] The background section of the present invention may include background information regarding the problem or environment of the present invention, rather than describing the prior art of others. Thus, the materials included in the background section are not an admission by the applicant of the prior art.

[0082] Any method or process described herein is machine-implemented or computer-implemented and is intended to be performed by a machine, computer, or other device and is not intended to be performed solely by a human without machine assistance. Tangible results produced may include reports or other machine-generated displays on display devices such as computer monitors, projection devices, audio generating devices, and associated media devices, and may include hard copy printouts that are also machine-generated. Computer control of other machines is another tangible result.

[0083] Any advantages and benefits described do not necessarily apply to all embodiments of the present invention. When the term "means" appears in a claim element, the applicant intends that the claim element falls within the provisions of 35 USC Section 112, Paragraph 6. Typically, there is one or more word labels before the term "means". The one or more words before the term "means" are a label for the purpose of facilitating reference to the claim element and are not intended to express a structural limitation. Such means-plus-function claims are intended to cover not only the structures described herein for performing the function and their structural equivalents, but also equivalent structures. For example, although nails and screws have different configurations, they are equivalent structures because they both perform the fastening function. Claims that do not use the term "means" do not fall within the provisions of 35 USC Section 112, Paragraph 6. Signals are typically electronic signals, but may also be optical signals, for example, that may be transmitted over fiber optic lines

[0084] The above description of the embodiments of the present invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the present invention to the precise form disclosed. Many modifications and variations are possible in light of the above teaching. The intention is that the scope of the present invention not be limited by this detailed description, but rather by the appended claims.

Claims

1. A receiver with discontinuous automatic gain control (AGC), comprising: A front end having a low-noise amplifier (LNA), a low-pass filter (LPF), and a programmable gain amplifier (PGA) connected in series to amplify a received signal applied to the input of the LNA, thereby generating an amplified output, wherein the gain of the front end can be adjusted according to a gain setting; A rectifier that rectifies the amplified output from the front end to generate an output voltage; A data converter that receives the output voltage from the rectifier and generates binary data; A frame detector that receives the binary data from the data converter and activates a frame signal synchronized with the frame of the binary data; A level detector that compares the output voltage from the rectifier with a first threshold to generate a first comparison result, and compares it with a second threshold to generate a second comparison result, wherein the second threshold is greater than the first threshold; An AGC controller that is activated by the frame signal from the frame detector for a new frame. The AGC controller initializes the gain setting to the maximum gain according to the frame signal. The AGC controller reduces the gain setting according to the first and second comparison results. When the first and second comparison results indicate that the output voltage is between the first threshold and the second threshold, the AGC controller locks the gain setting. Thereby, the gain setting is adjusted and locked according to the frame signal until the AGC controller is activated again for the next new frame.

2. The receiver according to claim 1, wherein the AGC controller locks the gain setting at the beginning of a frame before the data payload in the frame, and wherein the gain setting does not change during the data payload and only changes at the beginning of the frame.

3. The receiver according to claim 2, wherein the frame is an on-off keying (OOK) modulation frame, wherein a transmitted carrier represents the transmitted data 1, and wherein no transmitted carrier represents the transmitted data 0.

4. The receiver according to claim 3, wherein the frame further includes an AGC synchronization field, wherein the carrier continuously appears in the received signal during the AGC synchronization field, and wherein the carrier does not appear in the received signal between frames; wherein within the frame, the AGC synchronization field is received before the received data payload, and the data payload has two time periods: a time period when the carrier appears when transmitting data 1, and a time period when the carrier does not appear when transmitting data 0; Among them, when the AGC synchronization field is received, the gain setting is adjusted; wherein when the data payload is received, the gain setting does not change and remains locked; thereby, automatic gain control (AGC) is performed during the AGC synchronization field before the data payload in the frame is received.

5. The receiver according to claim 3, wherein the gain setting further comprises: PGA gain setting for setting the gain of the PGA, LNA gain setting for setting the gain of the LNA; wherein the AGC controller reduces the PGA gain setting to the minimum value before reducing the LNA gain setting from the maximum value, wherein, by reducing the gain of the PGA before reducing the gain of the LNA, the LNA operates at the maximum possible gain.

6. The receiver according to claim 3, wherein the gain setting further comprises: PGA gain setting for setting the gain of the PGA, LPF gain setting for setting the gain of the LPF, and LNA gain setting for setting the gain of the LNA; wherein the AGC controller reduces the PGA gain setting to the minimum value before reducing the LNA gain setting from the maximum value; wherein the AGC controller reduces the LPF gain setting to the minimum value before reducing the LNA gain setting from the maximum value, wherein, by reducing the gain of the PGA and reducing the gain of the LPF before reducing the gain of the LNA, the LNA operates at the maximum possible gain.

7. The receiver according to claim 6, wherein the front end further comprises: a local oscillator that generates a local clock, the frequency of the local clock being lower than the carrier frequency of the received signal; a mixer that mixes the output of the LNA with the local clock of the local oscillator to generate an input to the LPF; wherein the output of the LPF drives the input of the PGA, and the PGA generates the amplified output to the rectifier.

8. The receiver according to claim 6, wherein when no carrier is received on the received signal, the frame detector activates the frame signal between frames.

9. The receiver according to claim 8, further comprising: a power-down signal that is activated by the AGC controller when the gain setting is locked, wherein the power-down signal is de-activated by the frame signal of the frame detector.

10. The receiver according to claim 9, wherein the power-down signal from the AGC controller is applied to the level detector, and when the gain setting is locked, the power-down signal disables the level detector from comparing the output voltage.

11. The receiver according to claim 10, wherein the level detector further comprises: a first comparator that compares the output voltage with a first threshold to generate a first comparison result, and when the gain setting is locked, the first comparator is disabled by the power-down signal; a second comparator that compares the output voltage with a second threshold to generate a second comparison result, and when the gain setting is locked, the second comparator is disabled by the power-down signal.

12. A method for adjusting the gain of a receiver, comprising: (a) detecting a gap between frames and causing an automatic gain control (AGC) controller to reset during the gap before the start of a frame; when the AGC controller is reset, resetting the gain setting to the maximum gain; comparing the amplified voltage with a pair of thresholds to generate a comparison result; The amplified voltage is generated by gain-amplifying the received signal, and the gain is determined by the gain setting; When the comparison result indicates that the amplified voltage is not between the pair of thresholds, gradually adjust the gain setting to reduce the gain; When the comparison result indicates that the amplified voltage is between the pair of thresholds, lock the gain setting at a locked gain setting; Use the locked gain setting to amplify the received signal to recover the data payload in the frame; For subsequent frames, repeat starting from (a).

13. The method according to claim 12, wherein, Detecting the gap between frames includes: detecting the absence of a carrier on the received signal within a predetermined time period; wherein gradually adjusting the gain setting further includes: receiving a continuous carrier on the received signal and, during the AGC synchronization mode at the start of the frame after the gap between frames, generating the amplified voltage from the continuous carrier.

14. The method according to claim 13, wherein the frame is an on-off keying (OOK) modulated frame, wherein during the data payload, the transmitted carrier represents the transmitted data 1 and the non-transmission of the carrier represents the transmitted data 0.

15. The method according to claim 13, wherein gradually adjusting the gain setting further comprises: Before reducing the low-noise amplifier (LNA) gain setting, reduce the programmable gain amplifier (PGA) gain setting until the minimum PGA gain setting is reached; wherein the amplified voltage is generated by amplifying the received signal using the LNA and further amplifying the output of the LNA using the PGA; wherein the gain of the LNA is determined by the LNA gain setting and the gain of the PGA is determined by the PGA gain setting.

16. The method according to claim 15, wherein locking the gain setting further includes: when the minimum gain setting is reached and the comparison result indicates that the amplified voltage is not between the pair of thresholds, locking the gain setting to the minimum gain setting.

17. The method according to claim 13, further comprising: receiving a continuous carrier on the received signal and generating the amplified voltage from the continuous carrier during the AGC synchronization mode at the start of the frame after the gap between frames.

18. An adjustable-gain receiver, comprising: a receiver input that receives frames; a low-noise amplifier (LNA) that amplifies the receiver input with a gain determined by an LNA gain setting to produce a first amplified signal; a low-pass filter (LPF) that filters the first amplified signal; a programmable gain amplifier (PGA) that amplifies the first amplified signal with a gain determined by a PGA gain setting to produce a second amplified signal; a rectifier that rectifies the second amplified signal to produce an output voltage; a coding decision circuit that compares the output voltage with a data threshold to produce a data stream having data 1 and data 0 values; a frame detector that checks the data stream and activates a reset signal when a data 0 signal of a predetermined length between frames is detected; A level detector that compares the output voltage with a first voltage to produce a first result and compares the output voltage with a second voltage to produce a second result, wherein the first voltage is less than the second voltage; An automatic gain control (AGC) controller that resets the PGA gain setting and the LNA gain setting to maximum settings according to the reset signal of the frame detector. During the AGC synchronization mode at the start of a frame, the AGC controller continuously reduces the PGA gain setting and then continuously reduces the LNA gain setting until a lock signal is issued when the first result and the second result indicate that the output voltage is between the first voltage and the second voltage; Wherein, after the lock signal is issued, the AGC controller does not adjust the PGA gain setting and the LNA gain setting for the remainder of the frame, including when receiving the data payload of the frame.

19. The adjustable gain receiver according to claim 18, wherein the AGC synchronization mode is a continuous sequence of data 1 signals.

20. The adjustable gain receiver according to claim 19, wherein, A carrier is transmitted to the receiver input to represent a transmitted data 1 signal; Wherein, no carrier is transmitted to the receiver input to represent a transmitted data 0 signal; Wherein, the frame is an on-off keying (OOK) modulation frame.

Images