An emulator that supports asynchronous communication interfaces

Abstract

This invention introduces a simulator supporting asynchronous communication interfaces, relating to the field of chip simulation and debugging. The simulator comprises four parts: a chip function debugging module, a chip function simulation module, a register module, and a timing interface module. It reuses the chip's system RAM to store data transmitted and received by the communication interface. The addition of the register module and timing interface module implements a parallel master interface for asynchronous communication. The simulator adopts an asynchronous parallel interface design with master-slave device handshaking, ensuring compatibility with interface devices of various speeds while maximizing communication speed. This invention designs a simulator supporting asynchronous communication interfaces, enabling interface expansion for debugging functions, accelerating chip program debugging, and improving development efficiency.

Description

Technical Field

[0001] This invention relates to the field of chip simulation and debugging, and specifically to the design of a simulator with an asynchronous communication interface. Background Technology

[0002] Chip emulators typically use JTAG or SWD interfaces to connect to debug adapters for program downloading and debugging. These adapters are dedicated debugging devices, which hinders the expansion of debugging capabilities. Therefore, when designing an emulator, it is desirable to implement a high-speed interface that supports connection to other peripheral chips for rapid import and export of debugging data. Commonly used serial interfaces such as USB and SPI are complex to design and debug, and the peripheral chips connected to the emulator also require such interfaces, posing challenges to the design of the emulator interface and peripheral circuits. To address this problem, this invention proposes an emulator with a simple structure, good compatibility, and high communication speed using an asynchronous communication interface. Summary of the Invention

[0003] The technical problem solved by this invention is how to design an emulator that supports asynchronous communication interfaces. To ensure compatibility with different operating speeds of peripheral connection chips and maximize communication speed, an asynchronous parallel interface design with mutual handshaking is adopted.

[0004] The simulator of this invention reuses the system RAM of the chip, adds a register module and a timing interface module, and implements an asynchronous communication parallel master interface. The master interface includes the following signals: enable signal O_AEN, length enable signal O_LEN, master request signal O_REQ, slave acknowledge signal I_ACK, slave exception signal I_ERR, and data bus IO_DATA. These master interface signals are used to interconnect with the slave interfaces of peripheral slave devices to realize data transmission request and data transmission functions.

[0005] The emulator consists of four parts: a chip function debugging module, a chip function simulation module, a register module, and a timing interface module. The functions of each component are described below:

[0006] The chip function debugging module enables debugging of the chip function simulation module;

[0007] The chip function simulation module simulates the chip's functions. The chip function simulation module includes a system RAM, which is used to store data transmitted and received by the communication interface.

[0008] The register module implements a set of registers. The chip functional simulation module accesses this set of registers to configure the timing interface module and transmit data through the communication interface.

[0009] The timing interface module generates the main interface signal of the asynchronous communication interface, generates data transmission and reception timing, and implements system RAM read and write, exception handling, data transmission and reception and verification functions.

[0010] The connection relationships of each component are as follows:

[0011] The chip function simulation module is connected to the chip function debugging module and the register module, and the timing interface module is connected to the register module and the chip function simulation module.

[0012] The register module in the simulator consists of five registers: control register, status register, address register, length register, and timer register. User programs access these registers to perform operations such as data transmission and reception and exception handling.

[0013] The control register is used to configure the functions of the communication interface and initiate transmit and receive operations.

[0014] The status register is used to store the working status and fault flags of the communication interface;

[0015] The address register configures the slave device address accessed by the interface and the storage address of data received or sent from the system RAM;

[0016] The length register stores the length of data received or transmitted in the system RAM.

[0017] The timer register is used to configure the delay for reading and writing IO_DATA data and the timeout period for I_ACK response.

[0018] The timing interface module in the simulator consists of three modules: a transmission control module, an exception handling module, and a data processing and verification module.

[0019] The transmission control module outputs O_AEN, O_LEN, and O_REQ interface signals based on the configuration operation of the control register and the level state of I_ACK. The transmission control module implements the timing sequence for interface data transmission and reception based on the configuration values ​​of the address register, length register, and timer register. The transmission control module connects to the register module to achieve data interaction with its five registers. The transmission control module connects to the exception handling module to control exception handling. The transmission control module connects to the data processing and verification module to control the data transmission and verification functions of the communication interface.

[0020] The exception handling module performs communication exception handling and generates a status flag based on the I_ERR interface signal and the verification flag output by the data processing and verification module. The exception handling module outputs the generated status flag to the transmission control module, which then updates the status flag to the status register.

[0021] The data processing and verification module is connected to the system RAM in the chip functional simulation module. It performs read and write operations on the system RAM through the RAM access interface and generates the IO_DATA signal under the control of the transmission control module. It can send data in the system RAM out through IO_DATA or receive data from IO_DATA and store it in the system RAM. The data processing and verification module performs data verification during the receiving and sending process and outputs the verification result to the exception handling module.

[0022] The asynchronous communication interface implemented by the simulator of this invention divides the timing of a data transmission frame into four fields: address field, length field, data field, and checksum field.

[0023] When O_AEN is high, it indicates that the data on IO_DATA is an address field. The address field includes read / write bits, parity bits, and the slave device address accessed during transmission. A read / write bit of 1 indicates that this transmission is a read operation, and 0 indicates a write operation. A parity bit of 1 indicates that a parity field exists, and 0 indicates that there is no parity field.

[0024] The length field, when O_LEN is high, indicates that the data on the current IO_DATA is a length field, and the value of the length field is the length of the received or sent data field;

[0025] After the data field and length field are transmitted, the value of the length field specifies the length of the data on IO_DATA, which is the data field. At this time, O_AEN and O_LEN are both low.

[0026] In the check field, when the check bit of the address field is 1, the data on IO_DATA after the data field is transmitted is the check data. At this time, both O_AEN and O_LEN are low. The check field checks all the data in the address field, length field, and data field. The length of the check field is user-defined according to the check algorithm used.

[0027] The number of IO_DATA transmissions required for each of the above four fields depends on the bus width of IO_DATA and the length of data to be sent and received for each field. The interface designer can customize the communication protocol according to the specific requirements of the interface.

[0028] In the emulator communication interface of this invention, O_REQ and I_ACK serve as a pair of handshake signals to control the transmission process, supporting communication with devices of various speeds. O_REQ can only go high when I_ACK is low, and O_REQ can only go low when I_ACK is high. I_ACK can only go high after O_REQ goes high, and I_ACK can only go low after O_REQ goes low. The emulator achieves synchronous data transmission with the connected interface device through O_REQ and I_ACK.

[0029] The slave device connected to the emulator feeds back any anomalies that occur during communication to the emulator in real time via the I_ERR signal. When the emulator detects that I_ERR goes high, it stops the current transmission operation and performs fault tolerance processing. Attached Figure Description

[0030] Figure 1 This is a diagram of the simulator structure that supports asynchronous communication interfaces.

[0031] Figure 2 This is a timing diagram of the asynchronous communication interface writing data to IO_DATA.

[0032] Figure 3 This is a timing diagram of the asynchronous communication interface reading data from IO_DATA.

[0033] Figure 4 This is a timing diagram of a single data frame being sent via an asynchronous communication interface.

[0034] Figure 5 This is a timing diagram for receiving a single frame of data using an asynchronous communication interface. Detailed Implementation

[0035] The timing design of the simulator and communication interface of the present invention will be described in detail below with reference to the accompanying drawings.

[0036] like Figure 1 As shown, emulator 1 comprises four parts: chip function debugging module 2, chip function simulation module 3, register module 4, and timing interface module 5. Chip function simulation module 3 adds two access interfaces: a register access interface connecting to the register module, and a RAM access interface connecting to the timing interface module 5. By adding register module 4 and timing interface module 5, emulator 1 implements an external asynchronous communication parallel master interface for connecting to peripheral slave devices to achieve data interaction.

[0037] The simulator implements the sending and receiving of a frame of data through an asynchronous communication interface. The timing design of the interface is described below.

[0038] like Figure 2The diagram shows the timing for writing data to IO_DATA. The white segment of the device_io_rd signal indicates that after the slave device connected to the emulator detects O_REQ changing from low to high, it reads data from IO_DATA and processes it. After data processing is complete, the slave device sets I_ACK high to notify the emulator that the IO_DATA data has been read. t_io2reqr is the delay for writing data to IO_DATA, representing the stable delay of IO_DATA data, which is configured by the timer register. When O_REQ changes from low to high, it indicates that IO_DATA is ready and the slave device can read the IO_DATA data. After the slave device detects O_REQ changing from high to low, it sets I_ACK low. Only when I_ACK is low can the master device initiate the next IO_DATA data transmission.

[0039] The simulator's write operation to IO_DATA can be divided into three cases:

[0040] 1) The send_aen write operation is used to send data to the address field;

[0041] 2) The send_len write operation is used to send data in the length field;

[0042] 3) send_data write operation, used to send data to data fields and validation fields.

[0043] like Figure 3 The diagram shows the timing diagram for reading data from IO_DATA. The white segment of the device_io_wr signal indicates that the slave device connected to the emulator detects the O_REQ transition from low to high, prepares to send data, and outputs data to IO_DATA. Afterward, the slave device sets I_ACK high, notifying the emulator to read the data from IO_DATA. The white segment of the master_io_rd signal indicates that the emulator reads data from IO_DATA and processes it. t_ackr2io represents the delay for reading data from IO_DATA, indicating that the emulator waits for the IO_DATA data to stabilize; this is configured by the timer register. The emulator's data read operation from IO_DATA is used to receive data in both the data field and the checksum field.

[0044] like Figure 4 The diagram shown is a timing diagram for transmitting one frame of data, which is divided into four stages:

[0045] 1) In the send rwn / chk / addr stage, the address field data is sent. The read / write bit rwn is fixed at 0. In this specific implementation, the check bit chk is 1. This frame transmission includes the data transmission of the check field. When the address field data needs to be transmitted multiple times, the first transmitted IO_DATA data includes the read / write bit, check bit, and low address bit. The high address bit is transmitted later.

[0046] 2) In the send len stage, the length field data is sent, indicating the length of the data field to be sent in this frame;

[0047] 3) In the send data phase, the simulator sends the data from the data field;

[0048] 4) During the send chk stage, the checksum bit of the address field exists when it is 1, and the simulator sends the data of the checksum field.

[0049] like Figure 5 The diagram shown is a timing diagram for receiving a single data frame, divided into four stages:

[0050] 1) In the send rwn / chk / addr stage, the data in the send address field is sent in the same timing as the data in the send address field of a data frame, except that the value of the read / write bit rwn is fixed at 1, indicating that this frame is a data reception operation;

[0051] 2) In the send len stage, the length field data is sent, indicating the length of the data field to be received in this frame;

[0052] 3) In the read data phase, the simulator receives data from the data field;

[0053] 4) During the read chk stage, the check bit of the address field exists when it is 1, and the simulator receives the data of the check field.

[0054] The above embodiments are only used to illustrate and not limit the technical solutions of the present invention. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that modifications or equivalent substitutions can still be made to the present invention without departing from the spirit and scope of the present invention. Any modifications or partial substitutions should be covered within the scope of the claims of the present invention.

Claims

1. An emulator supporting an asynchronous communication interface, characterized in that, The system RAM of the multiplexed chip is used to implement an asynchronous communication parallel main interface. The main interface includes the following signals: address enable signal O_AEN, length enable signal O_LEN, master request signal O_REQ, slave acknowledge signal I_ACK, slave exception signal I_ERR, and data bus IO_DATA. The simulator includes four parts: chip function debugging module, chip function simulation module, register module, and timing interface module. The chip function debugging module enables debugging of the chip function simulation module; The chip function simulation module simulates the chip function. The chip function simulation module includes a system RAM, which is used to store the data transmitted and received by the communication interface. The register module implements a set of registers. The chip functional simulation module accesses this set of registers to configure the timing interface module and transmit data through the communication interface. The timing interface module generates the main interface signal of the asynchronous communication interface, generates data transmission and reception timing, and implements system RAM read and write, exception handling, data transmission and reception and verification functions. The timing of a single frame of data transmission in the asynchronous communication interface is divided into four fields: address field, length field, data field, and checksum field. When O_AEN is high, it indicates that the data on IO_DATA is an address field. The address field includes read / write bits, parity bits, and the slave device address accessed during transmission. A read / write bit of 1 indicates that this transmission is a read operation, and 0 indicates a write operation. A parity bit of 1 indicates that a parity field exists, and 0 indicates that there is no parity field. The length field, when O_LEN is high, indicates that the data on the current IO_DATA is a length field, and the value of the length field is the length of the received or sent data field; After the data field and length field are transmitted, the value of the length field specifies the length of the data on IO_DATA. When the check bit of the address field is 1, the data on IO_DATA after the data field is transmitted is the check data. The check field verifies all data in the address field, length field, and data field. The slave device connected to the emulator feeds back any abnormalities that occur during the communication process to the emulator in real time through the I_ERR signal. When the emulator detects that I_ERR goes high, it stops the current transmission operation and performs fault tolerance processing. The chip function simulation module is connected to the chip function debugging module and the register module, and the timing interface module is connected to the register module and the chip function simulation module.

2. The emulator supporting asynchronous communication interface according to claim 1, characterized in that, The register module consists of five registers: a control register, a status register, an address register, a length register, and a timer register. The control register is used to configure the functions of the communication interface and initiate transmit and receive operations. The status register is used to store the working status and fault flags of the communication interface; The address register configures the slave device address accessed by the interface and the storage address of data received or sent from the system RAM; The length register stores the length of data received or transmitted in the system RAM. The timer register is used to configure the delay for reading and writing IO_DATA data and the timeout period for I_ACK response.

3. The emulator supporting asynchronous communication interface according to claim 1, characterized in that, The timing interface module consists of three modules: a transmission control module, an exception handling module, and a data processing and verification module. The transmission control module outputs O_AEN, O_LEN, and O_REQ interface signals according to the configuration operation of the control register and the level state of I_ACK, thereby realizing the timing of the interface data transmission and reception operations. The exception handling module performs communication exception handling and generates a status flag based on the I_ERR interface signal and the verification flag output by the data processing and verification module. The data processing and verification module is connected to the system RAM in the chip functional simulation module. It performs read and write operations on the system RAM through the RAM access interface and generates the IO_DATA signal under the control of the transmission control module. The data processing and verification module performs data verification during the receiving and sending process and outputs the verification result to the exception handling module.

4. The emulator supporting asynchronous communication interface according to claim 1, characterized in that, O_REQ and I_ACK are a pair of handshake signals that control the transmission process. O_REQ can only go high when I_ACK is low, and O_REQ can only go low when I_ACK is high. I_ACK can only go high after O_REQ goes high, and I_ACK can only go low after O_REQ goes low.

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