Error detection and correction apparatus and related methods

Abstract

The present application provides a kind of error detection and correction device, including decision feedback equalizer (DFE), decision circuit, error detection circuit and error correction circuit.DFE equalizes data signal to generate first equalization signal.Decision circuit performs hard decision to first equalization signal to generate symbol decision signal.Error detection circuit performs forward error detection at the symbol position of the continuous symbol included in symbol decision signal to detect the first position of suspected error affecting at least one symbol in symbol decision signal.Error correction circuit performs error correction to symbol decision signal in response to the first position of suspected error detected by error detection circuit.Accordingly, the present application also provides a kind of error detection and correction method.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application generally relate to the field of data communications, and more particularly, to an error detection and correction device and related method capable of detecting the first location of a suspected error and performing forward error propagation path tracking to provide information needed for subsequent error correction. BACKGROUND

[0002] In high-speed data communication systems, existing filtering and equalization schemes are insufficient to support challenging channels and next-generation Ethernet. For example, detection of a received signal in a data communication system is challenging due to a variety of factors such as noise, crosstalk, and inter-symbol interference (ISI). A typical decision-feedback equalizer (DFE) is capable of canceling post-cursor ISI by using one or more previous symbols (e.g., one or more previous hard decisions). However, due to the feedback nature that relies on one or more previous hard decisions, a typical DFE can cause error propagation. Maximum likelihood sequence detection (MLSD) is a commonly used technique that utilizes and further removes ISI to handle noise. However, MLSD has a higher level of implementation complexity and a higher level of power and memory consumption. In some high-speed Ethernet standards, a simple method called 1+D precoding can use inter-symbol information of a DFE to cancel DFE error propagation. However, it requires a precoding engine at the transmit (TX) end and a deprecoding engine at the receive (RX) end. In addition, additional errors are generated after error propagation termination, and the first random error cannot be canceled. Therefore, there is a need for a low-cost error canceller that utilizes inter-symbol information of a DFE to not only compensate for propagated errors but also compensate for the first random error. SUMMARY

[0003] It is an object of the present application to provide an error detection and correction device and related method capable of detecting the first location of a suspected error and performing forward error propagation path tracking to provide information needed for subsequent error correction.

[0004] According to a first aspect of the present disclosure, an example error detection and correction apparatus is provided. The example error detection and correction apparatus includes a decision feedback equalizer (DFE), a decision circuit, an error detection circuit, and an error correction circuit. The DFE is configured to equalize a data signal to generate a first equalized signal. The decision circuit is configured to perform a hard decision on the first equalized signal to generate a symbol decision signal. The error detection circuit is configured to perform a forward error detection at a symbol position of consecutive symbols included in the symbol decision signal to detect a first position of a suspected error affecting at least one symbol in the symbol decision signal. The error correction circuit is configured to perform an error correction (also described as “error correction”) on the symbol decision signal in response to the first position of the suspected error detected by the error detection circuit.

[0005] In some embodiments, the error detection and correction apparatus further includes a feed forward equalizer (FFE) configured to process a received signal to generate a second equalized signal as the data signal.

[0006] In some embodiments, the suspected error detected by the error detection circuit is a single error affecting only a single symbol in the symbol decision signal.

[0007] In some embodiments, the suspected error detected by the error detection circuit is a dense error affecting multiple symbols in the symbol decision signal.

[0008] In some embodiments, the data signal is derived from a pulse amplitude modulation (PAM) signal.

[0009] In some embodiments, the consecutive symbols include a previous symbol at a previous symbol position and a current symbol at a current symbol position; the first equalized signal includes a previous sample and a current sample, wherein the previous symbol is a hard decision result of the previous sample, the current symbol is a hard decision result of the current sample, and the error detection circuit performs the forward error detection by checking whether an absolute difference between the previous sample and the previous symbol is not greater than a predetermined threshold, whether an absolute difference between the current sample and the current symbol is greater than the predetermined threshold, and whether an absolute value of the current sample is less than a maximum PAM level.

[0010] In some embodiments, the error correction circuit is configured to perform a forward error propagation path tracing starting from the first position detected by the error detection circuit to select an error propagation path having a propagation length; wherein the error correction performed on the symbol decision signal is performed at least according to the propagation length.

[0011] In some embodiments, the forward error propagation path tracing is performed based on a two-state trellis.

[0012] In some embodiments, the error detection circuit is further configured to control activation of the error correction circuit during the forward error detection.

[0013] According to a second aspect of the present invention, an exemplary error detection and correction method is provided. The error detection and correction method includes: performing decision feedback equalization on a data signal to generate a first equalized signal; performing hard decision on the first equalized signal to generate a symbol decision signal; performing forward error detection on symbol positions of consecutive symbols included in the symbol decision signal to detect the leading position of a suspected error affecting at least one symbol in the symbol decision signal; and performing error correction on the symbol decision signal in response to the leading position of the suspected error.

[0014] In some embodiments, the error correction circuit is activated in response to the first position of the suspected error being detected by the error detection circuit.

[0015] In some embodiments, the error detection and correction method further includes: performing feedforward equalization on the received signal to generate a second equalized signal as the data signal.

[0016] In some embodiments, the suspected error is a single error that affects only a single symbol in the symbol decision signal.

[0017] In some embodiments, the suspected error is a cluster of errors that affect multiple symbols in the symbol decision signal.

[0018] In some embodiments, the data signal is derived from a pulse amplitude modulated (PAM) signal.

[0019] In some embodiments, the continuous codewords include a previous codeword located at the previous codeword position and a current codeword located at the current codeword position; the first equalized signal includes a previous sample and a current sample, wherein the previous codeword is a hard decision result of the previous sample, and the current codeword is a hard decision result of the current sample; and performing the forward error detection includes checking the following conditions: whether the absolute difference between the previous sample and the previous codeword is not greater than a predetermined threshold; whether the absolute difference between the current sample and the current codeword is greater than the predetermined threshold; and whether the absolute value of the current sample is less than a maximum PAM level.

[0020] In some embodiments, performing the error correction includes: performing forward error propagation path tracing starting from the first position to select an error propagation path having a propagation length; and performing the error correction based at least on the propagation length.

[0021] In some embodiments, the forward error propagation path tracing is performed based on a two-state grid.

[0022] In some embodiments, performing the forward error detection further comprises: controlling activation of the error correction during the forward error detection.

[0023] In some embodiments, the error correction is activated in response to the error detection circuit detecting the first position of the suspected error.

[0024] Those skilled in the art will readily appreciate these and other objects of the present invention after reading the following detailed description of the preferred embodiments shown in the accompanying drawings. Detailed description will be given in the following embodiments with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The present invention may be more fully understood by reading the following detailed description and by referring to the examples given in the accompanying drawings, in which:

[0026] Figure 1 FIG. 1 is a schematic diagram of an error detection and correction device according to an embodiment of the present invention.

[0027] Figure 2 FIG. 4 is a schematic diagram of a TBEE according to an embodiment of the present invention.

[0028] Figure 3 is a schematic diagram showing the distribution of samples transmitted via an AWGN channel.

[0029] Figure 4 FIG. 4 is a schematic diagram of a two-state grid for error propagation path selection according to an embodiment of the present invention.

[0030] Figure 5 FIG. 4 is a schematic diagram showing an original path and multiple candidate paths according to an embodiment of the present invention.

[0031] Figure 6 FIG. 4 is a schematic diagram illustrating the concept of calculating the branch metric of the first branch according to an embodiment of the present invention.

[0032] Figure 7 FIG. 4 is a schematic diagram illustrating a concept of calculating a branch metric of a k-th propagation branch according to an embodiment of the present invention.

[0033] Figure 8 FIG. 4 is a schematic diagram illustrating a concept of calculating a branch metric of a k-th tail branch according to an embodiment of the present invention.

[0034] Figure 9 FIG. 4 is a flow chart of an error detection and correction method according to an embodiment of the present invention.

[0035] In the following detailed description, for illustrative purposes, numerous specific details are set forth to enable those skilled in the art to more thoroughly understand the embodiments of the present invention. However, it is apparent that one or more embodiments may be practiced without these specific details, and different embodiments may be combined as needed, and the present invention should not be limited to the embodiments illustrated in the accompanying drawings. DETAILED DESCRIPTION

[0036] The following description is of preferred embodiments of the present invention and is intended only to illustrate the technical features of the present invention and is not intended to limit the scope of the invention. Certain terms are used throughout the specification and claims to refer to specific components. Those skilled in the art will appreciate that manufacturers may use different names for the same components. Therefore, this specification and claims do not distinguish components by name, but rather by functional differences. The terms "component," "system," and "device" used in this invention may refer to entities related to a computer, which may be hardware, software, or a combination of hardware and software. The terms "including" and "comprising" used in the following description and claims are open-ended and should be interpreted as meaning "including, but not limited to..." Furthermore, the term "coupled" refers to an indirect or direct electrical connection. Therefore, when a device is described as being coupled to another device, this means that the device may be directly electrically connected to the other device or indirectly electrically connected to the other device through other devices or connections.

[0037] Corresponding numerals and symbols in the various figures of the drawings generally refer to corresponding parts unless otherwise indicated. The drawings are drawn to clearly illustrate the relevant parts of the embodiments and are not necessarily drawn to scale.

[0038] As used herein, the terms "substantially" or "approximately" mean that a person skilled in the art is able to solve the desired technical problem and substantially achieve the desired technical effect within an acceptable range. For example, "approximately equal to" means that a certain deviation from "exactly equal to" is acceptable to a person skilled in the art without affecting the accuracy of the result.

[0039] Figure 1 1 is a schematic diagram of an error detection and correction device according to an embodiment of the present invention. The error detection and correction device 100 may be part of a receiver in a data communication system. In this embodiment, the error detection and correction device 100 is a digital circuit, including a feed-forward equalizer (FFE) 102, a decision-feedback equalizer (DFE) 104, a trellis-based error eliminator (TBEE) 106, and a decision circuit (also described as a "decision circuit") 108. It should be noted that Figure 1Only the components relevant to the present invention are shown. In practice, the error detection and correction device 100 is allowed to include additional components for other specified functions. The FFE (feed forward equalizer) 102 can be implemented by an m-tap (m-tap) FFE, which has m multipliers 112, (m-1) delay elements 114 and (m-1) adders 116, wherein the m FFE coefficients f1 to f m (m≥1) are applied to m multipliers 112 respectively. However, this is for illustrative purposes only and is not intended to limit the present invention. In fact, the FFE (feed forward equalizer) 102 can adopt any suitable FFE structure. That is, the present invention has no limitation on the design of the FFE. The FFE (feed forward equalizer) 102 is configured to process a received signal S_IN to generate an equalized signal S_FFE as a data signal for subsequent DFE (decision feedback equalizer) 104 to process. For example, a pulse amplitude modulation (PAM) signal is generated and transmitted from a transmitter of a data communication system to a receiver of the data communication system through a channel, and the received signal S_IN is a digital signal obtained from the PAM (pulse amplitude modulation) signal, that is, the data signal (such as the equalized signal S_FFE) is derived from the PAM (pulse amplitude modulation) signal. Taking a 4-level PAM (PAM4) signal as an example, there are four symbols {-3, -1, +1, +3}, and each symbol corresponds to two bits. For example, the four two-bit combinations 00, 01, 11, and 10 can be associated with amplitudes of -3, -1, +1, and +3, respectively. It should be noted that FFE (feed-forward equalizer) 102 is optional, depending on actual design considerations.

[0040] The DFE (decision feedback equalizer) 104 is configured to equalize a data signal obtained from a received signal S_IN to generate an equalized signal S_DFE. For example, the equalized signal S_FFE output from the FFE (feedforward equalizer) 102 is used as an input signal of the DFE (decision feedback equalizer) 104. The DFE (decision feedback equalizer) 104 can be implemented by an n-tap DFE. For example, the n-tap DFE has n multipliers 118, (n-1) delay elements 120, (n-1) adders 122, and a plurality of combining circuits 123 and 124, wherein the n DFE coefficients h1 to h n(n ≥ 1) are applied to n multipliers 118, respectively. (It should be noted that the present invention does not distinguish different parameters / components by different superscripts and subscripts; for example, h1 and h2 refer to the same thing.) However, this is for illustrative purposes only and is not intended to limit the present invention. In practice, DFE (Decision Feedback Equalizer) 104 may employ any suitable DFE architecture. In other words, the present invention imposes no limitations on the DFE design.

[0041] Combining circuit 123 in DFE (Decision Feedback Equalizer) 104 is configured to combine a data signal (e.g., equalized signal S_FFE obtained by equalizing received signal S_IN) with the signal output by last-stage adder 122 in DFE (Decision Feedback Equalizer) 104 to generate an equalized signal S_DFE. This equalized signal S_DFE includes multiple samples, which are soft data. For example, combining circuit 123 can be implemented by a subtractor (which can be implemented by an adder configured to perform subtraction).

[0042] The decision circuit 108 is configured to perform a hard decision on the equalized signal S_DFE to generate a symbol decision signal S_D. The symbol decision signal S_D includes multiple symbols, which are hard data. For example, the decision circuit 108 may be a slicer. In the case where the received signal S_IN is derived from a PAM4 signal, each of the equalized signals S_FFE and S_DFE carries soft data, and the symbol decision signal S_D carries hard data (i.e., each symbol is determined by the slicer to be one of the four symbols {-3, -1, +1, +3}). The symbol decision signal S_D is fed back to the DFE (decision feedback equalizer) 104. In particular, the (n-1) previous symbols output by the decision circuit 108 are stored in the (n-1) delay components 120 and used to equalize the current sample in the data signal (e.g., the equalized signal S_FFE obtained after the FFE 102 equalizes the received signal S_IN).

[0043] In this embodiment, the combining circuit 124 in the DFE (decision feedback equalizer) 104 is configured to combine the equalized signal S_DFE and the symbol decision signal S_D to generate an error signal S_E. For example, the combining circuit 124 can be implemented by a subtracter (which can be implemented by an adder configured to perform subtraction) to output the difference between the equalized signal S_DFE and the symbol decision signal S_D (specifically, the difference between each sample (soft data) contained in the equalized signal S_DFE and the corresponding symbol (hard data) contained in the symbol decision signal S_D) as the error signal S_E. It should be noted that the combining circuit 124 is optional depending on actual design considerations.

[0044] The TBEE (trellis-based error eliminator) 106 is configured to eliminate or reduce errors of symbols introduced into the symbol decision signal S_D due to the feedback characteristic of the DFE (decision feedback equalizer). In this embodiment, the TBEE (trellis-based error eliminator) 106 includes an error detection circuit 126 and an error correction circuit 128, and the TBEE (trellis-based error eliminator) 106 eliminates or reduces errors of symbols in the symbol decision signal S_D according to the DFE coefficients (e.g., h1~h4) and the symbol decision signal S_D. n, where n ≥ 1), the equalization signal S_DFE, the symbol decision signal S_D, and the error signal S_E are operated on. The error detection circuit 126 is configured to perform forward error detection (FED) at the symbol positions of consecutive symbols included in the symbol decision signal S_D to detect the head position (also described as the "first position") of a suspected error that affects at least one symbol in the symbol decision signal S_D. For example, the suspected error detected by the error detection circuit 126 can be a single error that only affects a single symbol in the symbol decision signal S_D. That is, the error occurring at the current symbol will not propagate to the next symbol through the feedback characteristics of the DFE (decision feedback equalizer), and the propagation length is equal to zero, which means that the tail position of the suspected error is the same as the head position of the suspected error. For another example, the suspected error detected by the error detection circuit 126 may be a burst error, which affects a series of symbols (i.e., multiple symbols) included in the symbol decision signal S_D. Specifically, the present invention uses multiple consecutive symbols as an example for illustration, but the present invention is not limited thereto. In other words, the error occurring at the current symbol propagates to the following symbols through the feedback characteristics of the DFE (decision feedback equalizer), and the propagation length is equal to a non-zero value, which means that the tail position of the suspected error is different from the head position of the suspected error.

[0045] The error correction circuit 128 is configured to perform error correction (also described as "error correction") on the symbol decision signal S_D in response to the leading position of the suspected error detected by the error detection circuit 126, and generate a final symbol sequence S_OUT. For a PAM4 signal, the final symbol sequence S_OUT is a symbol sequence in which each symbol is one of four symbols {-3, -1, +1, +3} and includes corrected symbols generated by the TBEE (Trellis-Based Error Eliminator) 106. For example, the error correction circuit 128 is configured to perform forward error propagation path tracking starting from the first position detected by the error detection circuit 126 to select an error propagation path having a propagation length (which can be a zero value or a non-zero value); and the information of the propagation length is referenced by the error correction circuit 128 to perform error correction on the codeword decision signal S_D and thereby correct / correct the erroneous codewords.

[0046] Since the focus of the present invention is the proposed error detection and correction technology adopted by the TBEE (trellis-based error eliminator) 106, ordinary technicians in this field should easily understand the principles of FFE (feed forward equalizer) 102, DFE (decision feedback equalizer) 104 and decision circuit 108. Therefore, for the sake of brevity, further description of FFE (feed forward equalizer) 102, DFE (decision feedback equalizer) 104 and decision circuit 108 is omitted here.

[0047] The error detection and correction device and the related method provided by the present invention can detect the first position of a suspicious error, and further, can perform forward error propagation path tracing to provide information required for subsequent error correction. Figure 2 FIG. 1 is a schematic diagram of a TBEE (Trellis-Based Error Eliminator) according to an embodiment of the present invention. TBEE (Trellis-Based Error Eliminator) 200 includes an error detector 202 and an error corrector 204 . Figure 1 The TBEE (Trellis-Based Error Eliminator) 106 shown may be composed of Figure 2TBEE (Trellis-Based Error Eliminator) 200 is shown, wherein the error detection circuit 126 may be implemented by an error detector 202, and the error correction circuit 128 may be implemented by an error corrector 204. Error detector 202 includes circuits or modules for supporting multiple functions, including a head error detection function 206 and an activation control function 208. Error corrector 204 includes circuits for supporting multiple functions, including a path metrics calculation and selection function 210 and an error correction function 212. Head error detection function 206 is configured to detect the first position of a suspected error (i.e., the symbol position of the first error). In this embodiment, the first error detection function 206 is configured with an error threshold ε and searches for candidate first errors (e.g., a single random error affecting only a single symbol or the first random error at the beginning of a cluster of errors / error propagation affecting consecutive symbols) based on the error threshold ε. In this embodiment, the first error detection function 206 may perform first error detection based on the difference between the equalized signal S_DFE and the symbol decision signal S_D. If the error signal S_E is available to the error detector 202, the first error detection function 206 may perform first error detection on the symbol positions of consecutive symbols in a forward direction with reference to the error signal S_E. In other words, the first error detection function 206 may perform forward error detection on the symbol positions based on the difference between the equalized signal S_DFE and the symbol decision signal S_D. For example, the equalized signal S_DFE carries one sample (soft data) s for each symbol position i. i , and the decision circuit 108 determines the sample s i A hard decision is performed to generate / produce a symbol (hard data) d for the same symbol position i i The first error detection function 206 performs first error detection on the current symbol position i by checking multiple conditions. The first condition is checked to determine whether the previous sample s i-1 and the previous symbol d i-1 The absolute difference between |s i-1 -d i-1|is not greater than a predetermined threshold (i.e., |previous slicer error|≤ε). The second condition is checked to determine whether the current sample s i and the current symbol d i The absolute difference between |s i -d i |is greater than a predetermined threshold (i.e., |current slicer error|>ε). The third condition is checked to determine whether the current sample s i Is the absolute value of |soft data| less than the maximum PAM level (i.e., |soft data|<maximum PAM level)? It can be understood that if these three conditions are met at the same time, that is, |previous slicer error|≤ε and |current slicer error|>ε and |soft data|<maximum PAM level, then it means that the first error is detected at the current symbol position i (i.e., the first position of the suspected error); on the contrary, if at least one of these three conditions is not met, then it is considered that the symbol d at the current position i is a suspected error. i There are no errors. To better understand the technical features of the proposed error detection and correction technology, PAM4 and 1-tap DFE are used as an example. In fact, the proposed error detection and correction technology can be applied to PAM-x (x ≥ 2) receivers with n-tap DFE (n > 1).

[0048] Figure 3 is a diagram illustrating the distribution of samples transmitted via an additive white Gaussian noise (AWGN) channel. Assume that the error threshold ε is set to 0.8. When the absolute difference |s i-1 -d i-1 | is not greater than 0.8 and the absolute difference |s i -d i When | is greater than 0.8, the decision circuit 108 makes a decision on the current symbol d i The codeword decision of may have a first error. That is, at the current codeword position i, the codeword value of the correct codeword sent from the transmitter is adjacent to the codeword value of the current codeword di that is wrongly determined by the hard decision due to the first error offset of the soft data. When |e[0]|=|d i-1 -s i-1 |≤0.8, if Figure 3 If there is soft data in the middle shaded area, the first error can be calculated based on |e[1]|=|d i -s i|>0.8 is found. It should be noted that if the soft data is greater than +3, the correct symbol {+3} can still be determined, and if the soft data is less than -3, the correct symbol {-3} can still be determined. Therefore, when the current sample si has soft data greater than +3 or less than -3, the current symbol di can be considered an error-free symbol. Therefore, checking the third condition (i.e., |soft data| <maximum PAM level)以避免首错误的误检测。

[0049] When the first error detection function 206 determines that the first condition, the second condition, and the third condition are all satisfied at the current symbol position i, the first error detection function 206 determines that a head error occurs / appears / is generated at the current symbol position i, which means that the current symbol di at the current symbol position i may need error correction. The first error detection function 206 provides a head index to the error corrector 204 (specifically, the path metric calculation and selection function 210 of the error corrector 204) to indicate the head position of the suspected error. In addition, the first error detection function 206 also provides the sign (sign) s of the first error to the error corrector 204 (i.e., s=sign(e[1])=sign(d i -s i For example, the symbol s of the first error may be used for path metric calculation. In another example, the symbol s of the first error may be used to determine an error pattern caused by the 1-tap DFE and starting from the detected first error.

[0050] Activation control function 208 is configured to control the activation of error corrector 204 during a period in which first-error detection function 206 is operating to perform first-error detection on the symbol positions of consecutive symbols in the forward direction. For example, error corrector 204 is activated in response to first-error detection function 206 detecting a first error. In other words, error corrector 204 is activated only when first-error detection function 206 detects a first error. Since the error correction process does not need to be initiated when a first error is not detected, activation control function 208 can deactivate error corrector 204 to reduce power consumption. Furthermore, activation control function 208 can deactivate error corrector 204 at the end of an error correction process activated due to first-error detection. This allows TBEE (Trellis-Based Error Eliminator) 200 to consume very low power, meeting the requirements of low-power receivers. However, this is for illustrative purposes only and is not intended to limit the present invention. In some embodiments of the present invention, error detector 202 can be modified to omit activation control function 208. Such alternative designs also fall within the scope of the present invention.

[0051] After the first error is detected by the first error detection function 206, the path metric computation and selection function 210 of the error corrector 204 is operated to perform forward error propagation path tracking to select an error propagation path with a propagation length and provide information of the propagation length to the correction function 212. For example, the forward error propagation path tracking can be performed based on a two-state trellis.

[0052] Figure 4 is a schematic diagram of a two-state trellis for error propagation path selection according to an embodiment of the present application. Figure 4 The top of shows a two-state trellis 400 starting from a data state S0 of an error-free symbol (where |e[0]|≤ε). A path without any state transition is considered as an original path corresponding to the symbol sequence output by the decision circuit 108. A path with one state transition (first state transition) from state S0 to state S1 and another state transition (second state transition) from state S1 to state S0 can be considered as a candidate path for error propagation path selection. For example, candidate path j is a path corresponding to a sequence starting from the data state S1 of the detected first error, propagating (j-1) data states and each state is the same data state S1, and ending at the jth data state which is the data state S0.

[0053] Figure 5 is a schematic diagram of an original path and a plurality of candidate paths according to an embodiment of the present application. Figure 5 Sub-diagram (A) of shows the original path with branch metrics Ho, Po1, Po2, Po3, To4. Figure 5 Sub-diagram (B) of shows candidate path 1 (j=1) with branch metrics Hc and Tc1. Figure 5 Sub-diagram (C) of shows candidate path 4 (j=4) with branch metrics Hc, Pc1, Pc2, Pc3 and Tc4.

[0054] Figure 6 is a schematic diagram of the concept of computing branch metrics of head branches according to an embodiment of the present application. The branch metrics H o and H c of the original path and the candidate path can be computed using the following equations.

[0055] H o = e 2 [1] (1)

[0056]

[0057] branch metric H c and H o The difference between the branch metrics H

[0058]

[0059] Figure 7 is a schematic diagram illustrating the concept of calculating the branch metric of the kth propagation branch according to an embodiment of the present application. The branch metric P o [k] of the original path and the branch metric P c [k] of the candidate path can be calculated using the following equation.

[0060] P o [k] = e 2 [k] (4)

[0061]

[0062] The term 2h1 represents the error caused by 1-tap DFE error propagation. The difference between the branch metrics P c [k] and P o [k] can be represented by a new branch metric P[k] calculated using the following equation.

[0063]

[0064] Figure 8 is a schematic diagram illustrating the concept of calculating the branch metric of the kth tail branch according to an embodiment of the present application. As described above, if the soft data is greater than +3, it can still be determined as a correct symbol {+3}, and if the soft data is less than -3, it can still be determined as a correct symbol {-3}. Therefore, when the absolute value of the soft data is greater than the maximum PAM level, error propagation is terminated. The branch metric T o [k] of the original path and the branch metric T c [k] of the candidate path can be calculated using the following equation.

[0065] T o [k] = P o [k+1] = e 2 [k+1] (7)

[0066]

[0067] The term 2h1 represents the error caused by 1-tap DFE error propagation. c [k] and T o The difference between [k] can be expressed by the new branch metric T[k] calculated using the following formula.

[0068]

[0069] Whether a specific candidate path with the same number of branches is a target path that can be selected as the error propagation path can be determined by comparing it with the corresponding original path. Regarding the path metric calculation of each candidate path, the branch metrics H, P, and T calculated by the above formulas (3), (6), and (9) can be used to obtain equivalent path metrics to simplify the forward error propagation path tracking, such as Figure 4 In other words, the path metric PM[j] of the candidate path j = {1, 2, ..., k} can be expressed by the following formula.

[0070]

[0071] Since forward error propagation path tracing is employed, the path metric calculation and selection function 210 can sequentially calculate the path metrics PM[j] for candidate paths j = {1, 2, ..., k}. When the first PM < 0 is found, the error propagation path ends. In some embodiments, the path metric calculation and selection function 210 checks whether the current path metric PM[i] is a negative value before calculating and checking the next path metric PM[i+1]. If the current path metric PM[i] is found to be less than zero, the candidate path with this path metric PM[i] is selected and the propagation length P (P = i-1) is determined. It should be noted that when the first case of PM < 0 found by the path metric calculation and selection function 210 is the path metric PM[1], the propagation length P has a zero value (i.e., P = 0) because the suspected error is a single error and will not be propagated to subsequent codeword decisions through the feedback feature of the DFE.

[0072] As mentioned above, the first error detection function 206 provides the first error symbol s to the error corrector 204 (i.e., s = sign(e[1])). After the propagation length P is determined by the path metric calculation and selection function 210, the error correction function 212 can refer to the parameters including sign(e[1]) and P to identify the error pattern caused by the 1-tap DFE and starting from the position of the detected first error, and then can correct the symbol decision signal S_D according to the identified error pattern. For example, the error pattern caused by the 1-tap DFE alternates between {-1, +1}. Considering the case of sign(e[1]) = -1 and P = 3, the error pattern caused by the 1-tap DFE can be -1, +1, -1, +1. Considering another case of sign(e[1]) = +1 and P = 3, the error pattern caused by the 1-tap DFE can be +1, -1, +1, -1.

[0073] Assume that the PAM4 symbol values -3, -1, 1, 3 are represented by 0, 1, 2, 3, respectively. In the case of not using 1+D pre-coding, the correction of the symbol sequence {Sk} (S0 is the first error symbol of the DFE error propagation, i.e., the symbol affected by the first error) can be represented by the following formula.

[0074] S k = S k -sign(e[1]) x (-1) k for k = 0:1:P (14)

[0075] In another case of using 1+D pre-coding, two symbols S0 (which is the first error symbol at the beginning of the error propagation) and S P+1 (which is the symbol after the last error symbol at the end of the error propagation) can be modified using the following formula.

[0076] S0 = mod(S0 - sign(e[1]), 4) (15)

[0077] S P+1 = mod(S P+1 + (-1) P x sign(e[1]), 4) (16)

[0078] Figure 9 is a flowchart of an error detection and correction method according to an embodiment of the present application. The TBEE (Trellis-based Error Eliminator) 106 / 200 can employ the error detection and correction method. Assuming that the results are substantially the same, it is necessary to follow Figure 9The exact order of performing these steps is shown. At step 902, the error detection circuit 126 / error detector 202 performs forward error detection to detect a first location of a suspected error, which can be a single error or a burst error. At step 904, the error detection circuit 126 / error detector 202 determines whether a first error (the first location of the suspected error) is successfully found. If yes, the flow proceeds to step 906. Otherwise, the flow returns to step 902 to continue performing forward error detection. At step 906, the error correction circuit 128 / error corrector 204 calculates path metrics for determining a propagation length, which is a zero value if the suspected error is a single error or a non-zero value if the suspected error is a burst error. At step 908, the error correction circuit 128 / error corrector 204 determines whether error propagation is finished. If yes, the flow proceeds to step 910. Otherwise, the flow returns to step 906 to continue path metric calculation. At step 910, the error correction circuit 128 / error corrector 204 performs error correction on the hard decision output (i.e., the symbol decision signals, particularly, the erroneous symbols in the symbol decision signals) according to the sign of the first error and the propagation length. Those of ordinary skill in the art, after reading the above paragraphs on the principles of the TBEE (trellis-based error corrector) 106 / 200, can easily understand Figure 9 Details of the steps shown are therefore omitted for brevity.

[0079] The use of ordinal terms such as "first", "second", "third", etc., in the claims to modify a claim element does not by itself connote any priority, precedence, or order of one claim element over another, or to the temporal order of performance of method actions, but are used merely as labels to identify elements having the same name (to avoid confusion with other elements having the same name).

[0080] While the application has been described by way of example and in terms of the preferred embodiment, it is to be understood that the application is not limited to the disclosed embodiment. To the contrary, it is intended to cover various modifications and equivalent structures (and functions) falling within the scope of the claims. Other embodiments are set forth in the following claims.

Claims

1. An error detection and correction device, comprising: a decision feedback equalizer (DFE) configured to equalize the data signal to generate a first equalized signal; a decision circuit configured to perform a hard decision on the first equalized signal to generate a symbol decision signal; an error detection circuit configured to perform forward error detection on symbol positions of consecutive symbols included in the symbol decision signal to detect a leading position of a suspected error affecting at least one symbol in the symbol decision signal; and The error correction circuit is configured to perform error correction on the symbol decision signal in response to the first position of the suspected error detected by the error detection circuit.

2. The error detection and correction device according to claim 1, wherein: The error detection and correction device also includes: The feedforward equalizer FFE is configured to process the received signal to generate a second equalized signal as the data signal.

3. The error detection and correction device according to claim 1, wherein: The suspected error detected by the error detection circuit is a single error, and the single error affects only a single symbol in the symbol decision signal.

4. The error detection and correction device according to claim 1, wherein: The suspected error detected by the error detection circuit is a concentrated error, and the concentrated error affects a plurality of symbols in the symbol decision signal.

5. The error detection and correction device according to claim 1, wherein: The data signal is derived from a pulse amplitude modulation (PAM) signal.

6. The error detection and correction device according to claim 5, wherein: The consecutive symbols include a previous symbol located at a previous symbol position and a current symbol located at a current symbol position; the first equalized signal includes a previous sample and a current sample, wherein the previous symbol is a hard decision result of the previous sample, and the current symbol is a hard decision result of the current sample; and the error detection circuit performs forward error detection by checking the following conditions: whether the absolute difference between the previous sample and the previous symbol is not greater than a predetermined threshold; Whether the absolute difference between the current sample and the current symbol is greater than the predetermined threshold; and Whether the absolute value of the current sample is less than the maximum PAM level.

7. The error detection and correction device according to claim 1, wherein: The error correction circuit is configured to perform forward error propagation path tracing starting from the first position detected by the error detection circuit to select an error propagation path having a propagation length; wherein the error correction performed on the codeword decision signal is performed at least according to the propagation length.

8. The error detection and correction device according to claim 7, wherein: The forward error propagation path tracing is performed based on a two-state grid.

9. The error detection and correction device according to claim 1, wherein: The error detection circuit is further configured to control activation of the error correction circuit during the forward error detection.

10. The error detection and correction device according to claim 9, wherein: The error correction circuit is activated in response to the first position of the suspected error detected by the error detection circuit.

11. A method for error detection and correction, comprising: performing decision feedback equalization on the data signal to generate a first equalized signal; performing hard decision on the first equalized signal to generate a symbol decision signal; performing forward error detection at symbol positions of consecutive symbols included in the symbol decision signal to detect a leading position of a suspected error affecting at least one symbol in the symbol decision signal; and In response to the first position of the suspected error, error correction is performed on the symbol decision signal.

12. The error detection and correction method according to claim 11, wherein: The error detection and correction method further includes: Feedforward equalization is performed on the received signal to generate a second equalized signal as the data signal.

13. The error detection and correction method according to claim 11, wherein: The suspected error is a single error that affects only a single symbol in the symbol decision signal.

14. The error detection and correction method according to claim 11, wherein: The suspected errors are concentrated errors that affect multiple symbols in the symbol decision signal.

15. The error detection and correction method according to claim 11, wherein: The data signal is derived from a pulse amplitude modulation (PAM) signal.

16. The error detection and correction method according to claim 15, wherein: The consecutive symbols include a previous symbol located at a previous symbol position and a current symbol located at a current symbol position; the first equalized signal includes a previous sample and a current sample, wherein the previous symbol is a hard decision result of the previous sample, and the current symbol is a hard decision result of the current sample; and performing the forward error detection includes checking the following conditions: whether the absolute difference between the previous sample and the previous symbol is not greater than a predetermined threshold; Whether the absolute difference between the current sample and the current symbol is greater than the predetermined threshold; and Whether the absolute value of the current sample is less than the maximum PAM level.

17. The error detection and correction method according to claim 11, wherein: Performing this correction includes: performing forward error propagation path tracing starting from the first position to select an error propagation path having a propagation length; The error correction is performed at least according to the propagation length.

18. The error detection and correction method according to claim 17, wherein: The forward error propagation path tracing is performed based on a two-state grid.

19. The error detection and correction method according to claim 11, wherein: Performing this forward error detection also includes: The activation of the error correction is controlled during the forward error detection.

20. The error detection and correction method according to claim 19, wherein: The error correction is activated in response to the error detection circuit detecting the first position of the suspected error.

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