Quantum chip layout graphical pitch marking method, storage medium and electronic device

Abstract

The application discloses a kind of quantum chip layout graphic spacing mark method, storage medium and electronic equipment.The method comprises the following steps: obtaining at least part of two edge lines in the preset distance range in all graphics of quantum chip layout;With the first edge line as the bottom, a first projection area is constructed on the preset side relative to the graphic to which it belongs according to the preset distance, and a second projection area is constructed on the preset side relative to the graphic to which it belongs according to the preset distance with the second edge line as the bottom, and the preset side of the two edge lines is opposite to each other;Determine the coincident intersection point of the first edge line in the second projection area, and determine the coincident intersection point of the second edge line in the first projection area;Generate an enclosing region enclosing the coincident intersection point of the two edge lines, and perform error marking.The application can automatically complete spacing error marking, improve the marking efficiency.

Description

Technical Field

[0001] This invention relates to the field of chip layout design, and in particular to a method for marking the graphic spacing of a quantum chip layout, a storage medium, and an electronic device. Background Technology

[0002] Quantum chips are chips composed of many superconducting layers and dielectric layers stacked according to certain design rules. For example, the Josephson junction, a key component of quantum chips, consists of two superconducting layers with a dielectric layer sandwiched in between. Therefore, the layout of a quantum chip requires drawing many diagrams representing the devices. After the quantum chip layout design is completed, DRC (Design Rules Checking) is required, and spacing checking is a key task of DRC.

[0003] In existing quantum chip design rule checks, designers need to annotate graphics whose spacing does not conform to design rules. However, quantum chip layouts typically contain a large number of densely packed graphics, making manual annotation time-consuming, labor-intensive, and inefficient, thus failing to meet design requirements. Summary of the Invention

[0004] The purpose of this invention is to provide a method, storage medium, and electronic device for marking the spacing of quantum chip layouts, in order to solve the problem that manual marking errors in the prior art cannot meet design requirements, and to automatically complete the marking of spacing errors, thereby improving marking efficiency.

[0005] To address the aforementioned technical problems, this invention provides a method for marking the graphic spacing of a quantum chip layout, comprising:

[0006] Obtain at least two edges of the quantum chip layout that are partially within a preset distance range from all the graphics.

[0007] A first projection area is constructed with the first edge line as the base on a preset side relative to its corresponding graphic at a preset distance, and a second projection area is constructed with the second edge line as the base on a preset side relative to its corresponding graphic at a preset distance, wherein the preset sides of the two edge lines are opposite to each other.

[0008] Determine the point of intersection of the first edge line within the second projection area, and determine the point of intersection of the second edge line within the first projection area;

[0009] Generate a bounding region that surrounds the intersection of the two edges and mark any errors.

[0010] Preferably, the predetermined side of the first edge line is the side of the first edge line that is far away from the graphic to which it belongs, and the predetermined side of the second edge line is the side of the second edge line that is far away from the graphic to which it belongs.

[0011] Preferably, the predetermined side of the first edge line is the side of the first edge line facing the graphic to which it belongs, and the predetermined side of the second edge line is the side of the second edge line facing the graphic to which it belongs.

[0012] Preferably, the predetermined side of the first edge line is the side of the first edge line that is away from its corresponding graphic, and the predetermined side of the second edge line is the side of the second edge line that faces its corresponding graphic.

[0013] Preferably, the step of constructing the first projection area on a predetermined side relative to its corresponding graphic at the predetermined distance, using the first edge line as the base, specifically involves:

[0014] A first mirror line is constructed with a preset distance between the first edge line and the preset side of its corresponding graphic, and the first mirror line and the first edge line are connected to obtain a first projection area.

[0015] The specific steps of constructing the second projection area on a predetermined side relative to its corresponding graphic at the predetermined distance, using the second edge as the base, are as follows:

[0016] A second mirror line is constructed on the side of the second edge relative to the preset side of its corresponding graphic, with a distance of the preset distance between them. The second mirror line and the second edge line are then connected to obtain the second projection area.

[0017] Preferably, the intersection point of the first edge line is the two endpoints of the line segment of the first edge line located within the second projection area, and the intersection point of the second edge line is the two endpoints of the line segment of the second edge line located within the first projection area.

[0018] Preferably, the enclosing region is the convex hull of the intersection point of the two side lines.

[0019] Preferably, the angle formed by the two side lines is outside the preset angle range, or the two side lines do not intersect, or the two side lines belong to different shapes.

[0020] To address the aforementioned technical problems, the present invention also provides a storage medium storing a computer program configured to execute the graphic spacing annotation method for quantum chip layout as described in any of the preceding claims when running.

[0021] To address the aforementioned technical problems, the present invention also provides an electronic device, including a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to execute the graphic spacing annotation method for quantum chip layout as described in any of the preceding claims.

[0022] Unlike existing technologies, the graphic spacing annotation method for quantum chip layout provided by this invention obtains two edge lines in all graphics of the quantum chip layout that do not meet the spacing rules, constructs projection areas on a preset side of each edge line relative to its respective graphic, determines the intersection point of the two edge lines in the two projection areas, and finally generates an enclosing area surrounding the intersection point of the two edge lines and performs error annotation, thereby automatically completing the spacing error annotation and improving annotation efficiency.

[0023] The storage medium and electronic device provided by this invention belong to the same inventive concept as the graphic spacing annotation method of quantum chip layout, and therefore have the same beneficial effects, which will not be repeated here. Attached Figure Description

[0024] Figure 1 This is a flowchart illustrating the method for marking the graphic spacing of a quantum chip layout according to an embodiment of the present invention.

[0025] Figure 2 This is a schematic diagram of two graphics representing the quantum chip layout in an embodiment of the present invention.

[0026] Figure 3 This is a schematic diagram of the projection areas constructed with the two side lines as the bases.

[0027] Figure 4 This is a schematic diagram of the enclosed region generated within the projection areas of the two side lines.

[0028] Figure 5 This is a schematic diagram illustrating an incorrect labeling of the enclosed area within the projected region. Detailed Implementation

[0029] The specific embodiments of the present invention will now be described in more detail with reference to the accompanying drawings. The advantages and features of the present invention will become clearer from the following description and claims. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0030] In the description of this invention, it should be understood that the terms "center", "upper", "lower", "left", "right", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0031] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0032] Please refer to Figure 1 This invention provides a method for marking the spacing of graphics in a quantum chip layout. The method includes the following steps:

[0033] S1: Obtain at least two edges of the quantum chip layout that are partially within a preset distance range from all the graphics.

[0034] The quantum chip layout is a two-dimensional planar polygon, with each polygon containing at least three edges. If two edges are at least partially within a preset distance range, it indicates that the spacing between the shapes to which these two edges belong does not meet the DRC (Discretionary Restriction Control) requirements. The preset distance range can be a circle with a preset radius. If two edges are partially within this range, it means that these two edges are at least partially within the preset distance range. For example, if the shortest distance from one endpoint of one edge to another edge is less than the preset distance, then this edge is at least partially within the preset distance range of the other edge. The positional relationship between the two edges can be arbitrary, such as parallel or non-parallel. Figure 2 As shown, the distance between the endpoint of the edge line A1 of figure A and the edge line B1 of figure B is at least partially within a preset distance L (the circle shown by the dashed line in the figure).

[0035] S2: Construct a first projection area with the first edge as the base on a preset side relative to its corresponding graphic at a preset distance, and construct a second projection area with the second edge as the base on a preset side relative to its corresponding graphic at a preset distance, wherein the preset sides of the two edges are opposite to each other.

[0036] The first edge line relative to the preset side of its corresponding graphic includes two scenarios: one is that the first edge line faces the side of its corresponding graphic, i.e., the inside of the graphic; the other is that the first edge line is away from the side of its corresponding graphic, i.e., the outside of the graphic. Two edges being "relative to each other" means that there is an overlap between the preset side of the first edge line relative to its corresponding graphic and the preset side of the second edge line relative to its corresponding graphic.

[0037] In this embodiment, the predetermined side of the first edge line is the side of the first edge line away from its corresponding graphic, and the predetermined side of the second edge line is the side of the second edge line away from its corresponding graphic; alternatively, the predetermined side of the first edge line is the side of the first edge line facing its corresponding graphic, and the predetermined side of the second edge line is the side of the second edge line facing its corresponding graphic; or the predetermined side of the first edge line is the side of the first edge line away from its corresponding graphic, and the predetermined side of the second edge line is the side of the second edge line facing its corresponding graphic. Figure 2 As shown, the default side of the edge A1 of figure A is the side away from figure A, and the default side of the edge B1 of figure B is the side away from figure B. The two are opposite to each other.

[0038] The projection area is defined as follows: if two perpendicular lines are drawn from the two endpoints of a line segment in the same direction on a plane, the line connecting the two feet of the perpendiculars is the projection line of the line segment on that plane, and the area between the projection line and the line segment is the projection area.

[0039] like Figure 3 As shown, the first projection area constructed with the first edge line A1 as the base is A11. The first projection area includes a straight line parallel to the first edge line A1 and a perpendicular line connecting the straight line and the first edge line A1. The perpendicular distance from any point on the straight line to the first edge line A1 is a preset distance L, and the length of the perpendicular line is also a preset distance L.

[0040] Similarly, the second projection region constructed with the second edge line B1 as the base is B11. The second projection region includes a straight line parallel to the second edge line B1 and a perpendicular line connecting the straight line and the second edge line B1. The perpendicular distance from any point on the straight line to the second edge line B1 is a preset distance L, and the length of the perpendicular line is also a preset distance L.

[0041] S3: Determine the intersection point of the first edge line within the second projection area, and determine the intersection point of the second edge line within the first projection area.

[0042] Among them, such as Figure 3 As shown, the point where the first edge line A1 coincides with the second projection area B11 is the path point included by the line segment A0 of the first edge line A1 within the second projection area B11. The point where the second edge line B1 coincides with the first projection area A11 is the path point included by the line segment A0 of the second edge line B1 within the first projection area A11.

[0043] S4: Generate the region surrounding the intersection of the two edges and mark any errors.

[0044] Among them, such as Figure 4As shown, the region enclosing the intersection of the two edges is AB, meaning that the region AB is bounded by line segments A0 and B0. In this embodiment, the intersection of the first edge is the endpoints of the line segment of the first edge located within the second projection region, and the intersection of the second edge is the endpoints of the line segment of the second edge located within the first projection region. The enclosing region is the convex hull of the intersection of the two edges, which is the smallest polygon enclosing the intersection of the two edges. The convex hull can be calculated and generated using a convex hull algorithm.

[0045] Enclosed areas can be marked as errors using shading and / or highlighting. For example... Figure 5 As shown, the enclosing region AB is displayed with a grid filling.

[0046] In some embodiments of this application, the step of constructing a first projection area on a predetermined side of the graphic relative to the first edge line at a predetermined distance, with the first edge line as the base, specifically involves: constructing a first mirror line with a predetermined distance between the first edge line and the predetermined side of the graphic relative to the first edge line; and connecting the first mirror line and the first edge line to obtain the first projection area. The first mirror line is a straight line parallel to the first edge line A1, and the first mirror line and the first edge line A1 are connected by two perpendicular lines.

[0047] Similarly, the specific steps of constructing a second projection area on a preset side relative to its corresponding graphic, with the second edge as the base and at a preset distance, are as follows: construct a second mirror line with a preset distance between the second edge and its corresponding graphic, and connect the second mirror line and the second edge to obtain the second projection area.

[0048] like Figure 3 As shown, the first mirror line is a straight line parallel to the first edge line A1. The points connecting the two endpoints of the first edge line A1 and the two endpoints of the first mirror line are the feet of the perpendiculars. The area enclosed by the first edge line A1, the first mirror line, and the two feet of the perpendiculars is the first projection area. Similarly, the second mirror line is a straight line parallel to the second edge line B1. The points connecting the two endpoints of the second edge line B1 and the two endpoints of the second mirror line are the feet of the perpendiculars. The area enclosed by the second edge line B1, the second mirror line, and the two feet of the perpendiculars is the second projection area.

[0049] In a preferred embodiment, the angle formed by the two edge lines is outside a preset angle range. In some DRC requirements, if the included angle formed by two edge lines that are at least partially within a preset distance range is within the preset angle range, DRC is not required. For example, if the preset angle range is 35 degrees to 45 degrees, two edge lines that are at least partially within the preset distance range but form an included angle of 40 degrees will not be incorrectly labeled.

[0050] In a preferred embodiment, the two edge lines do not intersect. If two edge lines intersect, there is an intersection point; by determining whether two edge lines intersect, it can be determined whether the two edge lines intersect. For two edge lines that intersect but are at least partially within a preset distance range, no incorrect labeling is applied.

[0051] In a preferred embodiment, the two edge lines belong to different graphics. Since edge lines on the same graphic are prone to DRC misjudgment, two edge lines that are at least partially within a preset distance range but belong to the same graphic are not incorrectly labeled, which can minimize misjudgment.

[0052] In the above manner, the graphic spacing annotation method for quantum chip layout provided by the present invention obtains two edge lines in all graphics of the quantum chip layout that do not meet the spacing rules, constructs projection areas on a preset side relative to their respective graphics with the two edge lines as the base, determines the coincident intersection points of the two edge lines in the two projection areas, and finally generates an enclosing area surrounding the coincident intersection points of the two edge lines and performs error annotation, thereby automatically completing the spacing error annotation and improving annotation efficiency.

[0053] The present invention also provides a storage medium storing a computer program configured to execute, when running, the graphic spacing annotation method for the quantum chip layout of any of the foregoing embodiments.

[0054] Specifically, in this embodiment, the storage medium may include, but is not limited to, USB flash drives, read-only memory (ROM), random access memory (RAM), portable hard drives, magnetic disks, or optical disks, and other media capable of storing computer programs.

[0055] The present invention also provides an electronic device, including a memory and a processor, wherein the memory stores a computer program and the processor is configured to run the computer program to perform a graphic spacing annotation method for a quantum chip layout according to any embodiment.

[0056] Specifically, the memory and processor can be connected via a data bus. Furthermore, the aforementioned electronic device may also include a transmission device and an input / output device, wherein the transmission device is connected to the processor, and the input / output device is connected to the processor.

[0057] In the description of this specification, references to terms such as "one embodiment," "some embodiments," "example," or "specific example," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments. In addition, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0058] The above are merely preferred embodiments of the present invention and do not constitute any limitation on the present invention. Any equivalent substitutions or modifications made by those skilled in the art to the technical solutions and content disclosed in the present invention without departing from the scope of the present invention shall be deemed to have remained within the protection scope of the present invention.

Claims

1. A method for marking the spacing of graphics in a quantum chip layout, characterized in that, include: Obtain at least two edges of the quantum chip layout that are partially within a preset distance range from all the graphics. A first projection area is constructed with the first edge line as the base on a preset side relative to its corresponding graphic at a preset distance, and a second projection area is constructed with the second edge line as the base on a preset side relative to its corresponding graphic at a preset distance, wherein there is an overlapping area between the preset sides of the two edge lines. Determine the point of intersection of the first edge line within the second projection area, and determine the point of intersection of the second edge line within the first projection area; Generate a bounding region that surrounds the coincident intersection of the two edges, and mark any errors. The first projection area includes a straight line parallel to the first edge line and a perpendicular line connecting the straight line and the first edge line, and the perpendicular distance from any point on the straight line to the first edge line is a preset distance; the second projection area includes a straight line parallel to the second edge line and a perpendicular line connecting the straight line and the second edge line, and the perpendicular distance from any point on the straight line to the second edge line is a preset distance. The point of intersection of the first edge line within the second projection area is the path point included by the line segment of the first edge line within the second projection area, and the point of intersection of the second edge line within the first projection area is the path point included by the line segment of the second edge line within the first projection area. The enclosed region is the smallest polygon that encloses the intersection of the two side lines.

2. The method according to claim 1, characterized in that, The preset side of the first edge line is the side of the first edge line that is far away from the graphic to which it belongs, and the preset side of the second edge line is the side of the second edge line that is far away from the graphic to which it belongs.

3. The method according to claim 1, characterized in that, The preset side of the first edge line is the side of the first edge line facing the graphic to which it belongs, and the preset side of the second edge line is the side of the second edge line facing the graphic to which it belongs.

4. The method according to claim 1, characterized in that, The predetermined side of the first edge line is the side of the first edge line that is away from its corresponding graphic, and the predetermined side of the second edge line is the side of the second edge line that faces its corresponding graphic.

5. The method according to any one of claims 1 to 4, characterized in that, The step of constructing the first projection area on a predetermined side relative to its corresponding graphic at the predetermined distance, with the first edge as the base, specifically involves: A first mirror line is constructed with a preset distance between the first edge line and the preset side of its corresponding graphic, and the first mirror line and the first edge line are connected to obtain a first projection area. The specific steps of constructing the second projection area on a predetermined side relative to its corresponding graphic at the predetermined distance, using the second edge as the base, are as follows: A second mirror line is constructed on the side of the second edge relative to the preset side of its corresponding graphic, with a distance of the preset distance between them. The second mirror line and the second edge line are then connected to obtain the second projection area.

6. The method according to claim 1, characterized in that, The points where the first edge lines coincide are the two endpoints of the line segment of the first edge line located within the second projection area, and the points where the second edge lines coincide are the two endpoints of the line segment of the second edge line located within the first projection area.

7. The method according to claim 1, characterized in that, The angle formed by the two side lines is outside the preset angle range, or the two side lines do not intersect, or the two side lines belong to different shapes.

8. A storage medium, characterized in that, The storage medium stores a computer program, which is configured to execute the graphic spacing annotation method for the quantum chip layout according to any one of claims 1 to 7 when it runs.

9. An electronic device, characterized in that, It includes a memory and a processor, wherein the memory stores a computer program and the processor is configured to run the computer program to perform the graphic spacing annotation method for the quantum chip layout according to any one of claims 1 to 7.

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