An FPGA-based target detection neural network accelerator and a target detection system

Abstract

The application discloses an FPGA-based target detection neural network accelerator and a target detection system, the accelerator is arranged on an FPGA and comprises a control module, an input buffer module, a parameter buffer module, a systolic array module, a post-processing module and a pooling module; the control module comprises an instruction memory and a controller; the instruction memory is used for storing an instruction set of a neural network; the controller is used for generating control instructions according to the instruction set and controlling the operation of each module; the input buffer module is used for storing input feature data blocks of the target detection neural network; the parameter buffer module is used for storing bias data and weight data of the target detection neural network; the systolic array module is used for performing convolution operation; the post-processing module is used for processing the convolution calculation result; the pooling module is used for performing maximum pooling operation on data; and the output buffer module is used for reading and writing cache of data. The application improves the inference efficiency of the accelerator by configuring parameters of the target detection neural network, and realizes the high-performance and high-flexibility target detection neural network accelerator.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of artificial intelligence, and in particular to a target detection neural network accelerator based on FPGA and a target detection system. BACKGROUND

[0002] Target detection technology plays an important role in various fields of social life. In the field of intelligent monitoring, efficient target detection can monitor and identify personnel, vehicles and other targets in real time, providing a safer and more intelligent monitoring system. In the field of autonomous driving, fast and accurate target detection is the key to realizing reliable traffic environment perception. In the field of industrial automation and robotics, target detection can be used for object recognition, logistics management and other applications to improve production efficiency and quality. However, the complexity, large amount of calculation and high real-time requirements of target detection algorithms pose higher challenges to traditional computing platforms. In order to meet these needs and further promote the application of target detection technology, FPGA (Field-Programmable Gate Array) technology has received widespread attention. FPGA has the advantages of high performance, low power consumption and flexible configuration, making target detection applications faster, smarter and more efficient.

[0003] Neural network accelerator (NNA) is an edge computing device used to optimize artificial intelligence processing. It has high speed and low power consumption, and is an accelerator dedicated to inference processing in deep learning. Different application scenarios may have different requirements for target detection tasks, and different detection tasks require adjustments to the model structure of the target detection neural network, and the neural network accelerator also needs to be adjusted accordingly. Many neural network accelerators based on FPGA have been published in public literature, but the existing target detection neural network accelerators based on FPGA have the following shortcomings in technology:

[0004] (1) For actual application scenarios, new targets may appear in the scene over time, which may not be covered by the original model. However, target detection models need to adjust the model structure for different detection tasks, and generally, the last layer of each detection head of the model needs to be changed according to the number of target detection categories, which affects the scheduling of data during the operation of the accelerator. The existing neural network accelerator is designed for target detection tasks and does not have good adaptability and scalability. A general neural network accelerator needs to consider universality, which reduces the performance in design.

[0005] (2) In order to improve the running speed of the convolutional neural network accelerator, the prior art starts from adopting a systolic array, reducing data bit width, improving the efficiency of the calculation unit, etc., but does not combine these technologies to the greatest extent, so as to maximize the inference efficiency of the accelerator.

[0006] Therefore, there is an urgent need for a target detection neural network accelerator with good adaptability and expansibility, and high performance. SUMMARY

[0007] In order to solve the problems of poor expansibility, weak adaptability and insufficient performance of the existing neural network accelerator, the application provides a target detection neural network accelerator based on FPGA and a target detection system.

[0008] According to the first aspect of the application, a target detection neural network accelerator based on FPGA is provided, which is deployed on an FPGA and comprises:

[0009] A control module comprising an instruction memory and a controller, the instruction memory being configured to receive an instruction set of the target detection neural network, and the controller being configured to obtain instructions from the instruction set in the instruction memory, generate control instructions, and control the operation of an input cache module, a parameter cache module, a systolic array module, a post-processing module, a pooling module and an output cache module.

[0010] The input cache module is configured to store input feature data blocks of the current layer of the target detection neural network, and the size of the input feature data blocks depends on the input data amount of the current layer of the target detection neural network.

[0011] The parameter cache module is configured to store bias data and weight data of the target detection neural network.

[0012] The systolic array module is configured to perform convolution operation with the weight data and the feature data of the input feature data blocks as inputs.

[0013] The post-processing module is configured to process the results obtained by the convolution calculation to obtain quantized output data.

[0014] The pooling module is configured to perform maximum pooling operation on the quantized output data.

[0015] The output cache module is configured to read and write cache data.

[0016] Preferably, the instruction set comprises the hyperparameters of each layer of the target detection neural network, and the address for data reading and writing of the input buffer module, the parameter buffer module, the systolic array module, the post-processing module, the pooling module and the output buffer module; after receiving the start signal sent by the central processing unit, the controller controls the accelerator to work, accelerates the target detection neural network layer by layer, and in the acceleration process of each layer of the target detection neural network, the controller reads the corresponding control instructions of each layer from the instruction memory, and sends the control instructions to the input buffer module, the parameter buffer module, the systolic array module, the post-processing module, the pooling module and the output buffer module, and the input buffer module, the parameter buffer module, the systolic array module, the post-processing module, the pooling module and the output buffer module work after receiving the instructions; the accelerator does not need the central processing unit to participate in the work during running.

[0017] According to the above technical means, the instruction set prepared by software is used to configure the model parameters of the target detection neural network in different situations, so that the expansibility of the target detection neural network is improved.

[0018] Preferably, the input buffer module comprises a data preprocessing unit, a first data writing unit, an input feature storage unit and a first data reading unit; after reading the input feature data block, the data preprocessing unit performs boundary zero padding operation on the input feature data block according to the instruction sent by the controller, and then sends the processed feature data block to the first data writing unit; the first data writing unit writes the obtained input feature data block into the input feature storage module; the first data reading unit reads the input feature data block in the input feature storage unit, and constructs it into the data form required by the systolic array module to obtain the input feature data, and outputs the input feature data to the systolic array module; the first data reading unit and the first data writing unit obtain the read-write address instruction from the controller.

[0019] According to the above technical means, the data reading and writing modules obtain the relevant read-write address instructions from the controller, instead of generating the read-write address through complex operations, so that the efficiency of the accelerator can be improved.

[0020] Preferably, the parameter buffer module comprises a weight buffer unit and a bias buffer unit; the weight data and bias data of the target detection neural network are written into the external storage; the weight buffer unit reads and stores the weight data of the target detection neural network from the external storage based on the on-chip Block RAM of the FPGA, and adopts the ping-pong buffer operation to output the weight data to the weight data; the bias buffer unit loads all the bias data from the external storage at one time when the accelerator starts.

[0021] According to the above technical means, the data is output by using the ping-pong cache operation, so as to improve the efficiency of data output, and meanwhile, data loss caused by processing speed difference is avoided.

[0022] Preferably, the convolution calculation of the systolic array module adopts a weight reuse mode, the systolic array module comprises a plurality of processing units, each processing unit comprises a plurality of hardware multipliers, each hardware multiplier receives two unsigned input data and two signed weight data per clock pulse, and each clock cycle can complete four multiplication operations, and the 8-bit multiplication result is sent to a data accumulation module, a previous part is added, and accumulation operation is completed and stored in the internal cache of the processing unit.

[0023] According to the above technical means, the input feature data is read in a weight reuse cycle, the demand for cache is reduced, and the efficiency of the accelerator is improved.

[0024] Preferably, the processing of the post-processing module on the convolution result comprises bias adding, activation and quantization operations, wherein the bias adding operation on the convolution result is adding a bias value to the convolution result; the activation operation on the convolution result is truncating the convolution result to unsigned integer data by using a Relu activation function; and the quantization operation on the convolution result is right shifting the convolution result to quantize the convolution result, and the number of right shifts is input by the controller according to the instruction set, and the data of the same layer of the target detection neural network share one right shift value.

[0025] According to the above technical means, the weight parameters and the activation output are quantized to 4 bits, the data storage volume is significantly reduced, the number of times of accessing DDR memory of the accelerator is reduced, and the transmission delay of data between modules of the accelerator is reduced.

[0026] Preferably, after the pooling module receives the quantized output data, if the next layer of the current layer of the target detection neural network is a pooling layer, the quantized output data is subjected to a maximum pooling operation, and then the data after the maximum pooling operation is output to an output cache module; if the next layer of the current layer of the target detection neural network is not a pooling layer, the quantized output data is not operated, and the data is directly output to the output cache module by skipping the pooling module.

[0027] According to the above technical means, the features of the data are extracted by the maximum pooling operation, and the data volume is compressed by the pooling operation.

[0028] Preferably, the output buffer module comprises a second data write unit, a second data read unit and an output feature storage unit, the second data write unit obtains a write address from the controller, writes the output feature data output by the pooling layer into the output feature storage unit according to the write address; the output feature storage unit is realized based on the on-chip Block RAM of the FPGA, and works by using the ping-pong buffer operation; and the second data read unit outputs the data in the output feature storage unit in sequence.

[0029] According to the above technical means, the ping-pong buffer output data is used to avoid data loss and improve data transmission efficiency.

[0030] Preferably, the accelerator further comprises an up-sampling module for up-sampling the output feature data.

[0031] According to another aspect of the present application, a target detection system based on FPGA is provided, which is deployed on the FPGA and comprises:

[0032] An image acquisition module is configured to acquire image data and input the image data into the central processor;

[0033] The central processor is configured to process data, after receiving the image data, send an instruction start signal to the neural network accelerator, and after receiving an end signal sent by the neural network accelerator, output the processed image data;

[0034] The neural network accelerator is configured to receive the instruction start signal sent by the central processor, accelerate the target detection neural network, and send an end signal to the central processor after completing the acceleration;

[0035] An image output module is configured to superimpose characters on the processed image data, obtain a target detection result, and output the target detection result.

[0036] Compared with the prior art, the present application constructs a configurable target detection neural network accelerator based on FPGA, updates and configures the accelerator flexibly and quickly according to the requirements in the actual application scene by configuring the parameters of the target detection neural network, without changing the internal structure of the accelerator, improves the inference efficiency of the accelerator, and realizes a high-performance and high-flexibility target detection neural network accelerator. BRIEF DESCRIPTION OF DRAWINGS

[0037] Figure 1 Fig. 1 shows a structure schematic diagram of a target detection neural network accelerator based on FPGA according to an embodiment of the present application.

[0038] Figure 2 Fig. 2 shows a structure schematic diagram of a yolov4-tiny model according to an embodiment of the present application.

[0039] Figure 3 Fig. 1 shows a schematic diagram of the operation of the systolic array module according to an embodiment of the present application.

[0040] Figure 4 Fig. 2 shows a schematic diagram of the structure of a processing unit in the systolic array module according to an embodiment of the present application.

[0041] Figure 5 Fig. 3 shows a schematic diagram of the operation principle of a hardware multiplier in the systolic array module according to an embodiment of the present application.

[0042] Figure 6 Fig. 4 shows a schematic diagram of the operation principle of a max pooling operation in the pooling module according to an embodiment of the present application.

[0043] Figure 7 Fig. 5 shows a schematic diagram of the structure of an FPGA-based target detection neural network accelerator according to an embodiment of the present application.

[0044] Figure 8 Fig. 6 shows a schematic diagram of an FPGA-based target detection system according to an embodiment of the present application. DETAILED DESCRIPTION

[0045] The FPGA-based target detection neural network accelerator and target detection system according to the embodiments of the present application can effectively improve the target detection performance.

[0046] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the accompanying drawings. Obviously, the described embodiments are only some of the embodiments of the present application and are used only for illustrative purposes, and cannot be understood as limiting the present patent. Based on the embodiments of the present application, all other embodiments obtained by those of ordinary skill in the art without creative labor fall within the scope of the present application. The accompanying drawings are used only for illustrative purposes and cannot be understood as limiting the present patent; in order to better illustrate the embodiments, some parts of the drawings are omitted, enlarged or reduced, and the actual size is not represented; the description of the directions such as "up", "down", etc. is not limiting to the present patent; for those of ordinary skill in the art, some well-known content in the drawings can be omitted; the position relationship described in the drawings is used only for illustrative purposes and cannot be understood as limiting the present patent.

[0047] The technical solutions of the present application will be further described below with reference to the accompanying drawings and embodiments.

[0048] Example 1

[0049] The present embodiment provides a kind of as Figure 1The FPGA-based target detection neural network accelerator shown is aimed at a yolov4-tiny target detection network, and the yolov4-tiny model structure is as shown in Figure 2 As shown, the model input image can be 416x416, 512x512, 608x608, and the like two-dimensional size. For tasks with different numbers of detection categories, the model needs to change the output channel number of the 21st layer and the 25th layer convolution kernel, and the output channel calculation formula is as follows:

[0050] out channel =(5+classes)*3

[0051] Where classes refers to the number of detection categories, 5 refers to the five parameters of x, y, h, w, and confidence, and 3 refers to three anchor frames. In a specific embodiment, the number of detection categories is 80, so the output channel number of the 21st layer is 255. The yolov4-tiny accelerator proposed in the application uses a Relu activation function, 4-bit quantization is performed on the weight parameters and activation outputs using a quantization-aware training, and the Power of Two quantization method is used to realize quantization by right shifting.

[0052]

[0053] In this embodiment, the structure of the accelerator includes:

[0054] A control module including an instruction memory and a controller, the instruction memory being configured to receive an instruction set of a target detection neural network, and the controller being configured to obtain instructions from the instruction set in the instruction memory, generate control instructions, and control the input buffer module, the parameter buffer module, the systolic array module, the post-processing module, the pooling module, and the output buffer module to run;

[0055] An input buffer module configured to store an input feature data block of a current layer of the target detection neural network, the size of the input feature data block depending on the input data amount of the current layer of the target detection neural network, and the input buffer module being configured to obtain instructions from the controller for configuration;

[0056] A parameter buffer module configured to store bias data and weight data of the target detection neural network;

[0057] A systolic array module configured to perform convolution operation with the weight data and the feature data of the input feature data block as inputs;

[0058] A post-processing module configured to process the result of the convolution calculation to obtain quantized output data;

[0059] A pooling module configured to perform maximum pooling operation on the quantized output data;

[0060] an output buffer module for reading and writing data.

[0061] In the embodiment, the instruction set includes the hyperparameters of each layer of the target detection neural network and the addresses for reading and writing data of the input buffer module, the parameter buffer module, the systolic array module, the post-processing module, the pooling module and the output buffer module; after receiving the start signal sent by the central processing unit, the controller controls the accelerator to work, accelerates the target detection neural network layer by layer, reads the corresponding control instructions of each layer from the instruction memory during the acceleration of each layer of the target detection neural network, and sends the control instructions to the input buffer module, the parameter buffer module, the systolic array module, the post-processing module, the pooling module and the output buffer module. The input buffer module, the parameter buffer module, the systolic array module, the post-processing module, the pooling module and the output buffer module work after receiving the instructions; the accelerator runs without the participation of the central processing unit.

[0062] In the embodiment, the instruction set is generated by a pre-written software script, and then the instruction set is stored in the Bin file format on the SD card of the FPGA chip. The instruction set mainly includes the hyperparameters of each layer of the model (the data reading and writing times and length of each module, padding, quantization shift bit number, convolution mode and other information) and the addresses for reading and writing data of each DMA and buffer module at runtime. When the system starts, the central processing unit reads the instruction set content from the SD card to the PSDDR, and then the central processing unit writes the instruction set to the instruction memory at one time. At runtime, the controller obtains instructions from the instruction memory to generate corresponding control instructions with the state machine, so as to control the running of each module.

[0063] The input buffer module includes a data preprocessing unit, a first data writing unit, an input feature storage unit and a first data reading unit. After reading the input feature data block, the data preprocessing unit performs boundary zero padding operation on the input feature data block according to the instruction sent by the controller, and then sends the processed feature data block to the first data writing unit. The input buffer module is equipped with 4 DMAs for reading 4 channels of input data from the DDR. Each DMA corresponds to read 1 channel of data. The read data is finally written into the input feature storage unit through the data preprocessing unit and the first data writing unit. The first data reading unit reads the input feature data block in the input feature storage unit, and constructs it into the data form required by the systolic array module to obtain the input feature data, and outputs the input feature data to the systolic array module. The first data reading unit and the first data writing unit obtain the read and write address instructions from the controller. Instead of generating the read and write addresses by logic, the operation efficiency of the accelerator can be improved.

[0064] The parameter cache module includes a weight cache unit and a bias cache unit; weight data and bias data of the target detection neural network are written into the DDR; the weight cache unit reads and stores the weight data of the target detection neural network from the external storage based on the on-chip Block RAM of the FPGA, and adopts a ping-pong cache operation to output the weight data to the weight data, thereby improving the efficiency of data output and avoiding data loss caused by differences in processing speed. The bias cache module only loads all the bias data from the DDR once at system startup.

[0065] The convolution calculation of the systolic array module adopts a weight reuse mode, the systolic array module includes 4x4 processing units, each processing unit includes 9 parallel hardware multipliers, the input is 4-channel input feature data and 8-channel weight data, and 8 channels of convolution results are output in parallel. The working principle of the systolic array is as shown in Figure 3 The weight data flows from top to bottom, and the input feature data flows from left to right. The internal structure of the processing unit is as shown in Figure 4 A0-A8 are 9 hardware multipliers, each hardware multiplier receives two unsigned 4-bit input data and two signed 4-bit weight data per clock pulse, and can complete 4 uint4*int4 multiplication operations per clock cycle. The calculation mode is as shown in Figure 5 The previous part and the completed accumulation operation are stored in the internal cache of the processing unit. After one convolution operation is completed, each processing unit outputs 36 convolution results.

[0066] The post-processing module receives 8-channel parallel convolution results and outputs 8-channel parallel quantization output. The processing of the post-processing module on the convolution results includes bias addition, activation and quantization operations. The bias addition operation on the convolution results is to add a bias value to the convolution results. The activation operation on the convolution results is to truncate the convolution results to unsigned integer data using the Relu activation function. The quantization operation on the convolution results is to shift the convolution results to the right to quantize the data to 4 bits. The right shift number is input by the controller according to the instruction set. The data of the same layer of the target detection neural network share one right shift value.

[0067] Quantizing the weight parameters and the activation output to 4 bits can significantly reduce the data storage volume, reduce the number of accelerator access to DDR memory, and reduce the transmission delay of data between modules in the accelerator.

[0068] The pooling module, after receiving the quantized output data, if the next layer of the current layer of the target detection neural network is a pooling layer, performs a maximum pooling operation on the quantized output data, and outputs the data after the maximum pooling operation to the output cache module, if the next layer of the current layer of the target detection neural network is not a pooling layer, does not operate on the quantized output data, and directly outputs the data to the output cache module by skipping the pooling module.

[0069] The maximum pooling is as shown in Figure 6 The principle is to take the maximum of the feature points in the neighborhood, and the feature of the data can be extracted through the maximum pooling operation, and the data volume is compressed through the pooling operation.

[0070] The output cache module includes a second data writing unit, a second data reading unit and an output feature storage unit. The second data writing unit obtains a writing address from the controller, and writes the 8-channel input data of the output feature data output by the pooling layer into the output feature storage unit in parallel according to the writing address. The output feature storage unit is realized based on the on-chip Block RAM of FPGA, and works by using the ping-pong cache operation. The second data reading unit outputs the data in the output feature storage unit in sequence, and transmits the data to the DDR through a DMA.

[0071] Example 2

[0072] On the basis of Embodiment 1, Embodiment 2 provides an upsampling module, as shown in Figure 7 , which is used for upsampling the data output by the output feature module. The upsampling module shares a DMA with the parameter cache module.

[0073] When performing image segmentation, pixel-level classification of the image is required, so after the abstract features are extracted by convolution, the extracted high-level features need to be enlarged by upsampling. The upsampling method provided in this embodiment is the bilinear interpolation method.

[0074] Bilinear interpolation is a linear interpolation extension of an interpolation function with two variables. The core idea is to perform linear interpolation in two directions respectively, and the specific implementation method is to calculate one point in the new image by using four (2*2) points in the original image.

[0075] Example 3

[0076] This embodiment provides a target detection system based on FPGA, as shown in Figure 8 , which is deployed on a ZC706 development board of Xilinx, and is realized based on a yolov4-tiny target detection neural network, and includes:

[0077] An image acquisition module is configured to acquire image data and input the image data into the central processor.

[0078] The central processing unit is used for processing data, after receiving the image data, the central processing unit sends an instruction start signal to the neural network accelerator, and when receiving the end signal sent by the neural network accelerator, the processed image data is outputted;

[0079] The neural network accelerator is used for receiving the instruction start signal sent by the central processing unit, accelerating the target detection neural network, and sending an end signal to the central processing unit after completing the acceleration;

[0080] The image output module is used for superimposing characters on the processed image data, obtaining the target detection result, and outputting the target detection result.

[0081] Obviously, the above embodiments of the present application are only examples for clearly illustrating the present application, and are not intended to limit the implementation modes of the present application. Based on the above description, other different forms of changes or variations can be made by those skilled in the art. Here, all the implementation modes are not required or can not be exhausted. Any modification, equivalent replacement and improvement made within the spirit and principle of the present application shall be included in the protection scope of the claims of the present application.

Claims

1. An FPGA-based target detection neural network accelerator, characterized in that: The accelerator is deployed on FPGA and includes: A control module comprising an instruction memory and a controller, wherein the instruction memory is used to receive an instruction set of the target detection neural network, and the controller is used to obtain instructions from the instruction set in the instruction memory, generate control instructions, and control the operation of the input cache module, the parameter cache module, the systolic array module, the post-processing module, the pooling module, and the output cache module; An input cache module is used to store the input feature data block of the current layer of the target detection neural network. The size of the input feature data block depends on the amount of input data of the current layer of the target detection neural network. The module is configured by receiving instructions from the controller. Parameter cache module, used to store bias data and weight data of the target detection neural network; The parameter cache module includes a weight cache unit and a bias cache unit; the weight data and bias data of the target detection neural network are written to the external storage; the weight cache unit reads and stores the weight data of the target detection neural network from the external storage based on the on-chip Block RAM of the FPGA, and outputs the weight data using a ping-pong cache operation; the bias cache unit loads all bias data from the external storage at one time when the accelerator is started; The systolic array module takes the weight data and the feature data of the input feature data block as input and performs convolution operation; The convolution calculation of the systolic array module adopts a weight reuse mode. The systolic array module includes a plurality of processing units, each of which includes a plurality of hardware multipliers. Each hardware multiplier receives two unsigned input data and two signed weight data per clock pulse, and can complete four multiplication operations per clock cycle. The 8-bit multiplication result will be sent to the data accumulation module, and the accumulation operation will be completed with the previous partial sum and stored in the internal cache of the processing unit. The post-processing module is used to process the results obtained by the convolution calculation to obtain quantized output data; The post-processing module processes the convolution results, including bias addition, activation, and quantization operations. The bias addition operation on the convolution result is to add the bias value to the convolution result; the activation operation on the convolution result is to use the Relu activation function to truncate the convolution result to unsigned integer data; the quantization operation on the convolution result is to shift the convolution result to the right and quantize the convolution result. The right shift number is input by the controller according to the instruction set, and the data of the same layer of the target detection neural network share a right shift value. Pooling module, used to perform maximum pooling operation on quantized output data; Output cache module, used for data read and write cache.

2. The FPGA-based target detection neural network accelerator according to claim 1, characterized in that: The instruction set includes hyperparameters of each layer of the target detection neural network and addresses for data reading and writing of the input cache module, parameter cache module, systolic array module, post-processing module, pooling module and output cache module; after receiving the start signal from the central processing unit, the controller controls the accelerator to work and accelerates the target detection neural network layer by layer. During the acceleration process of each layer of the target detection neural network, the controller reads the corresponding control instructions of each layer from the instruction memory and sends the control instructions to the input cache module, parameter cache module, systolic array module, post-processing module, pooling module and output cache module. The input cache module, parameter cache module, systolic array module, post-processing module, pooling module and output cache module work after receiving the instructions; the accelerator does not require the participation of the central processing unit when running.

3. The FPGA-based target detection neural network accelerator according to claim 2, characterized in that: The input cache module includes a data preprocessing unit, a first data writing unit, an input feature storage unit and a first data reading unit. After the input cache module reads the input feature data block, the data preprocessing unit performs a boundary zero padding operation on the input feature data block according to the instruction issued by the controller, and then sends the processed feature data block to the first data writing unit. The first data writing unit writes the obtained input feature data block into the input feature storage module. The first data reading unit reads the input feature data block in the input feature storage unit and constructs it into the data format required by the systolic array module to obtain input feature data, and outputs the input feature data to the systolic array module. The first data reading unit and the first data writing unit both obtain read and write address instructions from the controller.

4. The FPGA-based target detection neural network accelerator according to claim 3, characterized in that: After receiving the quantized output data, the pooling module performs a maximum pooling operation on the quantized output data if the next layer of the current layer of the target detection neural network is a pooling layer, and outputs the data after the maximum pooling operation to the output cache module; if the next layer of the current layer of the target detection neural network is not a pooling layer, the quantized output data is not operated, and the pooling module is skipped to directly output the data to the output cache module.

5. The FPGA-based target detection neural network accelerator according to claim 4, characterized in that: The output cache module includes a second data writing unit, a second data reading unit and an output feature storage unit. The second data writing unit obtains a write address from the controller and writes the output feature data output by the pooling layer into the output feature storage unit according to the write address. The output feature storage unit is implemented based on the on-chip Block RAM of the FPGA and operates using a ping-pong cache operation; the second data reading unit outputs the data in the output feature storage unit in sequence.

6. The FPGA-based target detection neural network accelerator according to claim 5, characterized in that: The accelerator further includes an upsampling module for upsampling the output feature data.

7. An FPGA-based target detection system, characterized in that: The target detection system is deployed on FPGA and includes: An image acquisition module is used to acquire image data and input the image data into a central processing unit; A central processing unit is used to process data. After receiving the image data, the central processing unit sends an instruction start signal to the neural network accelerator, and outputs the processed image data when receiving the end signal sent by the neural network accelerator; The neural network accelerator according to any one of claims 1 to 6, configured to receive a command start signal from a central processing unit, accelerate the target detection neural network, and send an end signal to the central processing unit after completing the acceleration; The image output module is used to superimpose characters on the processed image data to obtain target detection results and output the target detection results.

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