Gate drive circuit and display device

Abstract

The application relates to a gate driving circuit and a display device, the gate driving circuit comprises a plurality of cascaded gate driving units, the gate driving units charge horizontal scanning lines corresponding to display areas of a liquid crystal display panel, each gate driving unit comprises a pull-up control circuit, a pull-up circuit, a pull-down circuit, a pull-down maintaining circuit and a voltage stabilizing circuit, the voltage stabilizing circuit is electrically connected with the pull-up control circuit, the pull-up circuit, the pull-down circuit and the pull-down maintaining circuit, is used for receiving a second direct-current low-voltage signal and the pull-up control signal, and maintains stability of the pull-up control signal high potential according to the pull-up control signal and the second direct-current low-voltage signal. That is, the application can improve the stability of the scanning driving signal output waveform, and further improve the driving capacity of the gate driving circuit, so as to improve the charging rate of the liquid crystal display panel.

Description

[Technical Field]

[0001] This application relates to the field of display technology, specifically to a gate driving circuit and a display device. [Background Technology]

[0002] Liquid crystal displays (LCDs) offer advantages such as thinness, lightness, energy efficiency, and generally lower radiation levels compared to CRT (Cathode Ray Tube) displays, leading to their gradual replacement of CRTs and widespread application in various electronic products. Currently, GOA (Gateway Actuation) technology utilizes the TFT (Thin Film Transistor) LCD array manufacturing process to fabricate the gate line scan drive signal circuitry on the array substrate, enabling line-by-line scanning of the gate. Therefore, the existing LCD panel manufacturing process can be used to fabricate the horizontal scan line drive circuitry on the substrate surrounding the display area. GOA technology reduces the bonding process for external ICs, increasing production capacity and reducing product costs, and making LCD panels more suitable for manufacturing narrow-bezel or bezel-less display products.

[0003] The main architecture of the gate drive unit in the GOA circuit includes: a pull-up control circuit, a pull-up circuit, a pull-down circuit, and a pull-down sustaining circuit. The pull-up circuit outputs the clock signal as a scan drive signal. The pull-up control circuit outputs a pull-up control signal to control the on-time of the pull-up circuit. The pull-down circuit pulls both the pull-up control signal and the scan drive signal low. The pull-down sustaining circuit maintains both the pull-up control signal and the scan drive signal at a low potential. A higher high potential for the pull-up control signal results in greater stability, more sufficient in-plane pixel charging, and more stable GOA level transmission. Therefore, maintaining the high potential stability of the pull-up control signal is crucial for improving the driving capability of the GOA circuit. [Summary of the Invention]

[0004] This application provides a gate driving circuit and a display device to improve the reliability of the gate driving circuit.

[0005] To address the aforementioned problems, this application provides a gate driving circuit comprising multiple cascaded gate driving units, wherein the nth-stage gate driving unit is used to charge the nth-stage horizontal scan line of the display area of ​​the liquid crystal display panel, where n is a positive integer, and the nth-stage gate driving unit includes:

[0006] A pull-up control circuit is used to receive a start signal and output a pull-up control signal Q(n) according to the start signal;

[0007] A pull-up circuit, electrically connected to the pull-up control circuit, is used to receive the pull-up control signal Q and the clock signal CKn, and output the nth stage transmission signal ST(n) and the nth stage scan drive signal G(n) according to the pull-up control signal Q(n) and the clock signal CKn.

[0008] A pull-down circuit, electrically connected to the pull-up control circuit and the pull-up circuit, is used to receive a first DC low-voltage signal Vss1, and pull down the pull-up control signal Q(n) according to the first DC low-voltage signal Vss1, thereby pulling down the nth level scan drive signal G(n) so that the pull-up control signal Q(n) and the nth level scan drive signal G(n) are in the off state;

[0009] The pull-down sustaining circuit is electrically connected to the pull-up control circuit, the pull-up circuit, and the pull-down circuit. It receives the power supply voltage signal VDD and the first DC low voltage signal Vss1, and maintains the pull-up control signal Q(n) and the nth level scan drive signal G(n) in the off state according to the power supply voltage signal VDD and the first DC low voltage signal Vss1. It also outputs the (n+1)th level scan drive signal G(n+1) according to the first DC low voltage signal Vss1.

[0010] A voltage regulator circuit is electrically connected to the pull-up control circuit, the pull-up circuit, the pull-down circuit, and the pull-down sustaining circuit. It is used to receive the second DC low-voltage signal Vss2 and the pull-up control signal Q(n), and to maintain the stability of the high potential of the pull-up control signal Q(n) according to the pull-up control signal Q(n) and the second DC low-voltage signal Vss2.

[0011] In one embodiment, when n=1, the start signal is an initial signal, and the pull-up control circuit outputs a pull-up control signal Q(n) according to the initial signal; when n>1, the start signal is the (n-1)th stage transmission signal ST(n-1) and the (n-1)th stage scan drive signal G(n-1) output by the (n-1)th stage gate drive unit, and the pull-up control circuit outputs the pull-up control signal Q(n) according to the (n-1)th stage transmission signal ST(n-1) and the (n-1)th stage scan drive signal G(n-1).

[0012] In one embodiment, the pull-up control circuit includes a first thin-film transistor (T11); wherein, when n=1, the control terminal and the first terminal of the first thin-film transistor (T11) are input to the initial signal, and its second terminal is connected to the pull-up control signal point Q, for outputting the pull-up control signal Q(n) according to the initial signal; when n>1, the control terminal of the first thin-film transistor (T11) is input to the (n-1)th stage transmission signal ST(n-1), its first terminal is input to the (n-1)th stage scan drive signal G(n-1), and its second terminal is connected to the pull-up control signal point Q, for outputting the pull-up control signal Q(n) according to the (n-1)th stage transmission signal ST(n-1) and the (n-1)th stage scan drive signal G(n-1).

[0013] In one embodiment, the pull-up circuit includes: a second thin-film transistor (T22) and a third thin-film transistor (T21); wherein:

[0014] The control terminal of the second thin-film transistor (T22) is electrically connected to the pull-up control signal point Q, and is used to receive the pull-up control signal Q(n). Its first terminal is input with the clock signal CKn, and its second terminal is used to output the nth stage transmission signal ST(n) according to the pull-up control signal Q(n) and the clock signal CKn.

[0015] The control terminal of the third thin-film transistor (T21) is electrically connected to the pull-up control signal point Q, and is used to receive the pull-up control signal Q(n). Its first terminal is input to the clock signal CKn, and its second terminal is electrically connected to the horizontal scan line G, and is used to output the nth level scan drive signal G(n) according to the pull-up control signal Q(n) and the clock signal CKn.

[0016] In one embodiment, the pull-down circuit includes: a fourth thin-film transistor (T41) and a fifth thin-film transistor (T31); wherein:

[0017] The first terminal of the fourth thin-film transistor (T41) receives the first DC low-voltage signal Vss1, and its second terminal is electrically connected to the pull-up control signal point Q. This is used to pull down the pull-up control signal Q(n) according to the first DC low-voltage signal Vss1, so that the pull-up control signal Q(n) is in a closed state. Its first control terminal is electrically connected to the control terminal of the fifth thin-film transistor (T31), and is used to output the (n+1)th level scan drive signal G(n+1) according to the first DC low-voltage signal Vss1. Its second control terminal is electrically connected to the output terminal of the voltage regulator circuit, and is used to turn off the fourth thin-film transistor (T41) according to the second DC low-voltage signal Vss2 when the pull-up control signal Q(n) is at a high potential. When the pull-up control signal Q(n) is at a high potential, the second DC low-voltage signal Vss2 is less than the first DC low-voltage signal Vss1.

[0018] The first terminal of the fifth thin-film transistor (T31) receives the first DC low-voltage signal Vss1, and its second terminal is electrically connected to the horizontal scan line G. It is used to pull down the nth level scan drive signal G(n) according to the first DC low-voltage signal Vss1, so that the nth level scan drive signal G(n) is in the off state.

[0019] In one embodiment, the pull-down sustaining circuit includes: a sixth thin-film transistor (T51), a seventh thin-film transistor (T52), an eighth thin-film transistor (T53), a ninth thin-film transistor (T54), a tenth thin-film transistor (T42), and an eleventh thin-film transistor (T32); wherein:

[0020] The control terminal and the first terminal of the sixth thin-film transistor (T51) are input to the power supply voltage signal VDD, and its second terminal is electrically connected to the first terminal of the seventh thin-film transistor (T52) and the control terminal of the eighth thin-film transistor (T53), respectively.

[0021] The control terminal of the seventh thin-film transistor (T52) is electrically connected to the pull-up control signal point Q, and is used to input the pull-up control signal Q(n). Its second terminal is used to input the first DC low-voltage signal Vss1.

[0022] The first terminal of the eighth thin-film transistor (T53) receives the power supply voltage signal VDD, and its second terminal is electrically connected to the first terminal of the ninth thin-film transistor (T54), the first control terminal of the tenth thin-film transistor (T42), and the control terminal of the eleventh thin-film transistor (T32), respectively.

[0023] The control terminal of the ninth thin-film transistor (T54) is electrically connected to the pull-up control signal point Q, and is used to input the pull-up control signal Q(n). Its second terminal is used to input the first DC low-voltage signal Vss1.

[0024] The first terminal of the tenth thin-film transistor (T42) receives the first DC low-voltage signal Vss1, and its second terminal is electrically connected to the pull-up control signal point Q, which is used to maintain the pull-up control signal Q(n) in the off state according to the power supply voltage signal VDD and the first DC low-voltage signal Vss1. Its second control terminal is electrically connected to the output terminal of the voltage regulator circuit, which is used to turn off the tenth thin-film transistor (T42) according to the second DC low-voltage signal Vss2 when the pull-up control signal Q(n) is at a high potential.

[0025] The first terminal of the eleventh thin-film transistor (T32) receives the first DC low-voltage signal Vss1, and its second terminal is electrically connected to the horizontal scan line G, for maintaining the nth level scan drive signal G(n) in the off state according to the power supply voltage signal VDD and the first DC low-voltage signal Vss1.

[0026] In one embodiment, the voltage regulator circuit includes: a twelfth thin-film transistor (T61) and a thirteenth thin-film transistor (T62); wherein:

[0027] The first terminal of the twelfth thin film transistor (T61) receives the second DC low-voltage signal Vss2, and its second terminal is electrically connected to the second control terminal of the fourth thin film transistor (T41). Its control terminal is electrically connected to the pull-up control signal point Q, and is used to turn off the fourth thin film transistor (T41) according to the second DC low-voltage signal Vss2 when the pull-up control signal Q(n) is at a high potential.

[0028] The first terminal of the thirteenth thin-film transistor (T62) receives the second DC low-voltage signal Vss2, and its second terminal is electrically connected to the second control terminal of the tenth thin-film transistor (T42). Its control terminal is electrically connected to the pull-up control signal point Q, and is used to turn off the tenth thin-film transistor (T42) according to the second DC low-voltage signal Vss2 when the pull-up control signal Q(n) is at a high potential.

[0029] In one embodiment, during the blanking period, the potential of the second DC low-voltage signal Vss2 is zero, and the second control terminal of the fourth thin-film transistor (T41) and the second control terminal of the tenth thin-film transistor (T42) are reset.

[0030] In one embodiment, the low potential CDL of the clock signal CKn is less than the first DC low voltage signal Vss1.

[0031] To address the aforementioned problems, embodiments of this application provide a display device that includes the gate driving circuit described above.

[0032] The beneficial effects of this application are as follows: Unlike existing technologies, the gate driving circuit and display device provided in this application include a gate driving circuit comprising multiple cascaded gate driving (GOA) units. Each GOA unit charges the horizontal scan lines corresponding to the display area of ​​the liquid crystal display panel. Each GOA unit includes a pull-up control circuit, a pull-up circuit, a pull-down circuit, a pull-down sustaining circuit, and a voltage regulator circuit. The voltage regulator circuit is electrically connected to the pull-up control circuit, the pull-up circuit, the pull-down circuit, and the pull-down sustaining circuit, and is used to receive a second DC low-voltage signal Vss2 and the pull-up control signal Q(n), and maintain the stability of the high potential of the pull-up control signal Q(n) according to the pull-up control signal Q(n) and the second DC low-voltage signal Vss2. In other words, by adding a voltage regulator circuit to the GOA circuit to maintain the stability of the high voltage of the pull-up control signal, this invention can improve the stability of the output waveform of the scan drive signal, thereby improving the driving capability of the GOA circuit and thus increasing the charging rate of the liquid crystal display panel. [Attached Image Description]

[0033] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0034] Figure 1 This is a schematic diagram of the gate driving circuit provided in an embodiment of this application;

[0035] Figure 2 This is a timing diagram of the gate drive circuit provided in an embodiment of this application;

[0036] Figure 3 This is a schematic diagram of the gate drive circuit provided by existing technology;

[0037] Figure 4 This is a timing diagram of the gate drive circuit provided by existing technology.

Detailed Implementation Methods

[0038] The present application will now be described in further detail with reference to the accompanying drawings and embodiments. It should be particularly noted that the following embodiments are for illustrative purposes only and do not limit the scope of the application. Similarly, the following embodiments are only some, not all, embodiments of the present application, and all other embodiments obtained by those skilled in the art without inventive effort are within the scope of protection of the present application.

[0039] Please see Figure 1 , Figure 1 This is a schematic diagram of the gate drive circuit provided in an embodiment of this application. Figure 1 As shown, the gate driving circuit includes multiple cascaded gate driving units. The nth gate driving unit charges the nth horizontal scan line of the display area of ​​the liquid crystal display panel, where n is a positive integer. The nth gate driving unit includes:

[0040] Pull-up control circuit 100 is used to receive a start signal and output a pull-up control signal Q(n) according to the start signal;

[0041] Pull-up circuit 200 is electrically connected to pull-up control circuit 100, and is used to receive pull-up control signal Q and clock signal CK1, and output nth stage transmission signal ST(n) and nth stage scan drive signal G(n) according to pull-up control signal Q(n) and clock signal CK1.

[0042] The pull-down circuit 300 is electrically connected to the pull-up control circuit 100 and the pull-up circuit 200, and is used to receive the first DC low voltage signal Vss 1, and pull down the pull-up control signal Q(n) according to the first DC low voltage signal Vss 1, thereby pulling down the nth level scan drive signal G(n) so that the pull-up control signal Q(n) and the nth level scan drive signal G(n) are in the off state;

[0043] The pull-down sustaining circuit 400 is electrically connected to the pull-up control circuit 100, the pull-up circuit 200, and the pull-down circuit 300. It receives the power supply voltage signal VDD and the first DC low voltage signal Vss 1, and maintains the pull-up control signal Q(n) and the nth level scan drive signal G(n) in the off state according to the power supply voltage signal VDD and the first DC low voltage signal Vss 1. It also outputs the (n+1)th level scan drive signal G(n+1) according to the first DC low voltage signal Vss 1.

[0044] The voltage regulator circuit 500 is electrically connected to the pull-up control circuit 100, the pull-up circuit 200, the pull-down circuit 300, and the pull-down sustaining circuit 400. It is used to receive the second DC low voltage signal Vss2 and the pull-up control signal Q(n), and to maintain the stability of the high potential of the pull-up control signal Q(n) according to the pull-up control signal Q(n) and the second DC low voltage signal Vss2.

[0045] In one embodiment, when n=1, the start signal is an initial signal, and the pull-up control circuit 100 outputs a pull-up control signal Q(n) according to the initial signal; when n>1, the start signal is the (n-1)th stage transmission signal ST(n-1) and the (n-1)th stage scan drive signal G(n-1) output by the (n-1)th stage gate drive unit, and the pull-up control circuit 100 outputs the pull-up control signal Q(n) according to the (n-1)th stage transmission signal ST(n-1) and the (n-1)th stage scan drive signal G(n-1).

[0046] In one embodiment, such as Figure 1 As shown, the pull-up control circuit 100 includes a first thin-film transistor (T11); wherein, when n=1, the control terminal and the first terminal of the first thin-film transistor (T11) are input to the initial signal, and its second terminal is connected to the pull-up control signal point Q, for outputting the pull-up control signal Q(n) according to the initial signal; when n>1, the control terminal of the first thin-film transistor (T11) is input to the (n-1)th stage transmission signal ST(n-1), its first terminal is input to the (n-1)th stage scan drive signal G(n-1), and its second terminal is connected to the pull-up control signal point Q, for outputting the pull-up control signal Q(n) according to the (n-1)th stage transmission signal ST(n-1) and the (n-1)th stage scan drive signal G(n-1).

[0047] Other circuit modules will be described below.

[0048] In this application, the nth gate driving unit can be any of the multi-stage gate driving units in the gate driving circuit. The transistor can be a P-type thin-film transistor or an N-type thin-film transistor.

[0049] Based on Figures 1 to 4 This application will be described in detail with reference to a specific GOA circuit.

[0050] Figure 3 This is a schematic diagram of the gate drive circuit provided by existing technology. Figure 4 This is a timing diagram of the gate drive circuit provided by existing technology.

[0051] like Figure 3It is known that a gate drive circuit provided by the prior art includes:

[0052] The coupling capacitor Cbt is connected to point Q at one end and to point S at the other end.

[0053] The first thin-film transistor (T11) serves as a pull-up control circuit. The control terminal of the first thin-film transistor (T11) receives the (n-1)th stage transmission signal ST(n-1), its first terminal receives the (n-1)th stage scan drive signal G(n-1), and its second terminal is connected to the pull-up control signal point Q. It is used to output the pull-up control signal Q(n) according to the (n-1)th stage transmission signal ST(n-1) and the (n-1)th stage scan drive signal G(n-1).

[0054] The second thin-film transistor (T22) and the third thin-film transistor (T21) serve as pull-up circuits. The control terminal of the second thin-film transistor (T22) is electrically connected to the pull-up control signal point Q, and is used to receive the pull-up control signal Q(n). Its first terminal is input to the clock signal CKn, and its second terminal is used to output the nth stage transmission signal ST(n) according to the pull-up control signal Q(n) and the clock signal CKn. The control terminal of the third thin-film transistor (T21) is electrically connected to the pull-up control signal point Q, and is used to receive the pull-up control signal Q(n). Its first terminal is input to the clock signal CKn, and its second terminal is electrically connected to the horizontal scan line G, and is used to output the nth stage scan drive signal G(n) according to the pull-up control signal Q(n) and the clock signal CKn.

[0055] A fourth thin-film transistor (T41) and a fifth thin-film transistor (T31) serve as a pull-down circuit. The fourth thin-film transistor (T41) receives a low-voltage DC signal Vss at its first terminal and is electrically connected to the pull-up control signal point Q. It is used to pull down the pull-up control signal Q(n) according to the low-voltage DC signal Vss, so that the pull-up control signal Q(n) is in a closed state. Its control terminal is electrically connected to the control terminal of the fifth thin-film transistor (T31), and is used to output the (n+1)th level scan drive signal G(n+1) according to the low-voltage DC signal Vss. The fifth thin-film transistor (T31) receives the low-voltage DC signal Vss at its first terminal and is electrically connected to the horizontal scan line G. It is used to pull down the nth level scan drive signal G(n) according to the low-voltage DC signal Vss, so that the nth level scan drive signal G(n) is in a closed state.

[0056] The sixth thin-film transistor (T51), the seventh thin-film transistor (T52), the eighth thin-film transistor (T53), the ninth thin-film transistor (T54), the tenth thin-film transistor (T42), and the eleventh thin-film transistor (T32) serve as a pull-down sustaining circuit. Specifically: the control terminal and first terminal of the sixth thin-film transistor (T51) are input to the power supply voltage signal VDD, and its second terminal is electrically connected to the first terminal of the seventh thin-film transistor (T52) and the control terminal of the eighth thin-film transistor (T53), respectively. The control terminal of the seventh thin-film transistor (T52) is electrically connected to the pull-up control signal point Q, used to input the pull-up control signal Q(n), and its second terminal is input to the DC low-voltage signal Vss. The eighth thin-film transistor (T53)... The first terminal of the transistor receives the power supply voltage signal VDD, and its second terminal is electrically connected to the first terminal of the ninth thin-film transistor (T54), the control terminal of the tenth thin-film transistor (T42), and the control terminal of the eleventh thin-film transistor (T32), respectively. The control terminal of the ninth thin-film transistor (T54) is electrically connected to the pull-up control signal point Q and is used to input the pull-up control signal Q(n). Its second terminal receives the first DC low-voltage signal Vss1. The first terminal of the tenth thin-film transistor (T42) receives the DC low-voltage signal Vss, and its second terminal is electrically connected to the pull-up control signal point Q. It is used to maintain the pull-up control signal Q(n) in the off state according to the power supply voltage signal VDD and the DC low-voltage signal Vss.

[0057] The first terminal of the eleventh thin-film transistor (T32) receives the DC low-voltage signal Vss, and its second terminal is electrically connected to the horizontal scan line G, for maintaining the nth level scan drive signal G(n) in the off state according to the power supply voltage signal VDD and the DC low-voltage signal Vss.

[0058] Specifically, according to Figure 3 The existing GOA circuit diagram shown and Figure 4 The timing diagram shown illustrates the following operational stages of the GOA circuit:

[0059] Q-point precharge: When G(n-1) and ST(n-1) in the previous row are high, T11 is turned on, and Q-point is precharged to a high potential;

[0060] G(n) Output: CKn becomes high, outputting G(n) at a high potential, and Q is coupled to a higher point through capacitor Cbt. At this time, Vgs of T11 / T41 / T42 = 0. If the TFT experiences negative drift, the TFT will turn on, causing leakage at the Q point (e.g.). Figure 4 The thick dashed line in the middle cannot maintain a high potential, which in turn makes the high potential of the output G(n) and the stage transmission ST(n) signal not high, showing an abnormality;

[0061] Low-level maintenance: The next line outputs G(n+1) at a high level, T31 / T41 is turned on, G(n) and Q point are pulled down to a low level VSS. After passing through the inverter, Q point Qb is at a high level. T32 / T42 is turned on, maintaining Q point Q(n) and G point G(n) at a low level.

[0062] That is, targeting Figure 3 In the GOA circuit shown, after Q-point pre-charging, CKn turns on. When Q-point coupling maintains a high potential, the Vgs of the three transistor TFTs T11 / T41 / T42 connected to Q-point is 0. Once the TFTs experience negative drift (especially oxide TFTs), these three TFTs turn on, causing leakage at Q-point and making it impossible to maintain a high potential. Consequently, the high potential of the output G(N) and stage transmission ST(N) signals is not high, resulting in insufficient in-plane pixel charging and abnormal GOA stage transmission, ultimately leading to display abnormalities.

[0063] Figure 1 This is a schematic diagram of the gate driving circuit provided in an embodiment of this application. Figure 2 This is a timing diagram of the gate drive circuit provided in an embodiment of this application; as shown... Figure 1 As shown, in the gate drive circuit provided in this application:

[0064] The pull-up control circuit 100 includes a first thin-film transistor (T11); when n>1, the control terminal of the first thin-film transistor (T11) receives the (n-1)th stage transmission signal ST(n-1), its first terminal receives the (n-1)th stage scan drive signal G(n-1), and its second terminal is connected to the pull-up control signal point Q, for outputting the pull-up control signal Q(n) according to the (n-1)th stage transmission signal ST(n-1) and the (n-1)th stage scan drive signal G(n-1).

[0065] The pull-up circuit 200 includes a second thin-film transistor (T22) and a third thin-film transistor (T21); wherein: the control terminal of the second thin-film transistor (T22) is electrically connected to the pull-up control signal point Q, and is used to receive the pull-up control signal Q(n), its first terminal is input to the clock signal CKn, and its second terminal is used to output the nth stage transmission signal ST(n) according to the pull-up control signal Q(n) and the clock signal CKn; the control terminal of the third thin-film transistor (T21) is electrically connected to the pull-up control signal point Q, and is used to receive the pull-up control signal Q(n), its first terminal is input to the clock signal CKn, and its second terminal is electrically connected to the horizontal scan line G, and is used to output the nth stage scan drive signal G(n) according to the pull-up control signal Q(n) and the clock signal CKn.

[0066] The pull-down circuit 300 includes a fourth thin-film transistor (T41) and a fifth thin-film transistor (T31); wherein: the first terminal of the fourth thin-film transistor (T41) receives the first DC low-voltage signal Vss1, and its second terminal is electrically connected to the pull-up control signal point Q, for pulling down the pull-up control signal Q(n) according to the first DC low-voltage signal Vss1, so that the pull-up control signal Q(n) is in a closed state; its first control terminal is electrically connected to the control terminal of the fifth thin-film transistor (T31), for adjusting the first DC low-voltage signal Vss1 according to the first DC low-voltage signal Vss1. The output is the (n+1)th level scan drive signal G(n+1), whose second control terminal is electrically connected to the output terminal of the voltage regulator circuit. When the pull-up control signal Q(n) is at a high potential, the fourth thin film transistor (T41) is turned off according to the second DC low voltage signal Vss2. When the pull-up control signal Q(n) is at a high potential, the second DC low voltage signal Vss2 is less than the first DC low voltage signal Vss1. The first terminal of the fifth thin film transistor (T31) is input to the first DC low voltage signal Vss1, and its second terminal is electrically connected to the horizontal scan line G. It is used to pull down the nth level scan drive signal G(n) according to the first DC low voltage signal Vss1, so that the nth level scan drive signal G(n) is in the off state.

[0067] The pull-down sustaining circuit 400 includes: a sixth thin-film transistor (T51), a seventh thin-film transistor (T52), an eighth thin-film transistor (T53), a ninth thin-film transistor (T54), a tenth thin-film transistor (T42), and an eleventh thin-film transistor (T32); wherein: the control terminal and the first terminal of the sixth thin-film transistor (T51) are input to the power supply voltage signal VDD, and its second terminal is electrically connected to the first terminal of the seventh thin-film transistor (T52) and the control terminal of the eighth thin-film transistor (T53), respectively; the control terminal of the seventh thin-film transistor (T52) is electrically connected to the pull-up control signal point Q, and is used to input the pull-up control signal Q(n), and its second terminal is input to the first DC low-voltage signal Vss. 1; The first terminal of the eighth thin-film transistor (T53) receives the power supply voltage signal VDD, and its second terminal is electrically connected to the first terminal of the ninth thin-film transistor (T54), the first control terminal of the tenth thin-film transistor (T42), and the control terminal of the eleventh thin-film transistor (T32), respectively; the control terminal of the ninth thin-film transistor (T54) is electrically connected to the pull-up control signal point Q, and is used to input the pull-up control signal Q(n), and its second terminal receives the first DC low-voltage signal Vss1; the first terminal of the tenth thin-film transistor (T42) receives the first DC low-voltage signal Vss1, and its second terminal is electrically connected to the pull-up control signal point Q, and is used to input the power supply voltage signal VDD and the first DC low-voltage signal Vss1 according to the power supply voltage signal VDD and the first DC low-voltage signal Vss1. 1. The pull-up control signal Q(n) is kept in the off state, and its second control terminal is electrically connected to the output terminal of the voltage regulator circuit. When the pull-up control signal Q(n) is at a high potential, the tenth thin film transistor (T42) is turned off according to the second DC low voltage signal Vss2. The first terminal of the eleventh thin film transistor (T32) is input to the first DC low voltage signal Vss1, and its second terminal is electrically connected to the horizontal scan line G. It is used to keep the nth level scan drive signal G(n) in the off state according to the power supply voltage signal VDD and the first DC low voltage signal Vss1.

[0068] The voltage stabilizing circuit 500 includes: a twelfth thin film transistor (T61) and a thirteenth thin film transistor (T62); wherein: the first end of the twelfth thin film transistor (T61) inputs the second DC low voltage signal Vss2, its second end is electrically connected to the second control end of the fourth thin film transistor (T41), and its control end is electrically connected to the pull-up control signal point Q, and is used to turn off the fourth thin film transistor (T41) according to the second DC low voltage signal Vss2 when the pull-up control signal Q(n) is at a high potential; the first end of the thirteenth thin film transistor (T62) inputs the second DC low voltage signal Vss2, its second end is electrically connected to the second control end of the tenth thin film transistor (T42), and its control end is electrically connected to the pull-up control signal point Q, and is used to turn off the tenth thin film transistor (T42) according to the second DC low voltage signal Vss2 when the pull-up control signal Q(n) is at a high potential.

[0069] The coupling capacitor Cbt is electrically connected to point Q at one end and to point S at the other end.

[0070] As Figure 2 shown, during the blank time period, the potential of the second DC low voltage signal Vss2 is zero, so that the second control ends of the fourth thin film transistor (T41) and the tenth thin film transistor (T42) are reset.

[0071] As Figure 2 shown, the low potential CKL of the clock signal CKn is less than the first DC low voltage signal Vss 1.

[0072] As Figure 1 And Figure 2 shown, in this application:

[0073] Change T41 / T42 to a four-terminal TFT device, and add a voltage stabilizing circuit T61 / T62; the second control end (one of the bottom gate or the top gate) of T41 / T42 is connected to VSS2 through T61 / T62, and VSS2 < VSS 1. Then when the Q point is at a high potential, T61 / T62 is turned on, and for the first control end (the other of the bottom gate or the top gate) of T41 / T42, Vgs = 0, and for the second control end, Vgs = VSS2 - VSS 1 < 0. By adjusting the VSS2 voltage, T41 / T42 can be completely turned off to avoid leakage at the Q point;

[0074] Adjust the low potential CKL of CKn so that CKL < VSS 1; for T11, when the Q point is at a high potential, Vgs = CKL - VSS 1 < 0, and T11 can be completely turned off to avoid leakage at the Q point;

[0075] During the Blank time phase, the VSS2 point is raised to 0 to reset the second control terminal of T41 / T42, thus preventing the TFT from becoming negatively biased under prolonged pressure.

[0076] The above comparison shows that this application has the following beneficial effects:

[0077] By regulating the bottom gate (second control terminal) voltage and CKL voltage of the four-terminal TFT device, Q-point leakage current is suppressed, thus improving the GOA circuit's resistance to TFT negative bias.

[0078] For T41 / T42, the three-terminal device is changed to a four-terminal TFT. When the Q point is at a high potential, the bottom gate (second control terminal) is connected to a lower potential than the top gate (second control terminal). For T11, the CKL voltage is adjusted to be lower than VGL, thereby ensuring that the TFT is completely turned off and avoiding display abnormalities caused by Q point leakage. In this embodiment, the bottom gate (as the second control terminal) is connected to the lower potential VSS2. Alternatively, the top gate and bottom gate can be swapped during the design, with the bottom gate (as the first control terminal) connected to VSS1 and the top gate (as the second control terminal) connected to VSS2. This method also falls within the protection scope of this case.

[0079] This embodiment features a design to suppress leakage current at point Q of the GOA circuit. By adjusting the voltage, the GOA circuit can operate normally under different Vth conditions, making it suitable for display panels.

[0080] The above embodiments only provide one GOA circuit, but the four-terminal device and corresponding circuit of this case can also be applied to other GOA circuits. Any variant design based on this idea is within the protection scope of this case.

[0081] In other embodiments, this application also provides a display device, which includes the gate driving circuit of any of the above embodiments. In some embodiments, the display device may further include a display panel, and the gate driving circuit may be integrated into the display panel and electrically connected to each scan line of the display panel.

[0082] Specifically, the gate driving circuit may include multiple cascaded gate driving units, wherein the nth gate driving unit is used to charge the nth horizontal scan line of the display area of ​​the liquid crystal display panel, where n is a positive integer, and the nth gate driving unit includes:

[0083] A pull-up control circuit is used to receive a start signal and output a pull-up control signal Q(n) according to the start signal;

[0084] A pull-up circuit, electrically connected to the pull-up control circuit, is used to receive the pull-up control signal Q and the clock signal CKn, and output the nth stage transmission signal ST(n) and the nth stage scan drive signal G(n) according to the pull-up control signal Q(n) and the clock signal CKn.

[0085] A pull-down circuit, electrically connected to the pull-up control circuit and the pull-up circuit, is used to receive a first DC low-voltage signal Vss1, and pull down the pull-up control signal Q(n) according to the first DC low-voltage signal Vss1, thereby pulling down the nth level scan drive signal G(n) so that the pull-up control signal Q(n) and the nth level scan drive signal G(n) are in the off state;

[0086] The pull-down sustaining circuit is electrically connected to the pull-up control circuit, the pull-up circuit, and the pull-down circuit. It receives the power supply voltage signal VDD and the first DC low voltage signal Vss1, and maintains the pull-up control signal Q(n) and the nth level scan drive signal G(n) in the off state according to the power supply voltage signal VDD and the first DC low voltage signal Vss1. It also outputs the (n+1)th level scan drive signal G(n+1) according to the first DC low voltage signal Vss1.

[0087] A voltage regulator circuit is electrically connected to the pull-up control circuit, the pull-up circuit, the pull-down circuit, and the pull-down sustaining circuit. It is used to receive the second DC low-voltage signal Vss2 and the pull-up control signal Q(n), and to maintain the stability of the high potential of the pull-up control signal Q(n) according to the pull-up control signal Q(n) and the second DC low-voltage signal Vss2.

[0088] It should be noted that the display device in this application embodiment has the same beneficial effects as the gate driving circuit described above because it is equipped with the gate driving circuit provided in this application embodiment.

[0089] In summary, this application provides a gate driving circuit and a display device. The gate driving circuit includes multiple cascaded gate driving (GOA) units. Each GOA unit charges the horizontal scan lines corresponding to the display area of ​​the liquid crystal display panel. Each GOA unit includes a pull-up control circuit, a pull-up circuit, a pull-down circuit, a pull-down sustaining circuit, and a voltage regulator circuit. The voltage regulator circuit is electrically connected to the pull-up control circuit, the pull-up circuit, the pull-down circuit, and the pull-down sustaining circuit, and is used to receive a second DC low-voltage signal Vss2 and the pull-up control signal Q(n), and maintain the stability of the high potential of the pull-up control signal Q(n) according to the pull-up control signal Q(n) and the second DC low-voltage signal Vss2. That is, by adding a voltage regulator circuit to the GOA circuit to maintain the stability of the high voltage of the pull-up control signal, this invention can improve the stability of the scan drive signal output waveform, thereby improving the driving capability of the GOA circuit and thus improving the charging rate of the liquid crystal display panel.

[0090] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A gate driving circuit, characterized in that, It includes multiple cascaded gate driving units, wherein the nth gate driving unit is used to charge the nth horizontal scan line of the display area of ​​the liquid crystal display panel, where n is a positive integer, and the nth gate driving unit includes: A pull-up control circuit is used to receive a start signal and output a pull-up control signal according to the start signal; A pull-up circuit, electrically connected to the pull-up control circuit, is used to receive the pull-up control signal and the clock signal, and output the nth stage transmission signal and the nth stage scan drive signal according to the pull-up control signal and the clock signal; A pull-down circuit, electrically connected to the pull-up control circuit and the pull-up circuit, is used to receive a first DC low-voltage signal, and pull down the pull-up control signal according to the first DC low-voltage signal, thereby pulling down the nth level scan drive signal, so that the pull-up control signal and the nth level scan drive signal are in a closed state; The pull-down sustaining circuit is electrically connected to the pull-up control circuit, the pull-up circuit, and the pull-down circuit. It receives the power supply voltage signal and the first DC low voltage signal, and maintains the pull-up control signal and the nth level scan drive signal in the off state according to the power supply voltage signal and the first DC low voltage signal. It also outputs the (n+1)th level scan drive signal according to the first DC low voltage signal. A voltage regulator circuit is electrically connected to the pull-up control circuit, the pull-up circuit, the pull-down circuit, and the pull-down sustaining circuit. It is used to receive the second DC low-voltage signal and the pull-up control signal, and to maintain the stability of the high potential of the pull-up control signal according to the pull-up control signal and the second DC low-voltage signal. The pull-down circuit includes a fourth thin-film transistor. The first terminal of the fourth thin-film transistor receives the first DC low-voltage signal, its second terminal is electrically connected to the pull-up control signal point, and its second control terminal is electrically connected to the output terminal of the voltage regulator circuit. It is used to turn off the fourth thin-film transistor according to the second DC low-voltage signal when the pull-up control signal is at a high potential. When the pull-up control signal is at a high potential, the second DC low-voltage signal is less than the first DC low-voltage signal. The pull-down sustaining circuit includes a tenth thin-film transistor. The first terminal of the tenth thin-film transistor receives the first DC low-voltage signal, its second terminal is electrically connected to the pull-up control signal, and its second control terminal is electrically connected to the output terminal of the voltage regulator circuit. It is used to turn off the tenth thin-film transistor according to the second DC low-voltage signal when the pull-up control signal is at a high potential. The voltage regulator circuit includes a twelfth thin-film transistor and a thirteenth thin-film transistor. The first terminal of the twelfth thin-film transistor receives the second low-voltage DC signal, and its second terminal is electrically connected to the second control terminal of the fourth thin-film transistor. Its control terminal is electrically connected to the pull-up control signal point, and is used to turn off the fourth thin-film transistor according to the second low-voltage DC signal when the pull-up control signal is at a high potential. The first terminal of the thirteenth thin-film transistor receives the second low-voltage DC signal, and its second terminal is electrically connected to the second control terminal of the tenth thin-film transistor. Its control terminal is electrically connected to the pull-up control signal point, and is used to turn off the tenth thin-film transistor according to the second low-voltage DC signal when the pull-up control signal is at a high potential.

2. The gate driving circuit according to claim 1, characterized in that, When n=1, the start signal is the initial signal, and the pull-up control circuit outputs a pull-up control signal according to the initial signal; when n>1, the start signal is the (n-1)th stage transmission signal and the (n-1)th stage scan drive signal output by the (n-1)th stage gate drive unit, and the pull-up control circuit outputs the pull-up control signal according to the (n-1)th stage transmission signal and the (n-1)th stage scan drive signal.

3. The gate driving circuit according to claim 2, characterized in that, The pull-up control circuit includes a first thin-film transistor; wherein, when n=1, the control terminal and the first terminal of the first thin-film transistor are input to the initial signal, and its second terminal is connected to the pull-up control signal point, for outputting the pull-up control signal according to the initial signal; when n>1, the control terminal of the first thin-film transistor is input to the (n-1)th stage cascade signal, its first terminal is input to the (n-1)th stage scan drive signal, and its second terminal is connected to the pull-up control signal point, for outputting the pull-up control signal according to the (n-1)th stage cascade signal and the (n-1)th stage scan drive signal.

4. The gate driving circuit according to claim 3, characterized in that, The pull-up circuit includes: a second thin-film transistor and a third thin-film transistor; wherein: The control terminal of the second thin-film transistor is electrically connected to the pull-up control signal point to receive the pull-up control signal. Its first terminal receives the clock signal, and its second terminal is used to output the nth stage transmission signal according to the pull-up control signal and the clock signal. The control terminal of the third thin-film transistor is electrically connected to the pull-up control signal point to receive the pull-up control signal. Its first terminal is input to the clock signal, and its second terminal is electrically connected to the horizontal scan line to output the nth level scan drive signal according to the pull-up control signal and the clock signal.

5. The gate driving circuit according to claim 4, characterized in that, The pull-down circuit further includes a fifth thin-film transistor; wherein: The fourth thin-film transistor is used to pull down the pull-up control signal according to the first DC low-voltage signal so that the pull-up control signal is in a closed state. Its first control terminal is electrically connected to the control terminal of the fifth thin-film transistor and is used to output the (n+1)th level scan drive signal according to the first DC low-voltage signal. The first terminal of the fifth thin-film transistor receives the first DC low-voltage signal, and its second terminal is electrically connected to the horizontal scan line. It is used to pull down the nth-level scan drive signal according to the first DC low-voltage signal so that the nth-level scan drive signal is in a closed state.

6. The gate driving circuit according to claim 5, characterized in that, The pull-down sustaining circuit further includes a sixth thin-film transistor, a seventh thin-film transistor, an eighth thin-film transistor, a ninth thin-film transistor, and an eleventh thin-film transistor; wherein: The power supply voltage signal is input to the control terminal and the first terminal of the sixth thin film transistor, and its second terminal is electrically connected to the first terminal of the seventh thin film transistor and the control terminal of the eighth thin film transistor, respectively. The control terminal of the seventh thin-film transistor is electrically connected to the pull-up control signal point for inputting the pull-up control signal, and its second terminal is used to input the first DC low-voltage signal. The power supply voltage signal is input at the first terminal of the eighth thin film transistor, and its second terminal is electrically connected to the first terminal of the ninth thin film transistor, the first control terminal of the tenth thin film transistor, and the control terminal of the eleventh thin film transistor, respectively. The control terminal of the ninth thin-film transistor is electrically connected to the pull-up control signal point for inputting the pull-up control signal, and its second terminal is used to input the first DC low-voltage signal. The tenth thin-film transistor is used to maintain the pull-up control signal in the off state according to the power supply voltage signal and the first DC low voltage signal; The first terminal of the eleventh thin-film transistor receives the first low-voltage DC signal, and its second terminal is electrically connected to the horizontal scan line, for maintaining the nth-level scan drive signal in the off state according to the power supply voltage signal and the first low-voltage DC signal.

7. The gate driving circuit according to claim 6, characterized in that, During the blanking period, the potential of the second DC low-voltage signal is zero, and the second control terminal of the fourth thin-film transistor and the second control terminal of the tenth thin-film transistor are reset.

8. The gate driving circuit according to any one of claims 1 to 7, characterized in that, The low potential of the clock signal is lower than that of the first DC low voltage signal.

9. A display device, characterized in that, Includes the gate drive circuit as described in any one of claims 1 to 8.

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