Serial bus data autonomous analysis controller and working method

Abstract

The serial bus data autonomous analysis controller belongs to the field of digital circuits. On the basis of the UART protocol IP core, the data autonomous analysis state machine is designed according to the serial bus data ICD. The serial bus data autonomous analysis controller controls the data autonomous analysis state machine to realize the switching of six states by periodically inquiring the state register and the data register of the UART protocol IP core, and simultaneously analyzes the serial data according to the bus data ICD and stores the serial data in the designated space for the processor to read. The data autonomous analysis state machine is designed according to the bus data ICD to solve the problem of large time cost of the processor in analyzing the serial data, realizes the autonomous analysis of the serial data, reduces the time cost of the processor in analyzing the serial data, significantly improves the processor efficiency, and can be widely applied to the industrial field.

Description

Technical Field

[0001] This invention relates to the technical field of digital circuits, and in particular to a serial bus data autonomous parsing controller and its operating method. Background Technology

[0002] Serial buses (including RS422, RS232, and RS485) are a commonly used standard bus interface, characterized by their simple structure and high flexibility. In the aerospace field, there are numerous device control serial bus interfaces between airborne equipment. Currently, existing serial data parsing methods involve establishing a circular buffer in RAM, with the processor cyclically querying the status and data information of the UART protocol IP core in the FPGA and storing the data in the circular buffer. The data is then parsed based on the bus data ICD. Considering that airborne equipment often contains multiple serial bus interfaces, serial data parsing results in a large number of accesses to peripherals such as the FPGA and RAM by the processor, leading to increased processor time overhead and significantly reduced processor efficiency.

[0003] Reducing the time overhead of processor parsing serial data and improving its efficiency is of great engineering significance. Airborne equipment typically uses FPGAs to integrate UART protocol IP cores to implement serial bus protocol conversion. It is necessary to design a serial bus data autonomous parsing controller to achieve autonomous parsing of serial data, reduce the time overhead of processor parsing serial data, and significantly improve processor efficiency. Summary of the Invention

[0004] In view of this, the serial bus data autonomous parsing controller provided by the present invention reduces the time overhead of the processor in parsing serial data and significantly improves the processor's efficiency.

[0005] A serial bus data autonomous parsing controller, implemented based on a programmable logic device (PLD), includes a data autonomous parsing state machine and a UART protocol IP core communicatively connected to the data autonomous parsing state machine. The PLD includes a bus interface module.

[0006] The data autonomous parsing state machine parses and stores data based on serial bus data ICD;

[0007] The data autonomous parsing state machine (FSM) is connected to a bus interface module, which is connected to an external processor via a parallel bus. The processor can read the data parsed and stored by the data autonomous parsing state machine through the bus interface module.

[0008] The UART protocol IP core is connected to the bus transceiver via a unidirectional serial data line and is used to convert data from serial to parallel according to the frame format of the serial bus.

[0009] The data autonomous parsing state machine periodically queries the status information of the UART protocol IP core, controls the data autonomous parsing state machine to switch states, parses data according to the bus data ICD, and stores the parsed data for the processor to read.

[0010] Secondly, a method for operating a serial bus data autonomous parsing controller is provided, applied in the aforementioned serial bus data parsing controller. The data autonomous parsing state machine is configured with a temporary data storage area. The data autonomous parsing state machine includes six states: idle0, step1, step2, step3, step4, and step5. The bus interface module also includes a fixed data storage area. The operating method includes...

[0011] Step 0: The data autonomous parsing state machine periodically obtains the status information of the UART protocol IP core. If the status information shows that there is no data in the IP core receive buffer, then it continues to stay in Idle0; if the status information shows that there is data in the IP core receive buffer, then the data is read out and it is determined whether the data is equal to 8'hAA. If yes, then it jumps to Step 1; if no, it continues to stay in Idle0.

[0012] Step 1: The data autonomous parsing state machine periodically obtains the status information of the UART protocol IP core. If the status information shows that there is no data in the IP core receive buffer, then continue to Step 1. If the status information shows that there is data in the IP core receive buffer, then read out the data and determine whether the data is equal to 8'h55. If yes, then jump to Step 2. If no, then jump to Idle0.

[0013] Step 2: The data autonomous parsing state machine periodically obtains the status information of the UART protocol IP core. If the status information shows that there is no data in the IP core receive buffer, then continue to Step 2. If the status information shows that there is data in the IP core receive buffer, then read out the data, assign it to the frame count, and jump to Step 3.

[0014] Step 3: The data autonomous parsing state machine periodically obtains the status information of the UART protocol IP core. If the status information shows that there is no data in the IP core receive buffer, then continue to Step 3; if the status information shows that there is data in the IP core receive buffer, then read out the data, assign it to the packet length and the local variable len, and jump to Step 4.

[0015] Step 4: The data autonomous parsing state machine periodically obtains the status information of the UART protocol IP core. If the status information shows that there is no data in the IP core receive buffer, then continue to Step 4. If the status information shows that there is data in the IP core receive buffer, then read out the data and store it in the temporary data storage area. At the same time, the local variable len is decremented by 1, and it is determined whether the decremented len is equal to 0. If yes, then jump to Step 5; otherwise, continue to Step 4.

[0016] Step 5: The data autonomous parsing state machine periodically obtains the status information of the UART protocol IP core. If the status information shows that there is no data in the IP core receive buffer, then continue to Step 5; if the status information shows that there is data in the IP core receive buffer, then read out the data, assign it to the checksum, transfer the data in the temporary data storage area to the fixed data storage area, and jump to Idle0.

[0017] Beneficial effects

[0018] Based on the UART protocol IP core, this invention designs a serial bus data autonomous parsing controller using a programmable logic device, and designs a data autonomous parsing state machine based on the bus data ICD. By periodically querying the UART protocol IP core to obtain status information and data, the controller switches the data autonomous parsing state machine, realizing autonomous parsing of serial data. This reduces the time overhead of the processor in serial data parsing, significantly improves the processor's efficiency, and can be widely used in industrial fields. Attached Figure Description

[0019] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 The architecture diagram of the controller for autonomous parsing of serial data;

[0021] Figure 2 For serial bus data ICD;

[0022] Figure 3 To enable data to autonomously parse the state machine state transition diagram. Detailed Implementation

[0023] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0024] The following specific examples illustrate the implementation of this disclosure. Those skilled in the art can easily understand other advantages and effects of this disclosure from the content disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. This disclosure can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this disclosure. It should be noted that, in the absence of conflict, the following embodiments and features in the embodiments can be combined with each other. Based on the embodiments in this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0025] It should be noted that various aspects of embodiments within the scope of the appended claims are described below. It will be apparent that the aspects described herein can be embodied in a wide variety of forms, and any particular structure and / or function described herein is merely illustrative. Based on this disclosure, those skilled in the art will understand that one aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number of aspects set forth herein can be used to implement the device and / or practice the method. Additionally, this device and / or method can be implemented using other structures and / or functionalities besides one or more of the aspects set forth herein.

[0026] It should also be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of this disclosure. The drawings only show the components related to this disclosure and are not drawn according to the number, shape and size of the components in actual implementation. In actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0027] Furthermore, specific details are provided in the following description to facilitate a thorough understanding of the examples. However, those skilled in the art will understand that these aspects can be practiced without these specific details.

[0028] See Figure 1 The serial bus data autonomous parsing controller shown is implemented based on a programmable logic device (FPGA). It includes a data autonomous parsing state machine (FSM) and a UART protocol IP core that communicates with the FSM. The FPGA includes a bus interface module.

[0029] The data autonomous parsing state machine parses and stores data based on the serial bus data ICD. The ICD is a predefined data format. For example, the serial bus data ICD includes a packet header, frame count, packet length, data, and a "checksum".

[0030] The data autonomous parsing state machine (FSM) is connected to the bus interface module, which is connected to an external processor via a parallel bus. The processor can read the data parsed and stored by the data autonomous parsing state machine through the bus interface module.

[0031] The UART protocol IP core connects to the bus transceiver via a unidirectional serial data line and is used to convert data from serial to parallel according to the frame format of the serial bus.

[0032] The autonomous data parsing state machine periodically queries the status information of the UART protocol IP core, controls the autonomous data parsing state machine to switch states, parses data according to the bus data ICD, and stores the parsed data for the processor to read.

[0033] As a specific implementation provided in this case, the bus interface module includes a ready signal for indicating whether the autonomous data parsing process is complete, wherein...

[0034] The ready signal is set by the data autonomous parsing state machine. When the ready signal is set to "1", it indicates that the data autonomous parsing process has been completed.

[0035] The ready signal is reset by the processor via the parallel bus. When ready is set to 0, it indicates that the processor has read the parsed data.

[0036] As a specific implementation method provided in this case, the period for the data autonomous parsing state machine to query the UART protocol IP core status information is determined based on the serial bus communication baud rate.

[0037] When the serial bus communication baud rate is 115200bps, the polling period is less than 8.68us.

[0038] Secondly, a method for operating a serial bus data autonomous parsing controller is provided. Applied to the aforementioned serial bus data parsing controller, the data autonomous parsing state machine is configured with a temporary data storage area. The data autonomous parsing state machine includes six states: idle0, step1, step2, step3, step4, and step5. The bus interface module also includes a fixed data storage area. Its operating method includes…

[0039] Step 0: The data autonomous parsing state machine periodically obtains the status information of the UART protocol IP core. If the status information shows that there is no data in the IP core receive buffer, then it continues to stay in Idle0; if the status information shows that there is data in the IP core receive buffer, then the data is read out, and it is determined whether the data is equal to 8'hAA (8-bit hexadecimal representation). If yes, then jump to Step 1; if no, then continue to stay in Idle0.

[0040] Step 1: The data autonomous parsing state machine periodically obtains the status information of the UART protocol IP core. If the status information shows that there is no data in the IP core receive buffer, then continue to Step 1. If the status information shows that there is data in the IP core receive buffer, then read out the data and determine whether the data is equal to 8'h55 (8-bit decimal representation). If yes, then jump to Step 2; otherwise, jump to Idle0.

[0041] Step 2: The data autonomous parsing state machine periodically obtains the status information of the UART protocol IP core. If the status information shows that there is no data in the IP core receive buffer, then continue to Step 2. If the status information shows that there is data in the IP core receive buffer, then read out the data, assign it to the frame counter, and jump to Step 3.

[0042] Step 3: The data autonomous parsing state machine periodically obtains the status information of the UART protocol IP core. If the status information shows that there is no data in the IP core receive buffer, then continue to Step 3; if the status information shows that there is data in the IP core receive buffer, then read out the data, assign it to the packet length and the local variable len, and jump to Step 4.

[0043] Step 4: The data autonomous parsing state machine periodically obtains the status information of the UART protocol IP core. If the status information shows that there is no data in the IP core receive buffer, then continue to Step 4. If the status information shows that there is data in the IP core receive buffer, then read the data and store it in the temporary data storage area. At the same time, the local variable len is decremented by 1, and it is determined whether the decremented len is equal to 0. If yes, then jump to Step 5. If no, then continue to Step 4. At this time, a complete data packet has not yet been read.

[0044] Step 5: The data autonomous parsing state machine periodically obtains the status information of the UART protocol IP core. If the status information shows that there is no data in the IP core receive buffer, then it continues to Step 5; if the status information shows that there is data in the IP core receive buffer, then it reads out the data, assigns it to the checksum, transfers the data in the temporary data storage area to the fixed data storage area, and jumps to Idle0. Then one data parsing process is completed. This process is repeated to complete the parsing of multiple data packets, thereby releasing the processor's time margin.

[0045] Based on the UART protocol IP core, a data autonomous parsing state machine was designed according to the serial bus data ICD. The serial bus data autonomous parsing controller controls the data autonomous parsing state machine to switch between six states by periodically querying the status register and data register of the UART protocol IP core. Furthermore, it parses serial data according to the bus data ICD and stores it in a designated space for the processor to read. This invention addresses the problem of high time overhead in processor serial data parsing by designing a serial bus data autonomous parsing controller based on a programmable logic device and designing a data autonomous parsing state machine based on the bus data ICD. This achieves autonomous parsing of serial data, reducing the time overhead of the processor in serial data parsing, significantly improving processor efficiency, and can be widely applied in industrial fields.

[0046] Furthermore, in Step 5, the data in the temporary data storage area is transferred to the fixed data storage area. This includes: the data autonomous parsing state machine reads the ready signal of the bus interface module. If the ready signal is equal to 0, the data autonomous parsing state machine sequentially transfers the packet header, frame count, packet length, data stored in the temporary data storage area, and checksum to the fixed data storage area according to the bus data ICD, and sets the ready signal to 1. Once the data parsing is completed, it indicates that the processor can read the data packet.

[0047] Based on the UART protocol IP core, this invention designs a serial bus data autonomous parsing controller using a programmable logic device, and designs a data autonomous parsing state machine based on the bus data ICD. By periodically polling the UART protocol IP core, the switching of the data autonomous parsing state machine is controlled, realizing the autonomous parsing of serial data, reducing the time overhead of the processor in serial data parsing, and significantly improving the processor's efficiency.

[0048] Example 1

[0049] like Figure 1The serial bus data autonomous parsing controller shown is implemented based on a programmable logic device (PLC). Specifically, it includes a data autonomous parsing state machine and a UART protocol IP core. The data autonomous parsing state machine parses and stores data based on the serial bus data ICD. The state machine is connected to a bus interface module, which is connected to a processor via a parallel bus. The processor reads the parsed and stored data from the state machine through the bus interface module. The state machine is also connected to the UART protocol IP core. The UART protocol IP core is connected to a bus transceiver via two unidirectional serial data lines. Its function is to perform serial-to-parallel data conversion according to the serial bus frame format. The data autonomous parsing state machine periodically queries the UART protocol IP core's status information, controls the state machine to switch states, parses serial data based on the bus data ICD, and stores the parsed data for the processor to read.

[0050] Preferably, such as Figure 2 As shown, the serial bus data ICD includes a packet header, frame count, packet length, data, and checksum;

[0051] Preferably, the bus interface module further includes a ready signal, which is set by the data autonomous parsing state machine. When ready is set to 1, it indicates that the data autonomous parsing process has been completed. The ready signal is reset by the processor through the parallel bus. When ready is set to 0, it indicates that the processor has read the parsed data.

[0052] Preferably, the period for the data autonomous parsing state machine to query the UART protocol IP core status information should be determined based on the serial bus communication baud rate. When the serial bus communication baud rate is 115200bps, the query period should be less than 8.68us.

[0053] Preferably, the data autonomous parsing state machine includes 6 states: idl0e, step1, step2, step3, step4, and step5.

[0054] like Figure 3 As shown, in a second aspect, a serial bus data autonomous parsing method is provided, applied in a serial bus data parsing controller, characterized by specifically including the following states:

[0055] Idle0: Periodically retrieve the status information of the UART protocol IP core. If the status information shows that there is no data in the IP core receive buffer, continue to stay in Idle0; if the status information shows that there is data in the IP core receive buffer, read out the data and determine whether the data is equal to 8'hAA. If it is, jump to Step1; otherwise, continue to stay in Idle0.

[0056] Step 1: Periodically obtain the status information of the UART protocol IP core. If the status information shows that there is no data in the IP core receive buffer, continue to Step 1; if the status information shows that there is data in the IP core receive buffer, read out the data and determine whether the data is equal to 8'h55. If it is, jump to Step 2; otherwise, jump to Idle0.

[0057] Step 2: Periodically obtain the status information of the UART protocol IP core. If the status information shows that there is no data in the IP core receive buffer, continue to Step 2; if the status information shows that there is data in the IP core receive buffer, read out the data, assign it to the frame count, and jump to Step 3.

[0058] Step 3: Periodically obtain the status information of the UART protocol IP core. If the status information shows that there is no data in the IP core receive buffer, continue to Step 3; if the status information shows that there is data in the IP core receive buffer, read out the data, assign it to the packet length and the local variable len, and jump to Step 4.

[0059] Step 4: Periodically obtain the status information of the UART protocol IP core. If the status information shows that there is no data in the IP core receive buffer, continue to Step 4; if the status information shows that there is data in the IP core receive buffer, read the data and store it in the temporary data buffer. At the same time, decrement the local variable len by 1 and check whether the decremented len is equal to 0. If len is equal to 0, jump to Step 5; otherwise, continue to Step 4.

[0060] Step 5: Periodically obtain the status information of the UART protocol IP core. If the status information shows that there is no data in the IP core receive buffer, continue to Step 5; if the status information shows that there is data in the IP core receive buffer, read out the data, assign it to the checksum, store the bus data packet, and jump to Idle0.

[0061] Preferably, in Step 5, storing the bus data packet refers to the data autonomous parsing state machine reading the ready signal of the bus interface module. If the ready signal is equal to 0, the packet header, frame count, packet length, data, and checksum are stored in the designated storage space of the bus interface module in sequence according to the bus data ICD, and the ready signal is set to 1.

[0062] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A serial bus data autonomous parsing controller, characterized in that, The serial bus data autonomous parsing controller is implemented based on a programmable logic device (PLD). It includes a data autonomous parsing state machine and a UART protocol IP core that communicates with the data autonomous parsing state machine. The PLD includes a bus interface module. The data autonomous parsing state machine parses and stores data based on serial bus data ICD; The data autonomous parsing state machine (FSM) is connected to a bus interface module, which is connected to an external processor via a parallel bus. The processor can read the data parsed and stored by the data autonomous parsing state machine through the bus interface module. The UART protocol IP core is connected to the bus transceiver via a unidirectional serial data line and is used to convert data from serial to parallel according to the frame format of the serial bus. The data autonomous parsing state machine periodically queries the status information of the UART protocol IP core, controls the data autonomous parsing state machine to switch states, parses data according to the bus data ICD, and stores the parsed data for the processor to read.

2. The serial bus data autonomous parsing controller according to claim 1, characterized in that, The serial bus data ICD includes a packet header, frame count, packet length, data, and checksum.

3. The serial bus data autonomous parsing controller according to claim 1, characterized in that, The bus interface module includes a ready signal to indicate whether the autonomous data parsing process is complete. The ready signal is set by the data autonomous parsing state machine. When the ready signal is set to "1", it indicates that the data autonomous parsing process has been completed. The ready signal is reset by the processor via the parallel bus. When ready is set to 0, it indicates that the processor has read the parsed data.

4. The serial bus data autonomous parsing controller according to claim 1, characterized in that, The period for the data autonomous parsing state machine to query the UART protocol IP core status information is determined based on the serial bus communication baud rate. When the serial bus communication baud rate is 115200bps, the polling period is less than 8.68us.

5. A method for operating a serial bus data autonomous parsing controller, applied in the serial bus data parsing controller as described in any one of claims 1 to 4, wherein the data autonomous parsing state machine is configured with a temporary data storage area, characterized in that, The data autonomous parsing state machine includes six states: idle0, step1, step2, step3, step4, and step5. The bus interface module also includes a fixed data storage area. The working method includes... Step 0: The data autonomous parsing state machine periodically obtains the status information of the UART protocol IP core. If the status information shows that there is no data in the IP core receive buffer, then it continues to stay in Idle0; if the status information shows that there is data in the IP core receive buffer, then the data is read out and it is determined whether the data is equal to 8'hAA. If yes, then it jumps to Step 1; if no, it continues to stay in Idle0. Step 1: The data autonomous parsing state machine periodically obtains the status information of the UART protocol IP core. If the status information shows that there is no data in the IP core receive buffer, then continue to Step 1. If the status information shows that there is data in the IP core receive buffer, then read out the data and determine whether the data is equal to 8'h55. If yes, then jump to Step 2. If no, then jump to Idle0. Step 2: The data autonomous parsing state machine periodically obtains the status information of the UART protocol IP core. If the status information shows that there is no data in the IP core receive buffer, then continue to Step 2. If the status information shows that there is data in the IP core receive buffer, then read out the data, assign it to the frame count, and jump to Step 3. Step 3: The data autonomous parsing state machine periodically obtains the status information of the UART protocol IP core. If the status information shows that there is no data in the IP core receive buffer, then continue to Step 3; if the status information shows that there is data in the IP core receive buffer, then read out the data, assign it to the packet length and the local variable len, and jump to Step 4. Step 4: The data autonomous parsing state machine periodically obtains the status information of the UART protocol IP core. If the status information shows that there is no data in the IP core receive buffer, then continue to Step 4. If the status information shows that there is data in the IP core receive buffer, then read out the data and store it in the temporary data storage area. At the same time, the local variable len is decremented by 1, and it is determined whether the decremented len is equal to 0. If yes, then jump to Step 5; otherwise, continue to Step 4. Step 5: The data autonomous parsing state machine periodically obtains the status information of the UART protocol IP core. If the status information shows that there is no data in the IP core receive buffer, then continue to Step 5; if the status information shows that there is data in the IP core receive buffer, then read out the data, assign it to the checksum, transfer the data in the temporary data storage area to the fixed data storage area, and jump to Idle0.

6. The working method according to claim 5, characterized in that, The transfer of data from the temporary data storage area to the fixed data storage area in Step 5 includes: The data autonomous parsing state machine reads the ready signal from the bus interface module. If the ready signal is equal to 0, the data autonomous parsing state machine sequentially transfers the packet header, frame count, packet length, data stored in the temporary data storage area, and checksum to the fixed data storage area according to the bus data ICD, and sets the ready signal to 1.

Images