A CMOS voltage reference source using a self-cancellation technique of a mismatch voltage

Abstract

The application discloses a CMOS voltage reference source adopting a self-elimination technology of a disordered voltage, comprising a bias circuit, an operational amplifier circuit and a zero-temperature coefficient bias circuit; the bias circuit adopts a 1uA current source to provide a bias voltage for a subsequent circuit, so that the subsequent circuit can normally work under a power supply voltage of 0.65V to 2.5V; the operational amplifier circuit locks the output voltage of the zero-temperature coefficient bias through a two-stage folded common-source common-gate operational amplifier; and the zero-temperature coefficient bias circuit realizes working at a zero-temperature coefficient point by adjusting the bias point of MN25, and realizes the output of the voltage reference source. The CMOS voltage reference source can work in a wide voltage range and is not affected by the disordered voltage of the operational amplifier.

Description

Technical Field

[0001] This invention pertains to voltage reference circuits, specifically to a CMOS voltage reference source employing offset voltage self-cancellation technology. By applying this self-cancellation offset voltage technology, the CMOS voltage reference source can operate over a wide voltage range, unaffected by operational amplifier offset voltage. Background Technology

[0002] In voltage reference circuits, operational amplifiers are widely used components. Because the output voltage of the reference source requires extremely high circuit accuracy, the offset voltage of the operational amplifier has a significant impact on the reference output. The offset voltage of the operational amplifier arises from its own non-ideal factors, causing the positive and negative input terminals to not maintain the same voltage when operating in the loop, resulting in a certain difference. Furthermore, since the gain and other characteristics of the operational amplifier fluctuate with temperature, this difference changes with temperature, and this change is also added to the output reference source, affecting the temperature coefficient of the voltage reference output. Therefore, to further reduce the temperature coefficient of the output voltage in voltage reference circuits, additional sampling techniques, self-zeroing techniques, or chopping techniques are generally used to eliminate the influence of the operational amplifier offset voltage on the output voltage.

[0003] Meanwhile, in advanced CMOS processes, such as 65nm, the operating voltage of MOS transistors is only 1.2V, with a typical voltage tolerance range of 10%, or 1.32V. However, the overall voltage reference circuit is difficult to operate under ambient voltages above 2.5V. This paper employs MOS transistor stacking technology, using only 1.2V standard voltage CMOS transistors, further improving the operating voltage range of the voltage reference to 0.65V to 2.5V. Summary of the Invention

[0004] Technical problem solved: This invention discloses a CMOS voltage reference source using offset voltage self-elimination technology. By employing stacking technology and offset voltage self-elimination technology, a CMOS voltage reference source circuit is realized that can operate in an environment of 0.65V to 2.5V and is not affected by the offset voltage of the operational amplifier.

[0005] Technical solution:

[0006] A CMOS voltage reference source employing offset voltage self-cancellation technology, the CMOS voltage reference source comprising a bias circuit, an operational amplifier circuit, and a zero temperature coefficient bias circuit;

[0007] The bias circuit includes NMOS transistors MN1 to MN11, PMOS transistors MP1 and MP2, and a current source. The source and substrate of NMOS transistors MN1 and MN2 are grounded. The gate and drain of NMOS transistor MN1 and the gate of NMOS transistor MN2 are connected to one end of the current source, and the other end of the current source is connected to the power supply voltage terminal. The drain of NMOS transistor MN2 is connected to the source and substrate of NMOS transistor MN10. The gate and drain of NMOS transistors MN3, MN4, MN5, and MN6 are shorted. The source of NMOS transistor MN4 is connected in series with the gate of NMOS transistor MN3, the source of NMOS transistor MN5 is connected in series with the gate of NMOS transistor MN4, and the source of NMOS transistor MN6 is connected in series with the gate of NMOS transistor MN5. The bias circuit also includes NMOS transistors MN4, MN5, and MP2. The substrate of N6 is grounded; the source of NMOS transistor MN3 is connected to the substrate and grounded; the source and substrate of NMOS transistor MN7 are connected to the drain of NMOS transistor MN6, and the gate and drain are connected to the gate of NMOS transistor MN10; the source and substrate of NMOS transistor MN8 are connected to the drain of NMOS transistor MN7, and the gate and drain of NMOS transistor MN8 are connected to the substrate and source of NMOS transistor MN9; the gate and drain of NMOS transistor MN9 are connected to the drain of PMOS transistor MP2; the drain of NMOS transistor MN10 is connected to the source and substrate of NMOS transistor MN11; the gate of NMOS transistor MN11 is connected to the drain of NMOS transistor MN9; the gate and drain of PMOS transistor MP1 are connected to the drain of NMOS transistor MN11, the source and substrate of PMOS transistor MP1 are connected to the power supply voltage, the gate of PMOS transistor MP2 is connected to the drain of PMOS transistor MP1, and the source and substrate of PMOS transistor MP2 are connected to the power supply voltage.

[0008] The operational amplifier circuit includes NMOS transistors MN12 to MN24 and PMOS transistors MP3 to MP18. The source and substrate of NMOS transistor MN12 are grounded, its gate is connected to the drain of NMOS transistor MN1, and its drain is connected to the source of NMOS transistors MN13 and MN14. The gate of NMOS transistor MN13 is connected to the first end of a second resistor RDS, the gate of NMOS transistor MN14 is connected to the first end of a first resistor RGS, the drain of NMOS transistor MN13 is connected to the source and substrate of NMOS transistor MN15 and the drain of PMOS transistor MP3, and the drain of NMOS transistor MN14 is connected to NMOS transistor MN1. The source and substrate of transistor 6 are connected to the drain of PMOS transistor MP4; the gates of NMOS transistors MN15 and MN16 are connected to the drain of NMOS transistor MN7; the drain of NMOS transistor MN15 is connected to the source and substrate of PMOS transistor MP3, the drain of PMOS transistor MP9, and the source and substrate of PMOS transistor MP7; the drain of NMOS transistor MN16 is connected to the source and substrate of PMOS transistor MP4, the drain of PMOS transistor MP10, and the source and substrate of PMOS transistor MP8; the substrate and source of PMOS transistors MP9 and MP10 are connected to the power supply voltage; the gates of PMOS transistors MP9 and MP10 are connected to PMOS transistor MP1. The drain of PMOS transistors MP7 and MP8 is connected to the drain of PMOS transistor MP14; the drain of PMOS transistor MP7 is connected to the source and substrate of PMOS transistor MP5; the drain of PMOS transistor MP8 is connected to the source and substrate of PMOS transistor MP6; the gate of PMOS transistors MP5 and MP6 is connected to the drain of PMOS transistor MP11; the drain of PMOS transistor MP5 is connected to the drain of NMOS transistor MN19; the drain of PMOS transistor MP6 is connected to the drain of NMOS transistor MN20; the gate of NMOS transistors MN19 and MN20 is connected to the gate of NMOS transistor MN5; the source of NMOS transistor MN19 is connected to the NMOS transistor MN20. The drain of transistor MN17 and the source of NMOS transistor MN20 are connected to the drain of NMOS transistor MN18; the gates of NMOS transistors MN17 and MN18 are connected to the drain of NMOS transistor MN19; the sources of NMOS transistors MN17 and MN18 and the substrate are grounded; the gates and drains of PMOS transistors MP14, MP15, MP16, and MP17 are shorted, and the source of PMOS transistor MP14 and the gate of PMOS transistor MP15 are connected in series, the source of PMOS transistor MP15 and the gate of PMOS transistor MP16 are connected in series, and the source of PMOS transistor MP16 and the gate of PMOS transistor MP17 are connected in series.The substrate and source of PMOS transistor MP13 are connected to the drain of PMOS transistor MP14; the substrate and source of PMOS transistor MP12 are connected to the gate and drain of PMOS transistor MP13; and the substrate and source of PMOS transistor MP11 are connected to the gate and drain of PMOS transistor MP12. The substrate and source of NMOS transistor MN21 are grounded; the drain of NMOS transistor MN21 is connected to the gate and drain of PMOS transistor MP11; the gate of NMOS transistor MN21 is connected to the drain of NMOS transistor MN1; the gate of NMOS transistor MN22 is connected to the drain of NMOS transistor MN20; the source and substrate of NMOS transistor MN22 are grounded; and the drain of NMOS transistor MN22 is connected to NMOS transistor MN23. The substrate and source of NMOS transistor MN23 are connected to the drain of NMOS transistor MN7. The drain of NMOS transistor MN23 is connected to the substrate and source of NMOS transistor MN24. The gate of NMOS transistor MN24 is connected to the drain of NMOS transistor MN9. The drain of NMOS transistor MN24 is connected to the drain of PMOS transistor MP18. The gate of PMOS transistor MP18 is connected to the drain of PMOS transistor MP1. The source and substrate of PMOS transistor MP18 are connected to the power supply voltage. The substrates of NMOS transistors MN13, MN14, MN19, and MN20 are grounded. The source and substrate of PMOS transistor MP17 are connected to the power supply voltage terminal.

[0009] The zero-temperature coefficient bias circuit includes an NMOS transistor MN25, PMOS transistors MP19 to MP24, a first resistor RGS, and a second resistor RDS. The source and substrate of PMOS transistors MP19 and MP20 are connected to the power supply voltage, and their gates are connected to the drain of PMOS transistor MP18. The drain of PMOS transistor MP19 is connected to the source and substrate of PMOS transistor MP21, and the drain of PMOS transistor MP20 is connected to the source and substrate of PMOS transistor MP22. The gates of PMOS transistors MP21 and MP22 are connected to the drain of PMOS transistor MP13, and the gate of PMOS transistor MP24 is connected to the drain of PMOS transistor MP25. The drain of PMOS transistor MP11 is connected to the source of PMOS transistor MP23 and the substrate. The drain of PMOS transistor MP22 is connected to the source of PMOS transistor MP24 and the substrate. The gates of PMOS transistors MP23 and MP24 are connected to the drain of PMOS transistor MP11. The drain of PMOS transistor MP23 is connected to the first end of the first resistor RGS, and the second end of the first resistor RGS is grounded. The drain of PMOS transistor MP24 is connected to the first end of the second resistor RDS and the gate of NMOS transistor MN25. The second end of the second resistor RDS is connected to the drain of NMOS transistor MN25, and the source of NMOS transistor MN25 and the substrate are grounded.

[0010] Furthermore, the bias circuit uses a 1uA current source.

[0011] Furthermore, the CMOS voltage reference source is fabricated using a 65nm CMOS process.

[0012] Furthermore, both the first resistor RGS and the second resistor RDS include five resistor units connected in sequence, with four resistor units each connected in parallel with a switch.

[0013] The CMOS voltage reference source includes a trimming circuit. The output of the trimming circuit is connected to four switches. By controlling the opening and closing states of the switches, the resistance values ​​of the first resistor RGS and the second resistor RDS are trimmed in four positions.

[0014] Furthermore, the offset voltage of the operational amplifier For output voltage The influence formula is:

[0015] ;

[0016] in, R is the drain current of the NMOS transistor MN25, and R is the resistance of the first resistor RGS.

[0017] Beneficial effects:

[0018] First, the CMOS voltage reference source of the present invention, which employs offset voltage self-elimination technology, proposes a stacking technology to enable a transistor with a standard voltage of 1.2V using a 65nm process to operate in a power supply voltage environment ranging from 0.65V to 2.5V.

[0019] Second, the CMOS voltage reference source of the present invention, which employs offset voltage self-elimination technology, explores the influence of operational amplifier offset voltage on reference output in a zero temperature coefficient voltage reference source, and realizes a voltage reference source unaffected by offset voltage through reasonable biasing.

[0020] Third, the CMOS voltage reference source of the present invention, which adopts offset voltage self-elimination technology, uses a resistor adjustment structure to effectively reduce the impact of process, voltage and temperature deviations on the output voltage. Attached Figure Description

[0021] Figure 1 This invention discloses a circuit structure diagram of a CMOS voltage reference source employing offset voltage self-elimination technology, wherein the green dashed rectangle contains an additional chopping technology structure to reduce offset voltage.

[0022] Figure 2 This is a schematic diagram of the Candence simulation structure, where (a) is the operational amplifier offset voltage variation with temperature under different power supply voltages, and (b) is the operational amplifier offset voltage variation with temperature under different process angles.

[0023] Figure 3The diagram shows the offset voltage elimination structure and results. (a) is a schematic diagram of the offset voltage adaptive elimination technology, (b) is a schematic diagram of the offset voltage elimination using chopping technology, and (c) is a schematic diagram of the MN25 bias and output under different offset voltages.

[0024] Figure 4 This is a schematic diagram of the 4-bit adjustment array structure of the RDS and RGS resistors used in the proposed voltage reference source.

[0025] Figure 5 These are simulation diagrams of the output reference voltage temperature coefficient. (a) is the output reference voltage temperature coefficient simulation diagram of the TT process corner using chopping temperature coefficient (low offset) and self-cancellation technology under different power supply voltages (1V, 1.8V, 2.5V). (b) is the output reference voltage temperature coefficient simulation diagram of the FF process corner using chopping temperature coefficient (low offset) and self-cancellation technology under different power supply voltages (1V, 1.8V, 2.5V). (c) is the output reference voltage temperature coefficient simulation diagram of the SS process corner using chopping temperature coefficient (low offset) and self-cancellation technology under different power supply voltages (1V, 1.8V, 2.5V). Detailed Implementation

[0026] The following embodiments are provided to enable those skilled in the art to more fully understand the present invention, but do not limit the invention in any way.

[0027] This invention discloses a CMOS voltage reference source employing offset voltage self-elimination technology, wherein the CMOS voltage reference source includes a bias circuit, an operational amplifier circuit, and a zero temperature coefficient bias circuit;

[0028] The bias circuit includes NMOS transistors MN1 to MN11, PMOS transistors MP1 and MP2, and a current source. The source and substrate of NMOS transistors MN1 and MN2 are grounded. The gate and drain of NMOS transistor MN1 and the gate of NMOS transistor MN2 are connected to one end of the current source, and the other end of the current source is connected to the power supply voltage terminal. The drain of NMOS transistor MN2 is connected to the source and substrate of NMOS transistor MN10. The gate and drain of NMOS transistors MN3, MN4, MN5, and MN6 are shorted. The source of NMOS transistor MN4 is connected in series with the gate of NMOS transistor MN3, the source of NMOS transistor MN5 is connected in series with the gate of NMOS transistor MN4, and the source of NMOS transistor MN6 is connected in series with the gate of NMOS transistor MN5. The substrates of NMOS transistors MN4, MN5, and MN6 are grounded. The source of NMOS transistor MN3 is connected to the substrate and grounded. The source and substrate of NMOS transistor MN7 are connected to the drain of NMOS transistor MN6, and its gate and drain are connected to the gate of NMOS transistor MN10; the source and substrate of NMOS transistor MN8 are connected to the drain of NMOS transistor MN7, and the gate and drain of NMOS transistor MN8 are connected to the substrate and source of NMOS transistor MN9; the gate and drain of NMOS transistor MN9 are connected to the drain of PMOS transistor MP2; the drain of NMOS transistor MN10 is connected to the source and substrate of NMOS transistor MN11; NMOS transistor MN1... The gate of transistor 1 is connected to the drain of NMOS transistor MN9; the gate and drain of PMOS transistor MP1 are connected to the drain of NMOS transistor MN11, the source and substrate of PMOS transistor MP1 are connected to the power supply voltage, the gate of PMOS transistor MP2 is connected to the drain of PMOS transistor MP1, and the source and substrate of PMOS transistor MP2 are connected to the power supply voltage; the bias circuit uses a 1uA current source and the above transistors to provide bias voltage to the subsequent circuits so that it can operate normally under a power supply voltage of 0.65V to 2.5V.

[0029] The operational amplifier circuit includes NMOS transistors MN12 to MN24 and PMOS transistors MP3 to MP18. The source and substrate of NMOS transistor MN12 are grounded, its gate is connected to the drain of NMOS transistor MN1, and its drain is connected to the source of NMOS transistors MN13 and MN14. The gate of NMOS transistor MN13 is connected to the first end of a second resistor RDS, the gate of NMOS transistor MN14 is connected to the first end of a first resistor RGS, the drain of NMOS transistor MN13 is connected to the source and substrate of NMOS transistor MN15 and the drain of PMOS transistor MP3, and the drain of NMOS transistor MN14 is connected to NMOS transistor MN1. The source and substrate of transistor 6 are connected to the drain of PMOS transistor MP4; the gates of NMOS transistors MN15 and MN16 are connected to the drain of NMOS transistor MN7; the drain of NMOS transistor MN15 is connected to the source and substrate of PMOS transistor MP3, the drain of PMOS transistor MP9, and the source and substrate of PMOS transistor MP7; the drain of NMOS transistor MN16 is connected to the source and substrate of PMOS transistor MP4, the drain of PMOS transistor MP10, and the source and substrate of PMOS transistor MP8; the substrate and source of PMOS transistors MP9 and MP10 are connected to the power supply voltage; the gates of PMOS transistors MP9 and MP10 are connected to PMOS transistor MP1. The drain of PMOS transistors MP7 and MP8 is connected to the drain of PMOS transistor MP14; the drain of PMOS transistor MP7 is connected to the source and substrate of PMOS transistor MP5; the drain of PMOS transistor MP8 is connected to the source and substrate of PMOS transistor MP6; the gate of PMOS transistors MP5 and MP6 is connected to the drain of PMOS transistor MP11; the drain of PMOS transistor MP5 is connected to the drain of NMOS transistor MN19; the drain of PMOS transistor MP6 is connected to the drain of NMOS transistor MN20; the gate of NMOS transistors MN19 and MN20 is connected to the gate of NMOS transistor MN5; the source of NMOS transistor MN19 is connected to the NMOS transistor MN20. The drain of transistor MN17 and the source of NMOS transistor MN20 are connected to the drain of NMOS transistor MN18; the gates of NMOS transistors MN17 and MN18 are connected to the drain of NMOS transistor MN19; the sources of NMOS transistors MN17 and MN18 and the substrate are grounded; the gates and drains of PMOS transistors MP14, MP15, MP16, and MP17 are shorted, and the source of PMOS transistor MP14 and the gate of PMOS transistor MP15 are connected in series, the source of PMOS transistor MP15 and the gate of PMOS transistor MP16 are connected in series, and the source of PMOS transistor MP16 and the gate of PMOS transistor MP17 are connected in series.The substrate and source of PMOS transistor MP13 are connected to the drain of PMOS transistor MP14; the substrate and source of PMOS transistor MP12 are connected to the gate and drain of PMOS transistor MP13; the substrate and source of PMOS transistor MP11 are connected to the gate and drain of PMOS transistor MP12; the substrate and source of NMOS transistor MN21 are grounded; the drain of NMOS transistor MN21 is connected to the gate and drain of PMOS transistor MP11; the gate of NMOS transistor MN21 is connected to the drain of NMOS transistor MN1; the gate of NMOS transistor MN22 is connected to the drain of NMOS transistor MN20; the source and substrate of NMOS transistor MN22 are grounded; the drain of NMOS transistor MN22 is connected to the substrate and source of NMOS transistor MN23; and the gate of NMOS transistor MN23... The drain of NMOS transistor MN7 is connected to the drain of NMOS transistor MN23, which is connected to the substrate and source of NMOS transistor MN24. The gate of NMOS transistor MN24 is connected to the drain of NMOS transistor MN9, and the drain of NMOS transistor MN24 is connected to the drain of PMOS transistor MP18. The gate of PMOS transistor MP18 is connected to the drain of PMOS transistor MP1, and the source and substrate of PMOS transistor MP18 are connected to the power supply voltage. The substrates of NMOS transistors MN13, MN14, MN19, and MN20 are grounded. The source and substrate of PMOS transistor MP17 are connected to the power supply voltage. The operational amplifier circuit uses a two-stage folded cascode operational amplifier to lock its output voltage with zero temperature coefficient bias.

[0030] The zero-temperature coefficient bias circuit includes an NMOS transistor MN25, PMOS transistors MP19 to MP24, a first resistor RGS, and a second resistor RDS. The source and substrate of PMOS transistors MP19 and MP20 are connected to the power supply voltage, and their gates are connected to the drain of PMOS transistor MP18. The drain of PMOS transistor MP19 is connected to the source and substrate of PMOS transistor MP21, and the drain of PMOS transistor MP20 is connected to the source and substrate of PMOS transistor MP22. The gates of PMOS transistors MP21 and MP22 are connected to the drain of PMOS transistor MP13, and the gate of PMOS transistor MP24 is connected to the drain of PMOS transistor MP25. The drain of PMOS transistor MP11 is connected to the source of PMOS transistor MP23 and the substrate; the drain of PMOS transistor MP22 is connected to the source of PMOS transistor MP24 and the substrate; the gates of PMOS transistors MP23 and MP24 are connected to the drain of PMOS transistor MP11; the drain of PMOS transistor MP23 is connected to the first end of the first resistor RGS, and the second end of the first resistor RGS is grounded; the drain of PMOS transistor MP24 is connected to the first end of the second resistor RDS and the gate of NMOS transistor MN25; the second end of the second resistor RDS is connected to the drain of NMOS transistor MN25; the source of NMOS transistor MN25 and the substrate are grounded. The zero-temperature coefficient bias circuit achieves its operation at the zero-temperature coefficient point by adjusting the bias point of NMOS transistor MN25, thus realizing the output of the voltage reference source.

[0031] Figure 1 This diagram illustrates the structure of the CMOS voltage reference source employing offset voltage self-elimination technology proposed in this invention. It also shows the additional chopping technology used to reduce offset voltage within the green dashed rectangle (chopper 1 connects to the drains of MP9 and MP10 and the sources of MP7 and MP8; chopper 2 connects to the drains of MP5 and MP6 and the drains of MN19 and MN20; chopper 3 connects to the drains of MP23 and MP24 and the gates of MN13 and MN14). A comparison is made between the chopping technology and the adaptive offset voltage elimination structure. The use of diode connections for NMOS and PMOS transistors enables normal operation over a wide input voltage range, ensuring that each transistor operates within the specified voltage of 1.2V. The diagram also shows the voltage division of each transistor at 0.65V and 2.5V in the critical path, indicating that the maximum bias voltage is only 0.95V. This demonstrates that it can operate at a 2.5V supply voltage.

[0032] Figure 2 The diagram shows the simulation results from Candence. (a) shows the operational amplifier offset voltage versus temperature under different power supply voltages, and (b) shows the operational amplifier offset voltage versus temperature under different process corners. The effect of the operational amplifier offset voltage on the output is shown in the following equation:

[0033] ;

[0034] in R is the drain current of the NMOS transistor MN25, and R is the resistance of the first resistor RGS. Therefore, if normal bias is used, the offset voltage will have a great influence on the temperature coefficient of the output voltage under different input voltages and different process angles, and may increase the temperature coefficient of the output reference by up to 15ppm / ℃.

[0035] Figure 3 This diagram illustrates the principle and results of offset voltage elimination. (a) shows the adaptive offset voltage elimination technique; (b) shows the offset voltage elimination using chopping technology; and (c) shows the MN25 bias under different offset voltages and the output voltage of the voltage reference source. By employing appropriate biasing, the impact of operational amplifier offset voltage on the output can be effectively reduced. The output of this method is compared with that of traditional chopping technology, both achieving low temperature coefficients, demonstrating that this voltage reference source has excellent operational amplifier offset voltage suppression performance.

[0036] Figure 4This is a schematic diagram of the 4-bit adjustment array structure for the RDS and RGS resistors used in the proposed voltage reference source. Because the threshold voltage of MN25 varies significantly depending on the circuit manufacturing process, an adjustment circuit is used to adjust the 4-bit resistance value of the MN25 bias resistor. Simultaneously, the temperature curve of the offset voltage's influence on the output also differs slightly under different power supply voltages, requiring additional adjustment of the MN25 drain-source voltage to reduce the impact of the operational amplifier offset voltage on the output under different operating voltages. Specifically, the operation is as follows: By setting the enable pin to 1, a 4-bit adjustment is performed on RGS to reduce its temperature coefficient. Then, the enable pin is set to 0, locking the adjustment bits of RGS, and then a 4-bit adjustment is performed on RDS to reduce the impact of the offset voltage. The adjustment is then complete.

[0037] Figure 5 Simulation graphs of the temperature coefficient of output reference voltage using chopping (low offset) and self-cancellation technology at different process angles and power supply voltages (1V, 1.8V, 2.5V) in Cadence are presented. (a) corresponds to the TT process angle, (b) to the FF process angle, and (c) to the SS process angle. Under different process angles and power supply voltages, it can be found that the temperature coefficient achieved by the adaptive offset voltage technology used in this invention is similar to that achieved by chopping. Specific results are shown in Table 1.

[0038] Table 1 Results of angular temperature coefficients for different processes

[0039]

[0040] It can be observed that in most cases, the temperature coefficient of the adaptive offset voltage technology is reduced to a certain extent compared with that of the chopping technology. Only at the FF process corner with a power supply voltage of 1.8V, the chopping technology shows an improvement of 0.1ppm / ℃, proving that the present invention has an effective offset voltage reduction effect.

[0041] The above are merely preferred embodiments of the present invention. The scope of protection of the present invention is not limited to the above embodiments. All technical solutions falling within the scope of the present invention's concept are within the scope of protection of the present invention. It should be noted that for those skilled in the art, any improvements and modifications made without departing from the principles of the present invention should be considered within the scope of protection of the present invention.

Claims

1. A CMOS voltage reference source employing offset voltage self-cancellation technology, characterized in that, The CMOS voltage reference source includes a bias circuit, an operational amplifier circuit, and a zero temperature coefficient bias circuit; The bias circuit includes NMOS transistors MN1 to MN11, PMOS transistors MP1 and MP2, and a current source. The source and substrate of NMOS transistors MN1 and MN2 are grounded. The gate and drain of NMOS transistor MN1 and the gate of NMOS transistor MN2 are connected to one end of the current source, and the other end of the current source is connected to the power supply voltage terminal. The drain of NMOS transistor MN2 is connected to the source and substrate of NMOS transistor MN10. The gate and drain of NMOS transistors MN3, MN4, MN5, and MN6 are shorted. The source of NMOS transistor MN4 is connected in series with the gate of NMOS transistor MN3, the source of NMOS transistor MN5 is connected in series with the gate of NMOS transistor MN4, and the source of NMOS transistor MN6 is connected in series with the gate of NMOS transistor MN5. The bias circuit also includes NMOS transistors MN4, MN5, and MP2. The substrate of N6 is grounded; the source of NMOS transistor MN3 is connected to the substrate and grounded; the source and substrate of NMOS transistor MN7 are connected to the drain of NMOS transistor MN6, and the gate and drain are connected to the gate of NMOS transistor MN10; the source and substrate of NMOS transistor MN8 are connected to the drain of NMOS transistor MN7, and the gate and drain of NMOS transistor MN8 are connected to the substrate and source of NMOS transistor MN9; the gate and drain of NMOS transistor MN9 are connected to the drain of PMOS transistor MP2; the drain of NMOS transistor MN10 is connected to the source and substrate of NMOS transistor MN11; the gate of NMOS transistor MN11 is connected to the drain of NMOS transistor MN9; the gate and drain of PMOS transistor MP1 are connected to the drain of NMOS transistor MN11, the source and substrate of PMOS transistor MP1 are connected to the power supply voltage, the gate of PMOS transistor MP2 is connected to the drain of PMOS transistor MP1, and the source and substrate of PMOS transistor MP2 are connected to the power supply voltage. The operational amplifier circuit includes NMOS transistors MN12 to MN24 and PMOS transistors MP3 to MP18. The source and substrate of NMOS transistor MN12 are grounded, its gate is connected to the drain of NMOS transistor MN1, and its drain is connected to the source of NMOS transistors MN13 and MN14. The gate of NMOS transistor MN13 is connected to the first end of a second resistor RDS, the gate of NMOS transistor MN14 is connected to the first end of a first resistor RGS, the drain of NMOS transistor MN13 is connected to the source and substrate of NMOS transistor MN15 and the drain of PMOS transistor MP3, and the drain of NMOS transistor MN14 is connected to NMOS transistor MN1. The source and substrate of transistor 6 are connected to the drain of PMOS transistor MP4; the gates of NMOS transistors MN15 and MN16 are connected to the drain of NMOS transistor MN7; the drain of NMOS transistor MN15 is connected to the source and substrate of PMOS transistor MP3, the drain of PMOS transistor MP9, and the source and substrate of PMOS transistor MP7; the drain of NMOS transistor MN16 is connected to the source and substrate of PMOS transistor MP4, the drain of PMOS transistor MP10, and the source and substrate of PMOS transistor MP8; the substrate and source of PMOS transistors MP9 and MP10 are connected to the power supply voltage; the gates of PMOS transistors MP9 and MP10 are connected to PMOS transistor MP1. The drain of PMOS transistors MP7 and MP8 is connected to the drain of PMOS transistor MP14; the drain of PMOS transistor MP7 is connected to the source and substrate of PMOS transistor MP5; the drain of PMOS transistor MP8 is connected to the source and substrate of PMOS transistor MP6; the gate of PMOS transistors MP5 and MP6 is connected to the drain of PMOS transistor MP11; the drain of PMOS transistor MP5 is connected to the drain of NMOS transistor MN19; the drain of PMOS transistor MP6 is connected to the drain of NMOS transistor MN20; the gate of NMOS transistors MN19 and MN20 is connected to the gate of NMOS transistor MN5; the source of NMOS transistor MN19 is connected to the NMOS transistor MN20. The drain of transistor MN17 and the source of NMOS transistor MN20 are connected to the drain of NMOS transistor MN18; the gates of NMOS transistors MN17 and MN18 are connected to the drain of NMOS transistor MN19; the sources of NMOS transistors MN17 and MN18 and the substrate are grounded; the gates and drains of PMOS transistors MP14, MP15, MP16, and MP17 are shorted, and the source of PMOS transistor MP14 and the gate of PMOS transistor MP15 are connected in series, the source of PMOS transistor MP15 and the gate of PMOS transistor MP16 are connected in series, and the source of PMOS transistor MP16 and the gate of PMOS transistor MP17 are connected in series.The substrate and source of PMOS transistor MP13 are connected to the drain of PMOS transistor MP14; the substrate and source of PMOS transistor MP12 are connected to the gate and drain of PMOS transistor MP13; and the substrate and source of PMOS transistor MP11 are connected to the gate and drain of PMOS transistor MP12. The substrate and source of NMOS transistor MN21 are grounded; the drain of NMOS transistor MN21 is connected to the gate and drain of PMOS transistor MP11; the gate of NMOS transistor MN21 is connected to the drain of NMOS transistor MN1; the gate of NMOS transistor MN22 is connected to the drain of NMOS transistor MN20; the source and substrate of NMOS transistor MN22 are grounded; and the drain of NMOS transistor MN22 is connected to NMOS transistor MN23. The substrate and source of NMOS transistor MN23 are connected to the drain of NMOS transistor MN7. The drain of NMOS transistor MN23 is connected to the substrate and source of NMOS transistor MN24. The gate of NMOS transistor MN24 is connected to the drain of NMOS transistor MN9. The drain of NMOS transistor MN24 is connected to the drain of PMOS transistor MP18. The gate of PMOS transistor MP18 is connected to the drain of PMOS transistor MP1. The source and substrate of PMOS transistor MP18 are connected to the power supply voltage. The substrates of NMOS transistors MN13, MN14, MN19, and MN20 are grounded. The source and substrate of PMOS transistor MP17 are connected to the power supply voltage terminal. The zero-temperature coefficient bias circuit includes an NMOS transistor MN25, PMOS transistors MP19 to MP24, a first resistor RGS, and a second resistor RDS. The source and substrate of PMOS transistors MP19 and MP20 are connected to the power supply voltage, and their gates are connected to the drain of PMOS transistor MP18. The drain of PMOS transistor MP19 is connected to the source and substrate of PMOS transistor MP21, and the drain of PMOS transistor MP20 is connected to the source and substrate of PMOS transistor MP22. The gates of PMOS transistors MP21 and MP22 are connected to the drain of PMOS transistor MP13, and the gate of PMOS transistor MP24 is connected to the drain of PMOS transistor MP25. The drain of PMOS transistor MP11 is connected to the source of PMOS transistor MP23 and the substrate. The drain of PMOS transistor MP22 is connected to the source of PMOS transistor MP24 and the substrate. The gates of PMOS transistors MP23 and MP24 are connected to the drain of PMOS transistor MP11. The drain of PMOS transistor MP23 is connected to the first end of the first resistor RGS, and the second end of the first resistor RGS is grounded. The drain of PMOS transistor MP24 is connected to the first end of the second resistor RDS and the gate of NMOS transistor MN25. The second end of the second resistor RDS is connected to the drain of NMOS transistor MN25, and the source of NMOS transistor MN25 and the substrate are grounded.

2. The CMOS voltage reference source employing offset voltage self-elimination technology according to claim 1, characterized in that, The bias circuit uses a 1uA current source.

3. The CMOS voltage reference source employing offset voltage self-elimination technology according to claim 1, characterized in that, The CMOS voltage reference source was fabricated using a 65nm CMOS process.

4. The CMOS voltage reference source employing offset voltage self-elimination technology according to claim 1, characterized in that, The first resistor RGS and the second resistor RDS each include five resistor units connected in sequence, of which four resistor units are each connected in parallel with a switch. The CMOS voltage reference source includes a trimming circuit. The output of the trimming circuit is connected to four switches. By controlling the opening and closing states of the switches, the resistance values ​​of the first resistor RGS and the second resistor RDS are trimmed in four positions.

5. The CMOS voltage reference source employing offset voltage self-cancellation technology according to claim 1, characterized in that, Offset voltage of operational amplifier For output voltage The influence formula is: ； in, R is the drain current of the NMOS transistor MN25, and R is the resistance of the first resistor RGS.

Images