Latch circuit, dynamic latch, dynamic D flip-flop and related devices

Abstract

The present disclosure relates to latch circuits, dynamic latches, dynamic D flip-flops and related devices. A latch circuit includes: an input terminal; an output terminal; a first transistor having a first conductivity type, whose control terminal is configured to receive a first clock signal; a second transistor having a second conductivity type different from the first conductivity type, whose control terminal is configured to receive a second clock signal that is inverted from the first clock signal; a third transistor, whose control terminal is configured to receive a clock signal that is the same as the clock signal received by the control terminal of a transistor of the same conductivity type as the third transistor in the first and second transistors. The first transmission terminal of the first transistor and the first transmission terminal of the second transistor are commonly connected to the input terminal. The second transmission terminal of the first transistor is connected to the output terminal via the third transistor. The second transmission terminal of the second transistor is connected to the output terminal.

Description

Technical Field

[0001] The present disclosure relates generally to the field of integrated circuit technology, and more particularly to a latch circuit, a dynamic latch, a dynamic D flip-flop, a register, a processor, and a computing device. Background Art

[0002] As high-performance computing is widely used in exploration, climate change, transportation, artificial intelligence and other fields, the requirements for power consumption, computing speed, and area (cost) of computing chips are getting higher and higher. Computing chips need to use latches to latch data, and as the amount of calculation increases, the more latches the computing chip uses. Therefore, the performance of the latch directly affects the performance of the computing chip.

[0003] Compared with static latches, dynamic latches greatly simplify their circuit structure because they reduce the feedback circuit used to maintain the working state, which not only reduces the chip area but also reduces power consumption. With these advantages, dynamic latches are widely used in computing chips. However, since there are nodes in the dynamic latch whose potential is floating for part of the time, the parasitic capacitance at the node needs to maintain the correct voltage state during the part of the time.

[0004] In order to prevent device leakage from affecting the voltage of the node, the dynamic latch must operate at a higher frequency to reduce the leakage time to prevent functional errors. This greatly limits the scope of chip use. For example, in some states of the processor such as sleep or idle, the dynamic latch may operate at a relatively low frequency, and functional errors are likely to occur at this time. Summary of the invention

[0005] According to a first aspect of the present disclosure, a latch circuit is provided, the latch circuit comprising: an input terminal; an output terminal; a first transistor having a first conductivity type, the control terminal of the first transistor being configured to receive a first clock signal; a second transistor having a second conductivity type different from the first conductivity type, the control terminal of the second transistor being configured to receive a second clock signal inverted from the first clock signal; and a third transistor, the control terminal of the third transistor being configured to receive a clock signal identical to the clock signal received by the control terminal of a transistor of the same conductivity type as the third transistor in the first and second transistors. The first transmission terminal of the first transistor and the first transmission terminal of the second transistor are commonly connected to the input terminal. The second transmission terminal of the first transistor is connected to the output terminal via the third transistor. The second transmission terminal of the second transistor is connected to the output terminal.

[0006] According to a second aspect of the present disclosure, a dynamic latch is provided, which includes: a data input terminal configured to receive a data signal; a data output terminal configured to output a data signal; a clock control terminal configured to receive a clock signal; and a latch unit and an inverting drive unit sequentially connected in series between the data input terminal and the data output terminal. The latch unit is configured to latch or transmit a data signal from the data input terminal under the control of a clock signal. The inverting drive unit is configured to invert and transmit a data signal from the latch unit.

[0007] In some embodiments, the latch unit includes the latch circuit according to the first aspect of the present disclosure.

[0008] In some embodiments, the latch unit includes the latch circuit according to the first aspect of the present disclosure, and an inverter connected in series between a data input terminal and the latch circuit.

[0009] According to a third aspect of the present disclosure, a dynamic D flip-flop is provided, which includes: a data input terminal configured to receive a data signal; a data output terminal configured to output a data signal; a clock control terminal configured to receive a clock signal; and a first latch unit, a second latch unit and an inverting drive unit connected in series between the data input terminal and the data output terminal. The first latch unit is configured to latch or transmit a data signal from the data input terminal under the control of a clock signal. The second latch unit is configured to latch or transmit a data signal from the first latch unit under the control of a clock signal. The inverting drive unit is configured to invert and transmit a data signal from the second latch unit.

[0010] In some embodiments, the first latch unit includes the latch circuit according to the first aspect of the present disclosure.

[0011] In some embodiments, the first latch unit includes an inverter and the latch circuit according to the first aspect of the present disclosure, which are sequentially connected in series between the data input terminal and the second latch unit.

[0012] In some embodiments, the second latch unit includes an inverter and the latch circuit according to the first aspect of the present disclosure, which are sequentially connected in series between the first latch unit and the inverting driving unit.

[0013] According to a fourth aspect of the present disclosure, a register is provided, the register comprising: a plurality of data input terminals configured to receive data signals; a plurality of data output terminals configured to output data signals; a clock control terminal configured to receive clock signals; a clock buffer configured to buffer the clock signals received by the clock control terminal and provide clock signals to a plurality of register units; and the plurality of register units are connected in parallel between the plurality of data input terminals and the plurality of data output terminals, and are configured to write and / or read data under the control of the clock signals. The register units in the plurality of register units are the dynamic latches according to the second aspect of the present disclosure, or the dynamic D flip-flops according to the third aspect of the present disclosure.

[0014] According to a fifth aspect of the present disclosure, a processor is provided, which includes the dynamic latch according to the second aspect of the present disclosure, or the dynamic D flip-flop according to the third aspect of the present disclosure, or the register according to the fourth aspect of the present disclosure.

[0015] According to a sixth aspect of the present disclosure, a computing device is provided, which includes the processor according to the fifth aspect of the present disclosure.

[0016] Other features and advantages of the present disclosure will become apparent from the following detailed description of exemplary embodiments of the present disclosure with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The accompanying drawings, which constitute a part of the specification, describe embodiments of the present disclosure and, together with the specification, are used to explain the principles of the present disclosure. With reference to the accompanying drawings, the present disclosure can be more clearly understood according to the following detailed description, in which:

[0018] Figure 1 A circuit diagram of a dynamic latch according to a comparative example of the present disclosure is shown;

[0019] Figure 2 Shows Figure 1 Schematic diagram of the equivalent circuit;

[0020] Figure 3 A dynamic latch according to some embodiments of the present disclosure is shown;

[0021] Figure 4 A clock buffer according to some embodiments of the present disclosure is shown;

[0022] Figure 5 A dynamic latch and its associated clock circuit according to some embodiments of the present disclosure are shown;

[0023] Figures 6 to 17 Schematic diagrams of circuits of dynamic latches according to some embodiments of the present disclosure are respectively shown;

[0024] Fig.18 A dynamic D flip-flop according to some embodiments of the present disclosure is shown;

[0025] Figures 19 to 27 Schematic diagrams of circuits of dynamic D flip-flops according to some embodiments of the present disclosure are respectively shown;

[0026] Fig.28 shows registers according to some embodiments of the present disclosure;

[0027] Fig.29 Shows Fig.10 An example timing diagram of a circuit of a dynamic latch is shown;

[0028] Fig.30 Shows Fig.16 An example timing diagram of a dynamic latch circuit is shown.

[0029] Note that in the embodiments described below, the same reference numerals are sometimes used in common between different drawings to represent the same parts or parts with the same functions, and their repeated descriptions are omitted. In this specification, similar reference numerals and letters are used to represent similar items, so once an item is defined in one drawing, it does not need to be further discussed in other drawings unless otherwise specified.

[0030] For ease of understanding, the positions, sizes, and ranges of various structures shown in the drawings and the like sometimes do not represent actual positions, sizes, and ranges, etc. Therefore, the disclosed invention is not limited to the positions, sizes, and ranges, etc. disclosed in the drawings and the like. In addition, the drawings are not necessarily drawn to scale, and some features may be exaggerated to show details of specific components. DETAILED DESCRIPTION

[0031] Various exemplary embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. It should be noted that unless otherwise specifically stated, the relative arrangement of components and steps, numerical expressions and numerical values ​​set forth in these embodiments do not limit the scope of the present disclosure.

[0032] The following description of at least one exemplary embodiment is in fact merely illustrative and is in no way intended to limit the present disclosure and its application or use. That is, the structures and methods herein are shown in an exemplary manner to illustrate different embodiments of the structures and methods in the present disclosure. However, those skilled in the art will appreciate that they merely illustrate exemplary ways of the present disclosure that can be implemented, rather than exhaustive ways. In addition, the drawings need not be drawn to scale, and some features may be enlarged to illustrate the details of specific components.

[0033] In addition, technologies, methods, and equipment known to ordinary technicians in the relevant art may not be discussed in detail, but where appropriate, the technologies, methods, and equipment should be considered as part of the specification.

[0034] In all examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not as limiting. Therefore, other examples of the exemplary embodiments may have different values.

[0035] It should be understood that although the drawings in this document mainly use metal oxide semiconductor (MOS) transistors as examples for illustration, the present disclosure is not limited thereto, but may also adopt any other suitable transistors, including but not limited to bipolar junction (BJT) transistors, etc.

[0036] It should also be understood that, in this article, the control end of a transistor may refer to a port used to control the current flow and switching state of the transistor, and the transmission end of a transistor may refer to a port for current or signal input and output of the transistor. For example, specifically, for a MOS transistor, the control end is the gate, and the transmission end is the source and drain; for a BJT transistor, the control end is the base, and the transmission end is the emitter and collector. In addition, for example, for a MOS transistor, the first conductivity type is one of the P type and the N type, and the second conductivity type is the other of the P type and the N type; for a BJT transistor, the first conductivity type is one of the PNP type and the NPN type, and the second conductivity type is the other of the PNP type and the NPN type.

[0037] It should also be understood that in this article, power and ground are relative concepts, which exist relative to each other and are used to describe the polarity and direction of voltage in a circuit. For example, power can represent a high level and ground can represent a low level.

[0038] Figure 1A dynamic latch 10 according to a comparative example of the present disclosure is shown. The dynamic latch 10 includes a transmission gate 11 and an inverter 12 connected in series between a data input terminal D and a data output terminal Q. Specifically, the transmission gate 11 includes a P-type metal oxide semiconductor (PMOS) transistor and an N-type metal oxide semiconductor (NMOS) transistor connected in parallel, and the clock signals received by the gates of the two transistors are inverted to each other. The inverter 12 includes a PMOS transistor and an NMOS transistor connected in series between a power supply VDD and a ground VSS, the gates of the two transistors are connected in common to form the input terminal of the inverter 12, and the drains of the two transistors are connected in common to form the output terminal of the inverter 12. Thus, assuming that the data input terminal D receives a data signal S, when the clock signal CLKP is at a high level and the clock signal CLKN is at a low level, the transmission gate 11 is turned on, and the data signal S passes through the transmission gate 11 to the inverter 12, thereby being inverted by the inverter 12, so that the inverted version of the data signal S is output at the data output terminal Q. That is, the dynamic latch 10 is a dynamic latch for providing an inverted output.

[0039] like Figure 1 As shown, a node A is formed between the transmission gate 11 and the inverter 12. Data is temporarily stored on the node A through the parasitic capacitance of the inverter 12. However, in the operation of the dynamic latch 10, the potential of the node A may be suspended during a portion of the clock cycle. Dynamic leakage will cause the data temporarily stored on the node A to be lost.

[0040] Combination Figure 1 and Figure 2 When CLKP is high and CLKN is low, the transmission gate 11 is turned on, thereby transmitting data from the data input terminal D to the node A, so as to write the data into the parasitic capacitance C of the node A. When CLKP becomes low and CLKN becomes high, the transmission gate 11 is closed, and the data previously transmitted by the transmission gate 11 is retained in the parasitic capacitance C of the node A.

[0041] When CLKP is low and CLKN is high, assuming that the data stored in node A is "0", if the data at the data input terminal D changes to "1", a pull-up leakage path is formed through the transmission gate 11 (such as Figure 2 As shown in (a) in FIG. 1 ), the parasitic capacitance C is charged. When the clock frequency is low, that is, when the period when CLKP is low and CLKN is high (or the off period) is long enough, the level of node A will change from "0" to "1", resulting in data loss.

[0042] When CLKP is low and CLKN is high, assuming that the data stored in node A is "1", if the data at the data input terminal D becomes "0", a pull-down leakage path is formed through the transmission gate 11 (such as Figure 2 As shown in (b) in FIG. 1 ), the parasitic capacitance C is discharged. When the clock frequency is low, that is, the off period is long enough, the level of node A will change from "1" to "0", resulting in data loss.

[0043] That is to say, when CLKP is at a low level and CLKN is at a high level, the transmission gate 11 may not be ideally kept closed, but there is a certain leakage path, especially as the closed period increases, the risk of data loss increases. However, as the process node continues to shrink (for example, 7 nanometers, 5 nanometers, etc.), the leakage increases, which requires that the closed period has to be shorter and shorter.

[0044] Specifically, assuming that the charge stored on the parasitic capacitor C is Q, the capacitance value of the parasitic capacitor C is C, and the voltage across the parasitic capacitor C is V, then Q=C*V. If the leakage current is I leakage , then the leakage time T (corresponding to the off period) is T=Q / I leakage =C*V / I leakage The leakage time is proportional to the clock period, that is, the clock frequency F clk ∝1 / T=I leakage / (C*V). Therefore, dynamic leakage limits the minimum operating frequency of the dynamic latch. If the operating frequency of the dynamic latch is too low, functional errors may occur.

[0045] To this end, the present disclosure provides a dynamic latch that can effectively suppress dynamic leakage, so that it can operate normally at a lower operating frequency. This is conducive to reducing power consumption, especially when such a dynamic latch is widely used in a computing chip, the overall power consumption of the computing chip can be significantly reduced. The dynamic latch according to various embodiments of the present disclosure will be described in detail below in conjunction with the accompanying drawings. It should be understood that the actual dynamic latch may also include other components, and in order to avoid blurring the main points of the present disclosure, these other components are not discussed herein and are not shown in the accompanying drawings.

[0046] Figure 3A dynamic latch 100 according to some embodiments of the present disclosure is shown. The dynamic latch 100 includes a data input terminal 101, a data output terminal 102, a clock control terminal 103, and a latch unit 104 and an inverting drive unit 105 connected in series between the data input terminal 101 and the data output terminal 102. The data input terminal 101 is configured to receive a data signal. The data output terminal 102 is configured to output a data signal. The clock control terminal 103 is configured to receive a clock signal. The latch unit 104 is configured to latch or transmit the data signal from the data input terminal 101 under the control of the clock signal. The inverting drive unit 105 is configured to invert and transmit the data signal from the latch unit 104.

[0047] Figure 4 The clock buffer 200 for providing a clock signal is shown. The clock buffer 200 is composed of two stages of inverters 201 and 202 connected in series. The clock buffer 200 buffers the input clock signal CK and provides mutually inverted clock signals CLKN and CLKP. Figure 4 Only two inverters are shown in FIG. 1 , but the number of inverters is not limited to two, and can be more. The clock buffer 200 can be used to provide a clock signal for the dynamic latch 100. Figure 5 As shown, the clock signal CK is buffered by the clock buffer 200 and provides mutually inverted clock signals CLKN and CLKP to the dynamic latch 100. Similarly, the clock buffer 200 can be used to provide mutually inverted clock signals CLKN and CLKP to the dynamic D flip-flops, registers, etc. described below.

[0048] In some embodiments, the latch unit 104 may include a latch circuit according to various embodiments of the present disclosure. The latch circuit includes: an input terminal; an output terminal; a first transistor having a first conductivity type, the control terminal of the first transistor being configured to receive a first clock signal; a second transistor having a second conductivity type different from the first conductivity type, the control terminal of the second transistor being configured to receive a second clock signal that is inverted from the first clock signal; and a third transistor, the control terminal of the third transistor being configured to receive a clock signal that is the same as the clock signal received by the control terminal of a transistor of the same conductivity type as the third transistor in the first transistor and the second transistor.

[0049] The first transmission terminal of the first transistor and the first transmission terminal of the second transistor are commonly connected to the input terminal. The second transmission terminal of the first transistor is connected to the output terminal via the third transistor. The second transmission terminal of the second transistor is connected to the output terminal. Such a latch circuit can be configured as a latch circuit for providing a common-phase output.

[0050] In some embodiments, the third transistor has a first conductivity type. In other embodiments, the third transistor has a second conductivity type.

[0051] Specifically, in some embodiments, the latch circuit may include a first subcircuit and a second subcircuit connected in parallel between an input terminal and an output terminal, wherein the first transistor and the third transistor are included in the first subcircuit and connected in series with each other, and the second transistor is included in the second subcircuit.

[0052] For example, refer to Figure 6 , which shows a circuit 300 of a dynamic latch 100 according to some embodiments of the present disclosure. Figure 6 As shown, the circuit 300 includes a latch circuit 320 (which serves as the latch unit 104 (specifically, the in-phase latch unit) of the dynamic latch 100) and an inverter 330 (which serves as the inverting driving unit 105 of the dynamic latch 100) which are sequentially connected in series between the data input terminal D and the data output terminal Q.

[0053] The inverter 330 includes a PMOS transistor 331 and an NMOS transistor 332 which are sequentially connected in series between a power supply VDD and a ground VSS, the control terminals (here, gates) of the two transistors are commonly connected to form an input terminal of the inverter 330, and the transmission terminals (here, drains) of the two transistors are commonly connected to form an output terminal of the inverter 330. The output terminal of the inverter 330 can directly provide a data output terminal Q of the circuit 300.

[0054] The latch circuit 320 has an input terminal 3201 and an output terminal 3202. The input terminal 3201 of the latch circuit 320 can directly provide the data input terminal D of the circuit 300. The output terminal 3202 of the latch circuit 320 is connected to the input terminal of the inverter 330, forming a node A whose potential is suspended for part of the time.

[0055] like Figure 6As shown, the latch circuit 320 includes a first subcircuit (here, the upper subcircuit) and a second subcircuit (here, the lower subcircuit) connected in parallel between the input terminal 3201 and the output terminal 3202, wherein the first transistor 321 (here, the NMOS transistor) is included in the first subcircuit, and the second transistor 322 (here, the PMOS transistor) is included in the second subcircuit. The first transmission terminal (here, the drain) of the first transistor 321 and the first transmission terminal (here, the source) of the second transistor 322 are commonly connected to the input terminal 3201. The second transmission terminal (here, the drain) of the second transistor 322 is connected to the output terminal 3202. The latch circuit 320 also includes a third transistor 323 (here, the NMOS transistor), which is also included in the first subcircuit and connected in series with the first transistor 321. The second transmission terminal (here, the source) of the first transistor 321 is connected to the output terminal 3202 via the third transistor 323. Generally, the bulk regions of these transistors are not suspended, wherein the bulk region of the PMOS transistor may be connected to a power source, and the bulk region of the NMOS transistor may be grounded.

[0056] exist Figure 6 In the example of , the third transistor 323 has the same conductivity type as the first transistor 321, and they both receive the clock signal CLKP. Although not shown, the third transistor 323 and the control terminal (here, the gate) of the first transistor 321 can be connected together to receive the clock signal CLKP. In addition, the second transistor 322 has a different conductivity type from the first transistor 321, so that the control terminal (here, the gate) of the second transistor 322 receives the clock signal CLKN that is inverse to the clock signal CLKP.

[0057] and Figure 1 Compared with the dynamic latch 10, Figure 6 By connecting the third transistor 323 in series with the first transistor 321 , it is equivalent to realizing an NMOS transistor with a channel extension, thereby reducing leakage current and further realizing a lower minimum operating frequency.

[0058] This is especially advantageous in digital circuits, because digital circuits cannot design transistor sizes as arbitrarily as analog circuits, but usually use transistors from the Standard Cell Library. The channel length size selection of transistors in the Standard Cell Library is limited, and can usually include two levels, one of which is 1 unit length and the other is 1.2 unit length. The channel extension caused by simply replacing a transistor with a 1 unit length channel with a 1.2 unit length channel cannot fully suppress dynamic leakage. By increasing the threshold voltage V THIt can also reduce its leakage current, but the choice of threshold voltage of transistors in the standard cell library is also limited. Usually, transistors in the standard cell library are divided into multiple gears (generally 3~4 gears) according to the level of threshold voltage. Transistors with high threshold voltages have slow speeds and small leakage, while transistors with low threshold voltages have fast speeds and large leakage. Selecting transistors with high threshold voltages can reduce leakage current. However, due to the limited gears, there is a certain gradient in the threshold voltage between the two gears, so the following situation often occurs: when a transistor with a low threshold voltage is selected, the leakage is too large, and when a transistor with a high threshold voltage is selected, the speed is reduced too much, and it is even more difficult to turn on in low-voltage applications. Therefore, adjusting the threshold voltage cannot achieve precise suppression of dynamic leakage. In this regard, the present disclosure proposes that by connecting transistors with a certain threshold voltage (for example, a low threshold voltage) in series, the threshold voltage of the transistor group after the series connection can be between the threshold voltage of the gear and the threshold voltage of the higher gear, which not only reduces leakage but also ensures speed.

[0059] Therefore, in some embodiments, the third transistor may include a plurality of third transistors connected in series with the first transistor. The second transmission terminal of the first transistor may be connected to the output terminal via the plurality of third transistors. By controlling the number of third transistors connected in series, the desired channel extension effect can be achieved according to specific needs, thereby fully suppressing dynamic leakage. Of course, the number of third transistors should not be too many, otherwise it will slow down the speed of the dynamic latch. In some examples, the number of third transistors does not exceed two, for example, one.

[0060] Figure 7 FIG. 3 shows a circuit 300 of a dynamic latch 100 according to some other embodiments of the present disclosure. Figure 6 compared to, Figure 7 The third transistor 323 in the embodiment has the same conductivity type as the second transistor 322 (both are P-type), and both receive the clock signal CLKN. Although not shown, the control terminal (here, the gate) of the third transistor 323 and the second transistor 322 can be connected together to receive the clock signal CLKN. In some cases, Figure 6 Compared to Figure 7 may be more advantageous because Figure 7 The circuit may require a higher power supply voltage. Nevertheless, connecting the third transistor 323 of a different conductivity type from the first transistor 321 in series with the first transistor 321 is still beneficial to suppress leakage current, thereby reducing the minimum operating frequency of the dynamic latch.

[0061] Figure 8 FIG. 3 shows a circuit 300 of a dynamic latch 100 according to some other embodiments of the present disclosure. Figure 6 In comparison, Figure 8In the embodiment, the conductivity type of the first transistor 321 and the third transistor 323 are both P-type, and they both receive the clock signal CLKN. In addition, the conductivity type of the second transistor 322 is N-type, and receives the clock signal CLKP.

[0062] Fig. 9 FIG. 3 shows a circuit 300 of a dynamic latch 100 according to some other embodiments of the present disclosure. Figure 7 In comparison, Fig. 9 In the embodiment, the conductivity type of the second transistor 322 and the third transistor 323 are both N-type, and they both receive the clock signal CLKP. In addition, the conductivity type of the first transistor 321 is P-type, and receives the clock signal CLKN.

[0063] Further, in some embodiments, the latch circuit may further include a fourth transistor, the control terminal of the fourth transistor being configured to receive a clock signal identical to a clock signal received by a control terminal of a transistor of the same conductivity type as the fourth transistor in the first transistor and the second transistor. In particular, the second transmission terminal of the second transistor is connected to the output terminal via the fourth transistor. In some embodiments, the fourth transistor has a first conductivity type. In other embodiments, the fourth transistor has a second conductivity type.

[0064] Specifically, in some embodiments, the latch circuit may include a first sub-circuit and a second sub-circuit connected in parallel between an input terminal and an output terminal, wherein the first transistor and the third transistor are included in the first sub-circuit and connected in series with each other, and the second transistor and the fourth transistor are included in the second sub-circuit and connected in series with each other.

[0065] For example, refer to Fig.10 , which shows a circuit 300 of a dynamic latch 100 according to some embodiments of the present disclosure. Figure 6 In comparison, Fig.10 In the embodiment, the latch circuit 320 further includes a fourth transistor 324 (here a PMOS transistor), which is also included in the second sub-circuit and connected in series with the second transistor 322. The second transmission terminal (here a drain) of the second transistor 322 is connected to the output terminal 3202 via the fourth transistor 324.

[0066] exist Fig.10 In the example, the fourth transistor 324 has the same conductivity type as the second transistor 322, and both receive the clock signal CLKN. Although not shown, the control terminal (here, the gate) of the fourth transistor 324 and the second transistor 322 can be connected together to receive the clock signal CLKN.

[0067] and Figure 1 Compared with the dynamic latch 10, Fig.10By connecting the fourth transistor 324 in series with the second transistor 322 , a PMOS transistor with an extended channel is realized, thereby reducing leakage current and achieving a lower minimum operating frequency.

[0068] In some embodiments, the fourth transistor may include a plurality of fourth transistors connected in series with the second transistor. The second transmission terminal of the second transistor may be connected to the output terminal via the plurality of fourth transistors. By controlling the number of fourth transistors connected in series, the desired channel extension effect can be achieved according to specific needs, thereby fully suppressing dynamic leakage. Of course, the number of fourth transistors should not be too many, otherwise the speed of the dynamic latch will be slowed down. In some examples, the number of fourth transistors does not exceed two, for example, one.

[0069] Fig.11 FIG. 3 shows a circuit 300 of a dynamic latch 100 according to some other embodiments of the present disclosure. Fig.10 compared to, Fig.11 The fourth transistor 324 has the same conductivity type as the first transistor 321 (both are N-type), and they both receive the clock signal CLKP. Although not shown, the fourth transistor 324 and the control terminals (here gates) of the first transistor 321 and the third transistor 323 can be connected together to receive the clock signal CLKP. In some cases, Fig.10 Compared to Fig.11 may be more advantageous because Fig.11 The circuit may require a higher power supply voltage. Nevertheless, connecting the fourth transistor 324 of a different conductivity type from the second transistor 322 in series with the second transistor 322 is still beneficial to suppress leakage current, thereby reducing the minimum operating frequency of the dynamic latch.

[0070] Fig.12 FIG. 3 shows a circuit 300 of a dynamic latch 100 according to some other embodiments of the present disclosure. Fig.10 In comparison, Fig.12 , the third transistor 323 has the same conductivity type as the second transistor 322 (both are P-type), and they both receive the clock signal CLKN. Although not shown, the control terminal (here, gate) of the third transistor 323 and the second transistor 322 can be connected together to receive the clock signal CLKN. In addition, the fourth transistor 324 has the same conductivity type as the first transistor 321 (both are N-type), and they both receive the clock signal CLKP. Although not shown, the control terminal (here, gate) of the fourth transistor 324 and the first transistor 321 can be connected together to receive the clock signal CLKP. In some cases, Fig.10 Compared to Fig.12 may be more advantageous because Fig.12Nevertheless, connecting the third transistor 323 of a different conductivity type from the first transistor 321 in series with the first transistor 321 and connecting the fourth transistor 324 of a different conductivity type from the second transistor 322 in series with the second transistor 322 still helps to suppress leakage current, thereby reducing the minimum operating frequency of the dynamic latch.

[0071] Fig.13 FIG. 3 shows a circuit 300 of a dynamic latch 100 according to some other embodiments of the present disclosure. Fig.10 In comparison, Fig.13 In the embodiment, two third transistors 323 and 323' having the same conductivity type as the first transistor 321 (here N-type) are connected in series to the first transistor 321, and two fourth transistors 324 and 324' having the same conductivity type as the second transistor 322 (here P-type) are connected in series to the second transistor 322. It can be understood that although the number of transistors in the two sub-circuits of the latch circuit 320 is depicted as the same here, this is merely exemplary and not restrictive. The number of transistors in the two sub-circuits can be adjusted separately according to actual needs. For example, when the transistor process determines that the leakage of the NMOS transistor is more serious than the leakage of the PMOS transistor, the number of transistors included in the sub-circuit formed by the NMOS transistor (here the upper sub-circuit) can be greater than the number of transistors included in the sub-circuit formed by the PMOS transistor (here the lower sub-circuit). On the contrary, when the transistor process determines that the leakage of the PMOS transistor is more serious than that of the NMOS transistor, the number of transistors included in the subcircuit formed by the PMOS transistor (here, the lower subcircuit) can be greater than the number of transistors included in the subcircuit formed by the NMOS transistor (here, the upper subcircuit). In addition, the balance of the operating speeds of different subcircuits is also a consideration. For example, when the transistor process determines that the speed of the NMOS transistor is faster than the speed of the PMOS transistor, the number of transistors included in the subcircuit formed by the NMOS transistor (here, the upper subcircuit) can be greater than the number of transistors included in the subcircuit formed by the PMOS transistor (here, the lower subcircuit). On the contrary, when the transistor process determines that the speed of the PMOS transistor is faster than the speed of the NMOS transistor, the number of transistors included in the subcircuit formed by the PMOS transistor (here, the lower subcircuit) can be greater than the number of transistors included in the subcircuit formed by the NMOS transistor (here, the upper subcircuit). However, in general, low-leakage devices are usually high-threshold devices, and high-threshold devices are slower than low-threshold devices. Therefore, considering the number of transistors from the perspectives of speed and leakage, the final conclusion may be the same.

[0072] In summary, in various embodiments, the latch circuit 320 may include a first subcircuit and a second subcircuit connected in parallel between the input terminal 3201 and the output terminal 3202. The first subcircuit and the second subcircuit include transistors of different conductivity types (for example, the first subcircuit includes a first transistor having a first conductivity type, and the second subcircuit includes a second transistor having a second conductivity type). At least one of the first subcircuit and the second subcircuit includes a plurality of transistors connected in series (for example, the first subcircuit also includes a third transistor connected in series with the first transistor, and / or the second subcircuit also includes a fourth transistor connected in series with the second transistor). The number of transistors included in each of the first subcircuit and the second subcircuit may be determined by comprehensively considering factors such as transistor technology, for example, a subcircuit with more serious leakage due to transistor technology may include more transistors, and / or the speed of different subcircuits may be balanced by controlling the number of transistors. In some examples, the first subcircuit and the second subcircuit connected in parallel therewith may include the same number of transistors, which may be conducive to making the manufacturing process easy to implement. In fact, making one of the first sub-circuit and the second sub-circuit have fewer transistors than the other does not necessarily lead to a reduction in chip area in terms of process. The chip area occupied by the latch circuit 320 is often determined by the sub-circuit with more transistors.

[0073] Alternatively, the latch circuit 320 may also include a third sub-circuit and a fourth sub-circuit connected in series between the input terminal 3201 and the output terminal 3202. Each of the third sub-circuit and the fourth sub-circuit may include transistors of different conductivity types connected in parallel.

[0074] Specifically, in some embodiments, the conductivity type of the fourth transistor may be different from that of the third transistor, the first transistor and the second transistor are included in the third subcircuit and connected in parallel to each other, and the third transistor and the fourth transistor are included in the fourth subcircuit and connected in parallel to each other.

[0075] Thus, the second transmission terminal of the first transistor and the second transmission terminal of the second transistor are commonly connected to the first transmission terminal of the third transistor, the first transmission terminal of the fourth transistor is also connected to the first transmission terminal of the third transistor, and the second transmission terminal of the third transistor and the second transmission terminal of the fourth transistor are commonly connected to the output terminal.

[0076] For example, refer to Fig.14 , which shows a circuit 300 of the dynamic latch 100 according to some other embodiments of the present disclosure. Fig.10 compared to, Fig.14The latch circuit 320 includes a third sub-circuit (here, the left sub-circuit) and a fourth sub-circuit (here, the right sub-circuit) connected in series between an input terminal 3201 and an output terminal 3202, a first transistor 321 and a second transistor 322 of different conductivity types are included in the third sub-circuit and connected in parallel to each other, and a third transistor 323 and a fourth transistor 324 of different conductivity types are included in the fourth sub-circuit and connected in parallel to each other.

[0077] exist Fig.14 , the second transmission terminal (here, source) of the first transistor 321 and the second transmission terminal (here, drain) of the second transistor 322 are commonly connected to the first transmission terminal (here, drain) of the third transistor 323, the first transmission terminal (here, source) of the fourth transistor 324 is also connected to the first transmission terminal (here, drain) of the third transistor 323, and the second transmission terminal (here, source) of the third transistor 323 and the second transmission terminal (here, drain) of the fourth transistor 324 are commonly connected to the output terminal 3202. Although not shown, the control terminal (here, gate) of the third transistor 323 and the first transistor 321 may be commonly connected to receive the clock signal CLKP, and the control terminal (here, gate) of the fourth transistor 324 and the second transistor 322 may be commonly connected to receive the clock signal CLKN.

[0078] The third sub-circuit and the fourth sub-circuit can be equivalent to a transmission gate respectively. Since the transmission gate itself does not have a driving capability, it is not suitable to connect more similar sub-circuits in series here, otherwise it will affect the operation of the dynamic latch.

[0079] and Figure 1 Compared with the dynamic latch 10, Fig.14 By adding a fourth sub-circuit including a third transistor 323 and a fourth transistor 324, and connecting the fourth sub-circuit in series with the third sub-circuit including the first transistor 321 and the second transistor 322, it is equivalent to realizing a transistor with extended channel, thereby reducing leakage current and achieving a lower minimum operating frequency.

[0080] It is understood that the aforementioned embodiments can be freely combined. Thus, at least one of the third subcircuit and the fourth subcircuit can be transformed into a parallel connection of the first subcircuit and the second subcircuit of any of the aforementioned embodiments. Therefore, in some embodiments, the third subcircuit includes the first subcircuit and the second subcircuit connected in parallel, the first transistor is included in the first subcircuit of the third subcircuit and the second transistor is included in the second subcircuit of the third subcircuit, the fourth subcircuit includes the first subcircuit and the second subcircuit connected in parallel, the third transistor is included in the first subcircuit of the fourth subcircuit and the fourth transistor is included in the second subcircuit of the fourth subcircuit, wherein the latch circuit also includes one or more of the following: one or more fifth transistors connected in series with the first transistor in the first subcircuit of the third subcircuit; one or more sixth transistors connected in series with the second transistor in the second subcircuit of the third subcircuit; one or more seventh transistors connected in series with the third transistor in the first subcircuit of the fourth subcircuit; one or more eighth transistors connected in series with the fourth transistor in the second subcircuit of the fourth subcircuit. The control terminal of each of the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor can be configured to receive the same clock signal as the clock signal received by the control terminal of the transistor of the same conductivity type as the transistor in the first transistor and the second transistor. Each of the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor can have a first conductivity type or a second conductivity type. For example, the fifth transistor and the first transistor can have the same conductivity type, the sixth transistor and the second transistor can have the same conductivity type, the seventh transistor and the third transistor can have the same conductivity type, and the eighth transistor and the fourth transistor can have the same conductivity type, which can be beneficial to reducing the power supply voltage required for the circuit.

[0081] For example, refer to Fig.15, the first transistor 321, the second transistor 322, the fifth transistor 325, and the sixth transistor 326 constitute a third sub-circuit, wherein the first transistor 321 and the fifth transistor 325 connected in series constitute a first sub-circuit of the third sub-circuit, the second transistor 322 and the sixth transistor 326 connected in series constitute a second sub-circuit of the third sub-circuit, and the first sub-circuit of the third sub-circuit is connected in parallel with the second sub-circuit of the third sub-circuit. In addition, the third transistor 323, the fourth transistor 324, the seventh transistor 327 and 327', the eighth transistor 328 and 328' constitute a fourth sub-circuit, wherein the third transistor 323 connected in series and the seventh transistor 327, 327' constitute a first sub-circuit of the fourth sub-circuit, the fourth transistor 324 and the eighth transistor 328, 328' connected in series constitute a second sub-circuit of the fourth sub-circuit, and the first sub-circuit of the fourth sub-circuit is connected in parallel with the second sub-circuit of the fourth sub-circuit. The third sub-circuit and the fourth sub-circuit are connected in series between the input terminal 3201 and the output terminal 3202. Fig.15 The sub-circuit combination of the latch circuit 320 is merely exemplary and non-restrictive, and may be a combination of the first sub-circuit, the second sub-circuit, the third sub-circuit and / or the fourth sub-circuit described in any embodiment of the present disclosure.

[0082] In the above embodiments, for example, Fig.10 In the embodiment shown, the dynamic latch is active high. Fig.10 and Fig.29 , at the beginning, the input data at the data input terminal D is "0", and the data output terminal Q provides the inverted output data "1". Then, the input data at the data input terminal D changes from "0" to "1", but because CLKP is low and CLKN is high at this time, the latch circuit 320 is turned off, so the data output terminal Q still maintains "1". As CLKP becomes high and CLKN becomes low, the latch circuit 320 is turned on, and the input data "1" at the data input terminal D is inverted by the inverter 330 after being transmitted in phase by the latch circuit 320, so that the data output terminal Q provides the inverted output data "0".

[0083] In addition, the application of the clock signals CLKP and CLKN in any embodiment of this invention can be reversed. Fig.16 , and Fig.10 In contrast, the application of the clock signals CLKP and CLKN is swapped, so that the first transistor 321 and the third transistor 323 receive the clock signal CLKN and the second transistor 322 and the fourth transistor 324 receive the clock signal CLKP, thereby realizing a low-level active dynamic latch. Fig.16 and Fig.30, at the beginning, the input data at the data input terminal D is "0", and the data output terminal Q provides the inverted output data "1". Then, the input data at the data input terminal D changes from "0" to "1", but because CLKP is at a high level and CLKN is at a low level at this time, the latch circuit 320 is turned off, so the data output terminal Q still maintains "1". As CLKP becomes a low level and CLKN becomes a high level, the latch circuit 320 is turned on, and the input data "1" at the data input terminal D is inverted by the inverter 330 after being transmitted in phase by the latch circuit 320, so that the data output terminal Q provides the inverted output data "0".

[0084] Front combination Figures 6 to 16 Various exemplary implementations of the dynamic latch 100 as a dynamic latch for providing an inverted output are described, but the present disclosure is not limited thereto, and the dynamic latch 100 can also be implemented as a dynamic latch for providing a non-inverted output, for example, by further including an inverter connected in series between the data input terminal and the latch circuit in the latch unit. For example, referring to Fig.17 , and Fig.10 In contrast, an inverter 310 connected in series between the data input terminal D and the latch circuit 320 is provided. The inverter 310 includes a PMOS transistor 311 and an NMOS transistor 312 connected in series between the power supply VDD and the ground VSS, the control terminals (here the gate) of the two transistors are connected together to form the input terminal of the inverter 310, and the transmission terminals (here the drain) of the two transistors are connected together to form the output terminal of the inverter 310. The output terminal of the inverter 310 can be directly connected to the input terminal 3201 of the latch circuit 320. The input terminal of the inverter 310 can directly provide the data input terminal D of the circuit 300. The combination of the inverter 310 and the latch circuit 320 can act as the latch unit 104 (specifically, the inverting latch unit) of the dynamic latch 100. It can be understood that the latch circuit 320 shown here is merely exemplary and can be replaced by the latch circuit described in any embodiment of the present disclosure. The latch circuits involved in the circuits shown in the subsequent figures are also exemplary and can be replaced by the latch circuits described in any embodiment of the present disclosure, which will not be described in detail hereinafter.

[0085] The present disclosure also provides a dynamic D flip-flop on the other hand, which can effectively suppress dynamic leakage, so that it can operate normally at a lower operating frequency. The dynamic D flip-flop according to various embodiments of the present disclosure will be described in detail below in conjunction with the accompanying drawings. It should be understood that the actual dynamic D flip-flop may also include other components, and in order to avoid blurring the main points of the present disclosure, these other components are not discussed herein and are not shown in the accompanying drawings.

[0086] Fig.18A dynamic D flip-flop 400 according to some embodiments of the present disclosure is shown. The dynamic D flip-flop 400 includes a data input terminal 401, a data output terminal 402, a clock control terminal 403, and a first latch unit 404, a second latch unit 405, and an inverting drive unit 406 connected in series between the data input terminal 401 and the data output terminal 402. The data input terminal 401 is configured to receive a data signal. The data output terminal 402 is configured to output a data signal. The clock control terminal 403 is configured to receive a clock signal. The first latch unit 404 is configured to latch or transmit the data signal from the data input terminal 401 under the control of the clock signal. The second latch unit 405 is configured to latch or transmit the data signal from the first latch unit 404 under the control of the clock signal. The inverting drive unit 406 is configured to invert and transmit the data signal from the second latch unit 405.

[0087] Compared with the static D flip-flop, the dynamic D flip-flop has a greatly simplified circuit structure due to the reduction of the feedback circuit used to maintain the working state, which not only reduces the chip area but also reduces the power consumption. With these advantages, the dynamic D flip-flop is used on a large scale in computing chips. However, since there are nodes in the dynamic D flip-flop whose potential is suspended for part of the time (for example, the node formed between the first latch unit 404 and the second latch unit 405, and the node formed between the second latch unit 405 and the inverting drive unit 406), the parasitic capacitance at the node needs to maintain the correct voltage state during the part of the time. In order to avoid the device leakage affecting the voltage of the node, the dynamic D flip-flop must operate at a higher frequency, thereby reducing the leakage time to prevent functional errors. This greatly limits the scope of chip use. For example, in some states of the processor such as sleep or idle, the dynamic D flip-flop may operate at a relatively low frequency, and functional errors are likely to occur at this time.

[0088] In some embodiments, the first latch unit 404 may include a latch circuit according to any embodiment of the present disclosure. The input end of such a latch circuit may directly provide the data input end 401 of the dynamic D flip-flop, for example. As described above, by using the latch circuit of the present disclosure in the first latch unit 404, leakage current can be effectively suppressed, thereby reducing the minimum operating frequency of the dynamic D flip-flop.

[0089] In some examples, the second latch unit 405 may include a tri-state gate. Fig.19 , which shows a circuit 500 of a dynamic D flip-flop 400 according to some embodiments of the present disclosure. Fig.19As shown, the circuit 500 includes a latch circuit 520 (which serves as the first latch unit 404 (specifically, the in-phase latch unit) of the dynamic D flip-flop 400), a tri-state gate 530 (which serves as the second latch unit 405 (specifically, the inverting latch unit) of the dynamic D flip-flop 400), and an inverter 570 (which serves as the inverting driving unit 406 of the dynamic D flip-flop 400) which are sequentially connected in series between the data input terminal D and the data output terminal Q. The potential of the node A formed between the latch circuit 520 and the tri-state gate 530, and the node B formed between the tri-state gate 530 and the inverter 570 are floating for part of the time.

[0090] The latch circuit 520 includes an NMOS transistor 521, a PMOS transistor 522, an NMOS transistor 523, and a PMOS transistor 524, which are non-limitingly configured as follows: Fig.10The example arrangement shown. Inverter 570 includes a PMOS transistor 571 and an NMOS transistor 572 connected in series between a power supply VDD and a ground VSS. Tristate gate 530 includes a PMOS transistor 531, a PMOS transistor 532, an NMOS transistor 533, and an NMOS transistor 534 connected in series between a power supply VDD and a ground VSS. In particular, NMOS transistor 521, NMOS transistor 523, and PMOS transistor 532 receive a clock signal CLKP, and PMOS transistor 522, PMOS transistor 524, and NMOS transistor 533 receive a clock signal CLKN. In this way, the clock signal can turn on tristate gate 530 when latch circuit 520 is turned off, and turn off tristate gate 530 when latch circuit 520 is turned on. Thus, when CLKP is at a high level and CLKN is at a low level, the latch circuit 520 is turned on and the tri-state gate 530 is turned off, and the data from the data input terminal D is transmitted in phase through the latch circuit 520 and output to the node A (for example, rewriting the data at the node A), but cannot continue to pass through the tri-state gate 530. When CLKP becomes a low level and CLKN becomes a high level, the latch circuit 520 is turned off and the tri-state gate 530 is turned on, and the data from the data input terminal D cannot pass through the latch circuit 520, and the data at the node A is retained, while the data from the node A is inverted and transmitted through the tri-state gate 520 and output to the node B (for example, rewriting the data at the node B), and further inverted and transmitted through the inverter 570 and output to the data output terminal Q. When CLKP becomes high again and CLKN becomes low again, the latch circuit 520 is turned on and the tri-state gate 530 is turned off. The data from the data input terminal D is transmitted in phase by the latch circuit 520 and output to the node A (for example, rewriting the data of the node A), but cannot continue to pass through the tri-state gate 530, and the data of the node B is maintained. Similar to the above, the application of the clock signals CLKP and CLKN can also be reversed, that is, the NMOS transistor 521, the NMOS transistor 523, and the PMOS transistor 532 receive the clock signal CLKN, and the PMOS transistor 522, the PMOS transistor 524, and the NMOS transistor 533 receive the clock signal CLKP, so that the effective level will also change accordingly. In addition, the arrangement of the tri-state gate 530 is not limited to this, and it can also be replaced by the gates of the PMOS transistor 531 and the NMOS transistor 534 receiving the corresponding clock signal and the gates of the PMOS transistor 532 and the NMOS transistor 533 being connected together to receive the data signal. The tri-state gates mentioned elsewhere in this article are also similar and will not be repeated hereafter.

[0091] In some examples, the second latch unit 405 may include an inverter and a transmission gate sequentially connected in series between the first latch unit 404 and the inverting driving unit 406. Fig. 20 , and Fig.19In contrast, the tri-state gate 530 is replaced by a combination of an inverter 540 and a transmission gate 550, which acts as a second latch unit 405 (specifically, an inverting latch unit) of the dynamic D flip-flop 400. The inverter 540 includes a PMOS transistor 541 and an NMOS transistor 542 connected in series between a power supply VDD and a ground VSS. The transmission gate 550 includes an NMOS transistor 551 and a PMOS transistor 552 connected in parallel between the inverter 540 and the inverter 570. The inverter 540 can provide driving capability for the transmission gate 550. Fig. 20 The timing control is similar to Fig.19 , I won’t go into details here.

[0092] In some examples, the second latch unit 405 may include an inverter and a latch circuit according to any embodiment of the present disclosure that are sequentially connected in series between the first latch unit 404 and the inverting driving unit 406. Fig.21 , and Fig. 20 In contrast, the transmission gate 550 is replaced by a latch circuit 560, and the combination of the inverter 540 and the latch circuit 560 serves as the second latch unit 405 (specifically, an inverting latch unit) of the dynamic D flip-flop 400. The inverter 540 can provide a driving capability for the latch circuit 560. The latch circuit 560 includes an NMOS transistor 561, a PMOS transistor 562, an NMOS transistor 563, and a PMOS transistor 564, which are non-limitingly configured as follows: Fig.16 Thus, latch circuit 520 can alleviate the influence of dynamic leakage of node A, and latch circuit 560 can alleviate the influence of dynamic leakage of node B, so that the minimum working efficiency of the dynamic D flip-flop can be further reduced. Fig.21 The timing control is similar to Fig.19 , I won’t go into details here.

[0093] In other embodiments, the first latch unit 404 may include an inverter connected in series between the data input terminal 401 and the second latch unit 405 and a latch circuit according to any embodiment of the present disclosure. The input terminal of such an inverter may, for example, directly provide the data input terminal 401 of the dynamic D flip-flop. In such an embodiment, the second latch unit 405 may, for example, include one of the following: a tri-state gate; an inverter and a transmission gate connected in series between the first latch unit 404 and the inverting drive unit 406; an inverter connected in series between the first latch unit 404 and the inverting drive unit 406 and a latch circuit according to any embodiment of the present disclosure.

[0094] For example, Fig. 22 FIG. 6 shows a circuit 600 of a dynamic D flip-flop 400 according to some embodiments of the present disclosure. Fig. 22As shown, the circuit 600 includes an inverter 610, a latch circuit 620 (the combination of the inverter 610 and the latch circuit 620 serves as the first latch unit 404 (specifically, the inverting latch unit) of the dynamic D flip-flop 400), a tri-state gate 630 (which serves as the second latch unit 405 (specifically, the inverting latch unit) of the dynamic D flip-flop 400), and an inverter 670 (which serves as the inverting driving unit 406 of the dynamic D flip-flop 400). The inverter 610 includes a PMOS transistor 611 and an NMOS transistor 612, which are sequentially connected in series between a power supply VDD and a ground VSS. The latch circuit 620 includes an NMOS transistor 621, a PMOS transistor 622, an NMOS transistor 623, and a PMOS transistor 624, which are non-limitingly configured as follows. Fig.10 The tri-state gate 630 includes a PMOS transistor 631, a PMOS transistor 632, an NMOS transistor 633, and an NMOS transistor 634 connected in series between a power supply VDD and a ground VSS. The inverter 670 includes a PMOS transistor 671 and an NMOS transistor 672 connected in series between a power supply VDD and a ground VSS.

[0095] Fig.23 and Fig. 22 In contrast, the tri-state gate 630 is replaced by a combination of an inverter 640 and a transmission gate 650, which acts as a second latch unit 405 (specifically, an inverting latch unit) of the dynamic D flip-flop 400. The inverter 640 includes a PMOS transistor 641 and an NMOS transistor 642 connected in series between a power supply VDD and a ground VSS. The transmission gate 650 includes an NMOS transistor 651 and a PMOS transistor 652 connected in parallel between the inverter 640 and the inverter 670. The inverter 640 can provide driving capability for the transmission gate 650.

[0096] Fig.24 and Fig.23 In contrast, the transmission gate 650 is replaced by a latch circuit 660, and the combination of the inverter 640 and the latch circuit 660 serves as the second latch unit 405 (specifically, an inverting latch unit) of the dynamic D flip-flop 400. The inverter 640 can provide a driving capability for the latch circuit 660. The latch circuit 660 includes an NMOS transistor 661, a PMOS transistor 662, an NMOS transistor 663, and a PMOS transistor 664, which are non-limitingly configured as follows: Fig.16 Thus, latch circuit 620 can alleviate the influence of dynamic leakage of node A, and latch circuit 660 can alleviate the influence of dynamic leakage of node B, so that the minimum working efficiency of the dynamic D flip-flop can be further reduced.

[0097] Figure 22 to Figure 24 The timing control of the dynamic D flip-flop for providing an inverted output is similar to Figures 19 to 21 The timing control of the dynamic D flip-flop shown for providing the same-phase output is not described in detail here.

[0098] In some other embodiments, the second latch unit 405 may include an inverter connected in series between the first latch unit 404 and the inverting drive unit 406 and a latch circuit according to any embodiment of the present disclosure. In such an embodiment, the first latch unit 404 may include, for example, one of the following: a transmission gate; a tri-state gate; an inverter and a transmission gate connected in series between the data input terminal 401 and the second latch unit 405.

[0099] For example, Fig.25 FIG. 7 shows a circuit 700 of a dynamic D flip-flop 400 according to some embodiments of the present disclosure. Fig.25 As shown, the circuit 700 includes a tri-state gate 710 (which serves as the first latch unit 404 (specifically, the inverting latch unit) of the dynamic D flip-flop 400), an inverter 750, a latch circuit 760 (the combination of the inverter 750 and the latch circuit 760 serves as the second latch unit 405 (specifically, the inverting latch unit) of the dynamic D flip-flop 400), and an inverter 770 (which serves as the inverting driving unit 406 of the dynamic D flip-flop 400) which are sequentially connected in series between the data input terminal D and the data output terminal Q. The tri-state gate 710 includes a PMOS transistor 711, a PMOS transistor 712, an NMOS transistor 713, and an NMOS transistor 714 which are sequentially connected in series between the power supply VDD and the ground VSS. The inverter 750 includes a PMOS transistor 751 and an NMOS transistor 752 which are sequentially connected in series between the power supply VDD and the ground VSS. The latch circuit 760 includes an NMOS transistor 761, a PMOS transistor 762, an NMOS transistor 763, and a PMOS transistor 764, which are non-limitingly configured as follows: Fig.16 The example arrangement shown. The inverter 750 can provide driving capability for the latch circuit 760. The inverter 770 includes a PMOS transistor 771 and an NMOS transistor 772 which are sequentially connected in series between a power supply VDD and a ground VSS. Fig.25 The timing control of the dynamic D flip-flop shown to provide an inverted output is similar to Fig.19 , I won’t go into details here.

[0100] Fig.26 and Fig.25In contrast, the tri-state gate 710 is replaced by a combination of an inverter 720 and a transmission gate 730, which serves as the first latch unit 404 (specifically, an inverting latch unit) of the dynamic D flip-flop 400. The inverter 720 includes a PMOS transistor 721 and an NMOS transistor 722 connected in series between the power supply VDD and the ground VSS. The transmission gate 730 includes an NMOS transistor 731 and a PMOS transistor 732 connected in parallel between the inverter 720 and the inverter 750. Fig.26 The timing control of the dynamic D flip-flop shown to provide an inverted output is similar to Fig.19 , I won’t go into details here.

[0101] Fig. 27 and Fig.26 In contrast, the combination of inverter 720 and transmission gate 730 is replaced by transmission gate 740, which serves as the first latch unit 404 (specifically, the in-phase latch unit) of dynamic D flip-flop 400. Transmission gate 740 includes an NMOS transistor 741 and a PMOS transistor 742 connected in parallel between the data input terminal D and inverter 750. Fig. 27 The timing control of the dynamic D flip-flop shown to provide a non-inverting output is similar to Fig.19 , I won’t go into details here.

[0102] The present disclosure provides a register in another aspect. Fig.28 As shown, the register 800 includes: a plurality of data input terminals D[n:0], configured to receive data signals; a plurality of data output terminals Q[n:0], configured to output data signals; a clock control terminal CK, configured to receive clock signals. The register 800 also includes a clock buffer 802, which is configured to buffer the clock signal received by the clock control terminal CK and provide clock signals (CLKP, CLKN) to a plurality of register units 801. The clock buffer 802 is similar to the aforementioned clock buffer 200 and is not described in detail here. The register 800 also includes a plurality of register units 801, which are connected in parallel between the plurality of data input terminals D[n:0] and the plurality of data output terminals Q[n:0], and are configured to write and / or read data under the control of the clock signal. In particular, the register units in the plurality of register units 801 may be the dynamic latch according to any embodiment of the present disclosure, or the dynamic D flip-flop according to any embodiment of the present disclosure.

[0103] Usually, an independent latch or D flip-flop requires a clock buffer to generate mutually inverted clock signals for timing control. If an independent clock buffer is configured for each latch or D flip-flop, the clock buffer will consume a considerable chip area and power consumption in applications that require the use of multiple latches or D flip-flops. To this end, the register according to the embodiment of the present disclosure uses a clock buffer to simultaneously drive multiple dynamic latches or dynamic D flip-flops, which can effectively reduce the area and power consumption.

[0104] On the other hand, the present disclosure provides a processor, which may include the dynamic latch according to any embodiment of the present disclosure, or the dynamic D flip-flop according to any embodiment of the present disclosure, or the register according to any embodiment of the present disclosure.

[0105] The present disclosure further provides a computing device in another aspect, which may include a processor according to any embodiment of the present disclosure. Such a computing device may include, for example, but is not limited to, a computing chip used in fields such as exploration, climate change, transportation, and artificial intelligence, or an electronic device including such a computing chip.

[0106] The words "left", "right", "front", "back", "top", "bottom", "up", "down", "high", "low", etc., in the specification and claims, if present, are used for descriptive purposes and are not necessarily used to describe an unchanging relative position. It should be understood that the words used in this way are interchangeable under appropriate circumstances, so that the embodiments of the present disclosure described herein, for example, can operate in other orientations than those shown or otherwise described herein. For example, when the device in the drawings is turned over, features previously described as being "above" other features may now be described as being "below" the other features. The device may also be oriented in other ways (rotated 90 degrees or in other orientations), and the relative spatial relationships will be interpreted accordingly.

[0107] In the specification and claims, when an element is referred to as being "on", "attached", "connected", "coupled", or "contacting" another element, the element may be directly on, directly attached, directly connected, directly coupled, or directly contacting another element, or one or more intermediate elements may be present. In contrast, when an element is referred to as being "directly" "on", "directly attached", "directly connected", "directly coupled", or "directly contacting" another element, there will be no intermediate elements. In the specification and claims, a feature being arranged "adjacent" to another feature may refer to a feature having a portion that overlaps with an adjacent feature or a portion that is located above or below an adjacent feature.

[0108] As used herein, the word "exemplary" means "serving as an example, instance, or illustration" rather than as a "model" to be exactly copied. Any implementation described as exemplary herein is not necessarily to be construed as preferred or advantageous over other implementations. Furthermore, the present disclosure is not to be limited by any expressed or implied theory given in the technical field, background, summary, or detailed description.

[0109] As used herein, the term "substantially" is intended to include any minor variations due to design or manufacturing imperfections, device or component tolerances, environmental influences, and / or other factors. The term "substantially" also allows for deviations from a perfect or ideal condition due to parasitic effects, noise, and other practical considerations that may exist in actual implementations.

[0110] In addition, the terms "first", "second" and the like may also be used herein for reference purposes only, and thus are not intended to be limiting. For example, the terms "first", "second" and other such numerical terms referring to structures or elements do not imply a sequence or order unless the context clearly indicates otherwise.

[0111] It should also be understood that the term "including / comprising" when used herein indicates the presence of the indicated features, integral bodies, steps, operations, units and / or components, but does not exclude the presence or addition of one or more other features, integral bodies, steps, operations, units and / or components and / or combinations thereof. In the present disclosure, the term "providing" is used in a broad sense to cover all ways of obtaining an object, so "providing an object" includes but is not limited to "purchasing", "preparing / manufacturing", "arranging / setting", "installing / assembling", and / or "ordering" an object, etc.

[0112] As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. The terms used herein are for the purpose of describing specific embodiments only and are not intended to limit the present disclosure. As used herein, the singular forms "a", "an", and "the" are also intended to include the plural forms, unless the context clearly indicates otherwise.

[0113] The same or similar parts between the various embodiments of the present disclosure can refer to each other, and each embodiment focuses on the differences from other embodiments. In the description of the present disclosure, the description of reference terms "one embodiment", "some embodiments", "example", "specific example", or "some examples", "exemplary", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present disclosure. In the present disclosure, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art can combine and combine the different embodiments or examples described in the present disclosure and the features of the different embodiments or examples without contradiction.

[0114] In addition, when used in the present disclosure, the words "herein," "above," "below," "herein," "herein below," "herein," "above," and words of similar meaning shall refer to the present disclosure as a whole rather than to any particular portion of the present disclosure. Furthermore, unless expressly stated otherwise or understood otherwise in the context of use, conditional language used herein, such as "may," "might," "for example," "such as," and the like, is generally intended to express that certain embodiments include, while other embodiments do not include, certain features, elements, and / or states. Thus, such conditional language is generally not intended to imply that one or more embodiments require features, elements, and / or states in any way, or whether such features, elements, and / or states are included or performed in any particular embodiment.

[0115] Those skilled in the art will appreciate that the boundaries between the above operations are merely illustrative. Multiple operations can be combined into a single operation, which can be distributed in additional operations, and operations can be performed at least partially overlapping in time. Moreover, alternative embodiments can include multiple instances of specific operations, and the order of operations can be changed in various other embodiments. However, other modifications, variations, and replacements are equally possible. Aspects and elements of all embodiments disclosed above can be combined in any manner and / or in combination with aspects or elements of other embodiments to provide multiple additional embodiments. Therefore, this specification and accompanying drawings should be considered illustrative, not restrictive.

[0116] Although some specific embodiments of the present disclosure have been described in detail by way of example, it should be understood by those skilled in the art that the above examples are for illustration only and are not intended to limit the scope of the present disclosure. The various embodiments disclosed herein may be combined in any manner without departing from the spirit and scope of the present disclosure. It should also be understood by those skilled in the art that various modifications may be made to the embodiments without departing from the scope and spirit of the present disclosure. The scope of the present disclosure is defined by the appended claims.

Claims

1. A latch circuit, characterized in that: The latch circuit comprises: An input terminal configured to receive a data signal; An output terminal configured to output a data signal; a first transistor having a first conductivity type, wherein a control terminal of the first transistor is configured to receive a first clock signal; a second transistor having a second conductivity type different from the first conductivity type, a control terminal of the second transistor being configured to receive a second clock signal that is inverted from the first clock signal; and a third transistor, wherein a control terminal of the third transistor is configured to receive a clock signal that is the same as a clock signal received by a control terminal of a transistor of the same conductivity type as the third transistor among the first transistor and the second transistor, The first transmission end of the first transistor and the first transmission end of the second transistor are commonly connected to the input end, the second transmission end of the first transistor is connected to the output end via the third transistor, and the second transmission end of the second transistor is connected to the output end. The latch circuit includes a first subcircuit and a second subcircuit connected in parallel between the input terminal and the output terminal, wherein the first transistor and the third transistor are included in the first subcircuit and connected in series with each other, and the second transistor is included in the second subcircuit. One of the first sub-circuit and the second sub-circuit has fewer transistors than the other.

2. The latch circuit according to claim 1, characterized in that: The third transistor has the first conductivity type.

3. The latch circuit according to claim 1 or 2, characterized in that: The third transistor includes a plurality of third transistors connected in series with the first transistor.

4. The latch circuit according to claim 1, wherein: The latch circuit further includes a fourth transistor, a control terminal of the fourth transistor being configured to receive a clock signal that is the same as a clock signal received by a control terminal of a transistor of the same conductivity type as the fourth transistor among the first transistor and the second transistor, The second transmission end of the second transistor is connected to the output end via the fourth transistor.

5. The latch circuit according to claim 4, characterized in that: The second transistor and the fourth transistor are included in the second sub-circuit and are connected in series to each other.

6. The latch circuit according to claim 4 or 5, characterized in that: The fourth transistor has the second conductivity type.

7. The latch circuit according to claim 4 or 5, characterized in that: The fourth transistor includes a plurality of fourth transistors connected in series with the second transistor.

8. A latch circuit, characterized in that: The latch circuit comprises: An input terminal configured to receive a data signal; An output terminal configured to output a data signal; a first transistor having a first conductivity type, wherein a control terminal of the first transistor is configured to receive a first clock signal; a second transistor having a second conductivity type different from the first conductivity type, wherein a control terminal of the second transistor is configured to receive a second clock signal that is inverted from the first clock signal; a plurality of third transistors connected in series with the first transistor, control terminals of the third transistors being configured to receive a clock signal that is the same as a clock signal received by a control terminal of a transistor of the same conductivity type as the third transistor among the first transistor and the second transistor; and a plurality of fourth transistors connected in series with the second transistor, wherein control terminals of the fourth transistors are configured to receive a clock signal that is the same as a clock signal received by a control terminal of a transistor of the same conductivity type as the fourth transistor among the first transistor and the second transistor, The first transmission end of the first transistor and the first transmission end of the second transistor are commonly connected to the input end, the second transmission end of the first transistor is connected to the output end via the multiple third transistors, and the second transmission end of the second transistor is connected to the output end via the multiple fourth transistors.

9. A latch circuit, characterized in that: The latch circuit comprises: An input terminal configured to receive a data signal; An output terminal configured to output a data signal; a first transistor having a first conductivity type, wherein a control terminal of the first transistor is configured to receive a first clock signal; a second transistor having a second conductivity type different from the first conductivity type, wherein a control terminal of the second transistor is configured to receive a second clock signal that is inverted from the first clock signal; a third transistor, a control terminal of the third transistor being configured to receive a clock signal that is the same as a clock signal received by a control terminal of a transistor of the same conductivity type as the third transistor among the first transistor and the second transistor; and a fourth transistor, wherein a control terminal of the fourth transistor is configured to receive a clock signal that is the same as a clock signal received by a control terminal of a transistor of the same conductivity type as the fourth transistor among the first transistor and the second transistor, The first transmission end of the first transistor and the first transmission end of the second transistor are commonly connected to the input end, the second transmission end of the first transistor is connected to the output end via the third transistor, and the second transmission end of the second transistor is connected to the output end via the fourth transistor. wherein the conductivity type of the fourth transistor is different from that of the third transistor, wherein the latch circuit includes a third sub-circuit and a fourth sub-circuit connected in series between the input terminal and the output terminal, wherein the first transistor and the second transistor are included in the third sub-circuit and connected in parallel to each other, and the third transistor and the fourth transistor are included in the fourth sub-circuit and connected in parallel to each other.

10. The latch circuit according to claim 9, characterized in that: The third sub-circuit includes a first sub-circuit and a second sub-circuit connected in parallel, the first transistor is included in the first sub-circuit of the third sub-circuit and the second transistor is included in the second sub-circuit of the third sub-circuit, The fourth subcircuit includes a first subcircuit and a second subcircuit connected in parallel, the third transistor is included in the first subcircuit of the fourth subcircuit and the fourth transistor is included in the second subcircuit of the fourth subcircuit, Wherein, the latch circuit further includes one or more of the following: one or more fifth transistors in a first subcircuit of the third subcircuit connected in series with the first transistor; or one or more sixth transistors in a second subcircuit of the third subcircuit connected in series with the second transistor; or one or more seventh transistors in the first subcircuit of the fourth subcircuit connected in series with the third transistor; or one or more eighth transistors in a second subcircuit of the fourth subcircuit connected in series with the fourth transistor, Among them, the control end of each of the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor is configured to receive a clock signal that is the same as the clock signal received by the control end of a transistor of the same conductive type as the transistor in the first transistor and the second transistor.

11. The latch circuit according to claim 10, characterized in that: The first sub-circuit and the second sub-circuit connected in parallel with the first sub-circuit include the same number of transistors.

12. The latch circuit according to claim 9, characterized in that: The transistor in the latch circuit is a metal oxide semiconductor (MOS) transistor.

13. A dynamic latch, characterized in that: The dynamic latch comprises: A data input terminal configured to receive a data signal; A data output terminal configured to output a data signal; A clock control terminal configured to receive a clock signal; and A latch unit and an inverting driving unit are sequentially connected in series between the data input terminal and the data output terminal, the latch unit is configured to latch or transmit a data signal from the data input terminal under the control of a clock signal, and the inverting driving unit is configured to invert and transmit the data signal from the latch unit, Wherein, the latch unit comprises a latch circuit according to any one of claims 1 to 12.

14. The dynamic latch according to claim 13, characterized in that: The latch unit further includes an inverter connected in series between the data input terminal and the latch circuit.

15. A dynamic D flip-flop, characterized in that: The dynamic D flip-flop comprises: A data input terminal configured to receive a data signal; A data output terminal configured to output a data signal; A clock control terminal configured to receive a clock signal; and A first latch unit, a second latch unit and an inverting drive unit are sequentially connected in series between the data input terminal and the data output terminal, wherein the first latch unit is configured to latch or transmit a data signal from the data input terminal under the control of a clock signal, the second latch unit is configured to latch or transmit a data signal from the first latch unit under the control of a clock signal, and the inverting drive unit is configured to invert and transmit a data signal from the second latch unit, Wherein, the first latch unit comprises a latch circuit according to any one of claims 1 to 12.

16. The dynamic D flip-flop according to claim 15, characterized in that: The second latch unit includes one of the following: tri-state gate; or an inverter and a transmission gate connected in series between the first latch unit and the inverting driving unit; or An inverter and a latch circuit according to any one of claims 1 to 12 are sequentially connected in series between the first latch unit and the inverting driving unit.

17. A dynamic D flip-flop, characterized in that: The dynamic D flip-flop comprises: A data input terminal configured to receive a data signal; A data output terminal configured to output a data signal; A clock control terminal configured to receive a clock signal; and A first latch unit, a second latch unit and an inverting drive unit are sequentially connected in series between the data input terminal and the data output terminal, wherein the first latch unit is configured to latch or transmit a data signal from the data input terminal under the control of a clock signal, the second latch unit is configured to latch or transmit a data signal from the first latch unit under the control of a clock signal, and the inverting drive unit is configured to invert and transmit a data signal from the second latch unit, The first latch unit includes an inverter and a latch circuit according to any one of claims 1 to 12 which are sequentially connected in series between the data input terminal and the second latch unit.

18. The dynamic D flip-flop according to claim 17, wherein: The second latch unit includes one of the following: tri-state gate; or an inverter and a transmission gate connected in series between the first latch unit and the inverting driving unit; or An inverter and a latch circuit according to any one of claims 1 to 12 are sequentially connected in series between the first latch unit and the inverting driving unit.

19. A dynamic D flip-flop, characterized in that: The dynamic D flip-flop comprises: A data input terminal configured to receive a data signal; A data output terminal configured to output a data signal; A clock control terminal configured to receive a clock signal; and A first latch unit, a second latch unit and an inverting drive unit are sequentially connected in series between the data input terminal and the data output terminal, wherein the first latch unit is configured to latch or transmit a data signal from the data input terminal under the control of a clock signal, the second latch unit is configured to latch or transmit a data signal from the first latch unit under the control of a clock signal, and the inverting drive unit is configured to invert and transmit a data signal from the second latch unit, The second latch unit includes an inverter and a latch circuit according to any one of claims 1 to 12 which are sequentially connected in series between the first latch unit and the inverting driving unit.

20. The dynamic D flip-flop according to claim 19, wherein: The first latch unit includes one of the following: transmission gate; or tri-state gate; or An inverter and a transmission gate are sequentially connected in series between the data input terminal and the second latch unit.

21. A register, characterized in that: The registers include: A plurality of data input terminals configured to receive data signals; A plurality of data output terminals configured to output data signals; A clock control terminal configured to receive a clock signal; a clock buffer configured to buffer a clock signal received by the clock control terminal and provide the clock signal to a plurality of register units; and The plurality of register units are connected in parallel between the plurality of data input terminals and the plurality of data output terminals, and are configured to write and / or read data under the control of a clock signal, Wherein, a register unit among the plurality of register units is a dynamic latch according to claim 13 or 14, or a dynamic D flip-flop according to any one of claims 15 to 20.

22. A processor, characterized in that: The processor comprises a dynamic latch according to claim 13 or 14, or a dynamic D flip-flop according to any one of claims 15 to 20, or a register according to claim 21.

23. A computing device, characterized in that: The computing device comprises a processor according to claim 22.

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