A high-density memory based on vertical channel transistors and its preparation method

Abstract

The present invention proposes a high-density memory based on vertical channel transistors and a preparation method thereof, comprising a 1T1M structure memory cell consisting of a vertical channel field effect transistor (FET) and a magnetic tunnel junction (MTJ); the vertical channel FET is a FET based on a surround gate GAA configuration; the vertical channel FET effect transistor is stacked directly above the magnetic tunnel junction (MTJ); the memory cell uses the upper vertical channel FET transistor as a driving transistor, and the lower magnetic tunnel junction (MTJ) stores the memory cell state, and by controlling the current size and direction of the driving transistor, the magnetization reversal state of the free layer of the magnetic tunnel junction (MTJ) is regulated to realize data reading, erasing and writing; the present invention uses a surround gate (GAA) configuration vertical channel FET and a magnetic tunnel junction (MTJ) for vertical stacking, and its size can be miniaturized to 4F 2 , which can achieve MRAM with higher integration density.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor device manufacturing, in particular to a high-density memory based on vertical channel transistors and a preparation method thereof. Background Art

[0002] Magnetic random access memory (MRAM) is a non-volatile random access memory technology in which data is stored by magnetic storage elements. These elements are typically formed by two ferromagnetic plates, each of which can maintain magnetization, separated by a thin dielectric layer (i.e., a tunnel barrier). One of the two plates is a permanent magnet set to a specific polarity (i.e., the magnetic reference layer); the magnetization of the other plate can be changed to match the magnetization of the external field used to store the memory (i.e., the magnetic free layer). This configuration is called a magnetic tunnel junction (MTJ) column. The MTJ is connected to a transistor to form a single memory cell 1T1M. The traditional 1T1M structure has a large area (6-14F). 2 ) and low integration density. In the post-Moore era of integrated circuits, three-dimensional integration is the general trend. Therefore, it is necessary to provide a more effective technical solution to increase the integration density of MRAM. Summary of the Invention

[0003] The present invention proposes a high-density memory based on vertical channel transistors and its preparation method, which uses vertical channel FETs with a gate-all-around (GAA) structure and magnetic tunnel junctions (MTJs) for vertical stacking, and its size can be miniaturized to 4F. 2 , which can achieve MRAM with higher integration density.

[0004] The present invention adopts the following technical solutions.

[0005] A high-density memory based on vertical channel transistors, comprising a 1T1M structured memory cell consisting of a vertical channel field effect transistor (FET) and a magnetic tunnel junction (MTJ); the vertical channel FET is a FET based on a gate-all-around (GAA) configuration; the vertical channel FET is stacked directly above the magnetic tunnel junction (MTJ);

[0006] The memory cell uses the upper vertical channel FET transistor as the driving transistor, and the lower magnetic tunnel junction MTJ stores the memory cell state. By controlling the current size and direction of the driving transistor, the magnetization reversal state of the magnetic tunnel junction MTJ free layer is regulated to realize data reading, erasing and writing.

[0007] The area of ​​the memory unit is 4F 2 .

[0008] The magnetic tunnel junction MTJ is a multi-layer stacked magnetic structure grown on a Si / SiO2 material substrate (1), and the vertical channel field effect transistor FET is a vertical channel FET with a surround gate structure prepared above the MTJ.

[0009] The magnetic tunnel junction MTJ comprises a first passivation layer (6) formed on a substrate by a micro-nano processing process, and a pinning layer (2), a reference layer (3), a barrier layer (4), and a free layer (5) distributed from bottom to top on the substrate beside the first passivation layer.

[0010] The vertical channel FET with a surround gate configuration comprises a source electrode (7), a second passivation layer (8), a gate electrode (9), a third passivation layer (10), a gate dielectric layer (11), a channel layer (12), a filling layer (13), and a drain electrode (14) distributed from bottom to top.

[0011] The second passivation layer contacts the first passivation layer and the source electrode; and the third passivation layer contacts the second passivation layer and the gate electrode.

[0012] A method for preparing a high-density memory based on a vertical channel transistor is used to prepare the high-density memory based on a vertical channel transistor described above, and is characterized in that the method for preparing the memory comprises the following steps:

[0013] Step S1: cleaning the Si / SiO2 insulating substrate;

[0014] Step S2: growing an MTJ thin film stack on a substrate by magnetron sputtering, specifically including a pinning layer, a reference layer, a barrier layer, and a free layer;

[0015] Step S3: Spin-coating photoresist on the basis of step S2 to define the etching area by electron beam lithography, and etching out the cylindrical magnetic tunnel junction by dry etching;

[0016] Step S4: depositing a first passivation layer by physical vapor deposition based on step S3, and then removing the photoresist mask and the passivation layer thereon;

[0017] Step S5: Based on step S4, a vertical channel FET source layer is prepared by magnetron sputtering as a source electrode, and the source electrode contacts the free layer of the MTJ;

[0018] Step S6: depositing a second passivation layer by physical vapor deposition based on step S5;

[0019] Step S7: Based on step S6, a vertical channel FET gate layer is prepared by magnetron sputtering to serve as a gate;

[0020] Step S8: depositing a third passivation layer (10) by physical vapor deposition based on step S7;

[0021] Step S9: Based on step S8, spin-coating photoresist on the third passivation layer and defining the etching area by electron beam lithography, etching the groove by dry etching, and then removing the photoresist mask;

[0022] Step S10: depositing a gate dielectric layer on the surface and sidewalls of the groove using atomic layer deposition based on step S9;

[0023] Step S11: Based on step S10, spin-coating photoresist on the gate dielectric layer and using electron beam lithography to define an etching area, etching a dielectric layer window at the bottom of the groove by dry / wet etching, and then removing the photoresist mask;

[0024] Step S12: Based on step S11, a channel layer (12) is deposited on the surface and sidewall of the groove by atomic layer deposition;

[0025] Step S13: Based on step S12, a filling layer (13) is deposited inside the groove by atomic layer deposition;

[0026] Step S14: Based on step S13, magnetron sputtering is used on the channel layer and the filling layer to prepare a vertical channel FET drain layer as a drain.

[0027] The pinning layer material in step S2 includes Ru, Co, [Pt / Co] x , Pt, Ta; the reference layer materials include CoFeB, Ta, W, [Co / Pt] x , Co; the barrier layer material is MgO; the free layer material includes: MgO, CoFeB, Ta;

[0028] In steps S4, S6 and S8, the materials of the first passivation layer, the second passivation layer and the third passivation layer are SiN, SiO2 or Al2O3;

[0029] The source layer and the drain layer in steps S5 and S14 are made of Ti, Pt, Au or ITO;

[0030] The gate material in step S7 is Ni, Pt, Au, polycrystalline Si or ITO;

[0031] The gate dielectric layer in step S10 includes Al2O3, HfO2, ZrO2, La2O3, HfAlO x 、HfSiO x 、HfLaO x 、HfZrO x , one or more of HfSiON;

[0032] In step S12, the channel layer material is a semiconductor material, including an oxide semiconductor, polycrystalline silicon or amorphous silicon; the oxide semiconductor is zinc oxide ZnO, indium oxide In2O3, tin oxide SnO2, gallium oxide Ga2O3, indium gallium zinc oxide IGZO, indium tin oxide ITO or indium zinc oxide IZO;

[0033] In step S13, the filling layer material is one or more of SiN, SiO2, and Al2O3.

[0034] The first passivation layer forms an isolation structure at the sidewall of the magnetic tunnel junction MTJ, the second passivation layer forms an isolation structure between the gate and the source, and the third passivation layer forms an isolation structure between the gate and the drain.

[0035] The transistor channel of the high-density memory based on the vertical channel transistor is prepared using an oxide semiconductor material with wide bandgap, high mobility, low off-state current and low deposition temperature.

[0036] The present invention adopts a vertical channel FET with a gate-all-around (GAA) structure and a magnetic tunnel junction (MTJ) for vertical stacking, so that the 1T1M structure formed by the present invention has a smaller occupied area (4F) compared with the traditional 1T1M. 2 ), which can improve integration and storage density.

[0037] The present invention uses oxide semiconductor as the channel material of the transistor. Since oxide semiconductor has the advantages of wide bandgap, high mobility, low off-state current, and low deposition temperature, it can meet the requirements of high-performance display driving and three-dimensional stacked storage. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] The present invention is further described in detail below with reference to the accompanying drawings and specific embodiments:

[0039] Attachment Figure 1 To the attached Figure 13 The following is a schematic flow chart of the steps of the preparation process of the present invention, wherein:

[0040] Attachment Figure 1 This is a schematic diagram of the MTJ thin film stack structure grown on a substrate according to the present invention;

[0041] Attachment Figure 2 Schematic diagram of the etched columnar MTJ structure of the present invention;

[0042] Attachment Figure 3 This is a schematic diagram of the device structure after depositing the first passivation layer of the present invention;

[0043] Attachment Figure 4 This is a schematic diagram of the device structure after source electrode deposition according to the present invention;

[0044] Attachment Figure 5This is a schematic diagram of the device structure after depositing the second passivation layer of the present invention;

[0045] Attachment Figure 6 This is a schematic diagram of the device structure after gate deposition in the present invention;

[0046] Attachment Figure 7 This is a schematic diagram of the device structure after depositing the third passivation layer of the present invention;

[0047] Attachment Figure 8 This is a schematic diagram of the device structure after etching the channel groove in the present invention;

[0048] Attachment Figure 9 This is a schematic diagram of the device structure after the gate dielectric layer is deposited according to the present invention;

[0049] Attachment Figure 10 This is a schematic diagram of the device structure after etching the gate dielectric window in the present invention;

[0050] Attachment Figure 11 This is a schematic diagram of the device structure after the channel layer is deposited according to the present invention;

[0051] Attachment Figure 12 This is a schematic diagram of the device structure after depositing the groove filling layer of the present invention;

[0052] Attachment Figure 13 This is a schematic diagram of the device structure after drain electrode deposition according to the present invention;

[0053] In the figure: 1-Si / SiO2 substrate; 2-pinning layer; 3-reference layer; 4-barrier layer; 5-free layer; 6-first passivation layer; 7-source; 8-second passivation layer; 9-gate; 10-third passivation layer; 11-gate dielectric layer; 12-channel layer; 13-filling layer; 14-drain. DETAILED DESCRIPTION

[0054] As shown in the figure, a high-density memory based on vertical channel transistors includes a 1T1M structured memory cell consisting of a vertical channel field effect transistor (FET) and a magnetic tunnel junction (MTJ); the vertical channel FET is a FET based on a gate-all-around (GAA) configuration; the vertical channel FET is stacked directly above the magnetic tunnel junction (MTJ);

[0055] The memory cell uses the upper vertical channel FET transistor as the driving transistor, and the lower magnetic tunnel junction MTJ stores the memory cell state. By controlling the current size and direction of the driving transistor, the magnetization reversal state of the magnetic tunnel junction MTJ free layer is regulated to realize data reading, erasing and writing.

[0056] The area of ​​the memory unit is 4F 2 .

[0057] The magnetic tunnel junction MTJ is a multi-layer stacked magnetic structure grown on a Si / SiO2 substrate 1, and the vertical channel field effect transistor FET is a vertical channel FET with a surround gate structure prepared above the MTJ.

[0058] The magnetic tunnel junction MTJ includes a first passivation layer 6 formed on a substrate by micro-nano processing technology, and a pinned layer 2, a reference layer 3, a barrier layer 4, and a free layer 5 distributed from bottom to top on the substrate beside the first passivation layer.

[0059] The vertical channel FET with a surround gate configuration includes a source 7, a second passivation layer 8, a gate 9, a third passivation layer 10, a gate dielectric layer 11, a channel layer 12, a filling layer 13, and a drain 14 distributed from bottom to top.

[0060] The second passivation layer contacts the first passivation layer and the source electrode; and the third passivation layer contacts the second passivation layer and the gate electrode.

[0061] A method for preparing a high-density memory based on a vertical channel transistor is used to prepare the high-density memory based on a vertical channel transistor described above, and is characterized in that the method for preparing the memory comprises the following steps:

[0062] Step S1: cleaning the Si / SiO2 insulating substrate;

[0063] Step S2: growing an MTJ thin film stack on a substrate by magnetron sputtering, specifically including a pinning layer, a reference layer, a barrier layer, and a free layer;

[0064] Step S3: Spin-coating photoresist on the basis of step S2 to define the etching area by electron beam lithography, and etching out the cylindrical magnetic tunnel junction by dry etching;

[0065] Step S4: depositing a first passivation layer by physical vapor deposition based on step S3, and then removing the photoresist mask and the passivation layer thereon;

[0066] Step S5: Based on step S4, a vertical channel FET source layer is prepared by magnetron sputtering as a source electrode, and the source electrode contacts the free layer of the MTJ;

[0067] Step S6: depositing a second passivation layer by physical vapor deposition based on step S5;

[0068] Step S7: Based on step S6, a vertical channel FET gate layer is prepared by magnetron sputtering to serve as a gate;

[0069] Step S8: depositing a third passivation layer (10) by physical vapor deposition based on step S7;

[0070] Step S9: Based on step S8, spin-coating photoresist on the third passivation layer and defining the etching area by electron beam lithography, etching the groove by dry etching, and then removing the photoresist mask;

[0071] Step S10: depositing a gate dielectric layer on the surface and sidewalls of the groove using atomic layer deposition based on step S9;

[0072] Step S11: Based on step S10, spin-coating photoresist on the gate dielectric layer and using electron beam lithography to define an etching area, etching a dielectric layer window at the bottom of the groove by dry / wet etching, and then removing the photoresist mask;

[0073] Step S12: Based on step S11, a channel layer 12 is deposited on the surface and sidewalls of the groove by using atomic layer deposition;

[0074] Step S13: Based on step S12, a filling layer (13) is deposited inside the groove by atomic layer deposition;

[0075] Step S14: Based on step S13, magnetron sputtering is used on the channel layer and the filling layer to prepare a vertical channel FET drain layer as a drain.

[0076] The pinning layer material in step S2 includes Ru, Co, [Pt / Co] x , Pt, Ta; the reference layer materials include CoFeB, Ta, W, [Co / Pt] x , Co; the barrier layer material is MgO; the free layer material includes: MgO, CoFeB, Ta;

[0077] In steps S4, S6 and S8, the materials of the first passivation layer, the second passivation layer and the third passivation layer are SiN, SiO2 or Al2O3;

[0078] The source layer and the drain layer in steps S5 and S14 are made of Ti, Pt, Au or ITO;

[0079] The gate material in step S7 is Ni, Pt, Au, polycrystalline Si or ITO;

[0080] The gate dielectric layer in step S10 includes Al2O3, HfO2, ZrO2, La2O3, HfAlO x 、HfSiO x 、HfLaO x 、HfZrO x , one or more of HfSiON;

[0081] In step S12, the channel layer material is a semiconductor material, including an oxide semiconductor, polycrystalline silicon or amorphous silicon; the oxide semiconductor is zinc oxide ZnO, indium oxide In2O3, tin oxide SnO2, gallium oxide Ga2O3, indium gallium zinc oxide IGZO, indium tin oxide ITO or indium zinc oxide IZO;

[0082] In step S13, the filling layer material is one or more of SiN, SiO2, and Al2O3.

[0083] The first passivation layer forms an isolation structure at the sidewall of the magnetic tunnel junction MTJ, the second passivation layer forms an isolation structure between the gate and the source, and the third passivation layer forms an isolation structure between the gate and the drain.

[0084] The transistor channel of the high-density memory based on the vertical channel transistor is prepared using an oxide semiconductor material with wide bandgap, high mobility, low off-state current and low deposition temperature.

[0085] Example:

[0086] In this example, the specific operations for preparing the high-density memory are as follows:

[0087] Step 1: Soak the Si / SiO2 substrate in a 50°C acetone solution for half an hour to remove surface organic matter, then soak it in an isopropanol solution for two minutes to remove the residual acetone solution, and finally blow dry the sample surface with a nitrogen gun.

[0088] Step 2: Deposit a multilayer metal including a pinning layer (2), a reference layer (3), a barrier layer (4), and a free layer (5) on the substrate surface by magnetron sputtering to form a 150 nm thick MTJ film stack.

[0089] Step 3: Make a cylindrical magnetic tunnel junction structure, including process steps such as coating, baking, exposure, and etching.

[0090] (1) Spin-coat the mask ZEP electron beam glue based on step 2. The spin-coating parameters are 500 rpm / 5 s + 2000 rpm / 2 min. After spin-coating, bake at 180°C for 3 min.

[0091] (2) Using the Raith150 electron beam exposure system to define the etching area, even if the electron beam glue in the exposure area is deformed;

[0092] (3) Development: The developer is amyl acetate, the development time is 70 s, IPA fixation is 40 s, and nitrogen is blown dry. At this time, the deformed glue in the exposed area is dissolved in the developer, and the glue in the non-exposed area is retained, and the layout pattern is transferred to the sample;

[0093] (4) Ion beam etching (IBE) is used to etch a cylindrical magnetic tunnel junction with a height of 40 nm and a size of 100 nm~5μm.

[0094] Step 4: Based on step 3, an electron beam evaporation coating apparatus is used to deposit a 50 nm first passivation layer to wrap the cylindrical magnetic tunnel junction to insulate its sidewalls and facilitate subsequent process steps; the ZEP glue is removed and the passivation layer above the ZEP glue is peeled off in a 100 ° C hot bath in the degumming solution NMP for 1 hour, and finally, it is soaked in IPA for 5 minutes and blown dry with nitrogen.

[0095] Step 5: Prepare a vertical FET source layer above the MTJ free layer, including processes such as coating, baking, exposure, deposition, and mask removal.

[0096] (1) Spin-coat PMMA A4 photoresist based on step 4, with a spin-coating parameter of 3000 rpm / 60 s, and bake at 180°C for 90 s after spin-coating;

[0097] (2) Using the Raith150 electron beam exposure system to define the etching area, even if the electron beam glue in the exposure area is deformed;

[0098] (3) Development: The developer is MIBK:IPA 1:3, the development time is 60 s, and the IPA fixation is 30 s. At this time, the deformed glue in the exposed area is dissolved in the developer, and the glue in the non-exposed area is retained, and the layout pattern is transferred to the sample;

[0099] (4) Deposition of a 50 nm source layer using magnetron sputtering;

[0100] (5) Heat the stripping solution NMP at 120 °C for 1 h, then soak it in IPA for 5 min and blow dry with nitrogen.

[0101] Step 6: Prepare the second passivation layer, including processes such as coating, baking, exposure, and deposition.

[0102] (1) Spin-coat PMMA A4 photoresist based on step 5, with a spin-coating parameter of 2000 rpm / 60 s, and bake at 180°C for 90 s after spin-coating;

[0103] (2) Using the Raith150 electron beam exposure system to define the etching area, even if the electron beam glue in the exposure area is deformed;

[0104] (3) Development: The developer is MIBK:IPA 1:3, the development time is 60 s, and the IPA fixation is 30 s. At this time, the deformed glue in the exposed area is dissolved in the developer, and the glue in the non-exposed area is retained, and the layout pattern is transferred to the sample;

[0105] (4) A 100 nm second passivation layer was deposited by magnetron sputtering.

[0106] Step 7: Deposit a vertical channel FET gate layer on top of the second passivation layer. Deposit a 50 nm gate layer using magnetron sputtering as in step 6. Heat the layer in NMP degumming solution at 120°C for 1 hour, soak in IPA for 5 minutes, and blow dry with nitrogen.

[0107] Step 8: Prepare the third passivation layer, including processes such as coating, baking, exposure, and deposition.

[0108] (1) Spin-coat PMMA A4 photoresist based on step 7, with a spin-coating parameter of 3000 rpm / 60 s, and bake at 180°C for 90 s after spin-coating;

[0109] (2) Using the Raith150 electron beam exposure system to define the etching area, even if the electron beam glue in the exposure area is deformed;

[0110] (3) Development: The developer is MIBK:IPA 1:3, the development time is 60 s, and the IPA fixation is 30 s. At this time, the deformed glue in the exposed area is dissolved in the developer, and the glue in the non-exposed area is retained, and the layout pattern is transferred to the sample;

[0111] (4) A 50 nm third passivation layer was deposited using an electron beam evaporation coating apparatus.

[0112] Step 9: Prepare etching grooves, including processes such as coating, baking, exposure, deposition, and stripping.

[0113] (1) Spin-coat ZEP520A photoresist based on step 8, with the spin-coating parameters of 500 rpm / 5 s + 2000 rpm / 2 min, and bake at 180°C for 3 min after spin-coating;

[0114] (2) Using the Raith150 electron beam exposure system to define the etching area, even if the electron beam glue in the exposure area is deformed;

[0115] (3) Development: The developer is amyl acetate, the development time is 70 s, IPA fixation is 40 s, and nitrogen is blown dry. At this time, the deformed glue in the exposed area is dissolved in the developer, and the glue in the non-exposed area is retained, and the layout pattern is transferred to the sample;

[0116] (4) Etch the exposed area using ion beam etching (IBE) and inductively coupled plasma etching (ICP) to a depth of 200-250 nm, that is, etching to the source layer;

[0117] (5) Heat the solution in NMP at 120°C for 1 h, soak it in IPA for 5 min, and blow dry it with nitrogen.

[0118] Step 10: Based on step 9, a high-k dielectric layer is deposited by atomic layer deposition. Atomic layer deposition has the advantage of good sidewall coverage.

[0119] Step 11: Open a window at the bottom of the groove so that the channel layer can contact the source layer, including processes such as coating, baking, exposure, etching, and stripping.

[0120] (1) Spin-coat ZEP520A photoresist based on step 10, with the spin-coating parameters of 500 rpm / 5 s + 2000 rpm / 2 min, and bake at 180°C for 3 min after spin-coating;

[0121] (2) Using the Raith150 electron beam exposure system to define the etching area, even if the electron beam glue in the exposure area is deformed;

[0122] (3) Development: The developer is amyl acetate, the development time is 70 s, IPA fixation is 40 s, and nitrogen is blown dry. At this time, the deformed glue in the exposed area is dissolved in the developer, and the glue in the non-exposed area is retained, and the layout pattern is transferred to the sample;

[0123] (4) Using ICP to etch and open a window at the bottom of the groove;

[0124] (5) Heat the solution in NMP at 120°C for 1 h, soak it in IPA for 5 min, and blow dry it with nitrogen.

[0125] Step 12: Based on step 11, a channel layer is deposited by atomic layer deposition, and the channel layer is in contact with the source layer through a gate dielectric layer window.

[0126] Step 13: Prepare the groove filling layer, including processes such as coating, baking, exposure, deposition, and stripping.

[0127] Step 13 is as follows:

[0128] (1) Spin-coat PMMA A4 photoresist based on step 5, with a spin-coating parameter of 2000 rpm / 60 s, and bake at 180°C for 90 s after spin-coating;

[0129] (2) Using the Raith150 electron beam exposure system to define the etching area, even if the electron beam glue in the exposure area is deformed;

[0130] (3) Development: The developer is MIBK:IPA 1:3, the development time is 60 s, and the IPA fixation is 30 s. At this time, the deformed glue in the exposed area is dissolved in the developer, and the glue in the non-exposed area is retained, and the layout pattern is transferred to the sample;

[0131] (4) depositing the groove filling layer by magnetron sputtering or atomic layer deposition;

[0132] (5) Heat the film in NMP degumming solution at 100 °C for 1 h to remove the photoresist and peel off the filling layer above the film. Finally, soak the film in IPA for 5 min and blow dry with nitrogen.

[0133] Step 14: Based on step S13, a vertical channel FET drain layer is prepared by magnetron sputtering.

Claims

1. A high-density memory based on vertical channel transistors, characterized in that: A memory cell having a 1T1M structure consisting of a vertical channel field effect transistor (FET) and a magnetic tunnel junction (MTJ); wherein the vertical channel field effect transistor (FET) is a FET based on a gate-all-around (GAA) configuration; and wherein the vertical channel field effect transistor (FET) is stacked directly above the magnetic tunnel junction (MTJ). The memory cell uses the vertical channel FET transistor at the top as the driving transistor, and the magnetic tunnel junction MTJ at the bottom stores the memory cell state. By controlling the current size and direction of the driving transistor, the magnetization reversal state of the free layer of the magnetic tunnel junction MTJ is regulated to realize data reading, erasing and writing; The area of ​​the memory unit is 4F 2 ; The magnetic tunnel junction MTJ is a multi-layer stacked magnetic structure grown on a Si / SiO2 substrate (1), and the vertical channel field effect transistor FET is a vertical channel FET with a surround gate structure prepared above the MTJ; The magnetic tunnel junction MTJ comprises a first passivation layer (6) formed on a substrate by a micro-nano processing process, and a pinning layer (2), a reference layer (3), a barrier layer (4), and a free layer (5) distributed from bottom to top on the substrate beside the first passivation layer; The vertical channel FET with a surround gate configuration includes a source electrode (7), a second passivation layer (8), a gate electrode (9), a third passivation layer (10), a gate dielectric layer (11), a channel layer (12), a filling layer (13), and a drain electrode (14) distributed from bottom to top; The second passivation layer contacts the first passivation layer and the source electrode; and the third passivation layer contacts the second passivation layer and the gate electrode.

2. A method for preparing a high-density memory based on vertical channel transistors, characterized in that: Applied to the high-density memory based on vertical channel transistors according to claim 1, the method for preparing the memory comprises the following steps: Step S1: cleaning the Si / SiO2 insulating substrate; Step S2: growing an MTJ thin film stack on a substrate by magnetron sputtering, specifically including a pinning layer, a reference layer, a barrier layer, and a free layer; Step S3: Spin-coating photoresist based on step S2 to define the etching area using electron beam lithography, and dry etching to form a cylindrical magnetic tunnel junction; Step S4: Based on step S3, a first passivation layer is deposited by physical vapor deposition, and then the photoresist mask and the passivation layer thereon are removed; Step S5: Based on step S4, a vertical channel FET source layer is prepared by magnetron sputtering as a source electrode, and the source electrode contacts the free layer of the MTJ; Step S6: depositing a second passivation layer by physical vapor deposition based on step S5; Step S7: Based on step S6, a vertical channel FET gate layer is prepared by magnetron sputtering to serve as a gate; Step S8: Based on step S7, a third passivation layer (10) is deposited by physical vapor deposition; Step S9: Based on step S8, spin-coating photoresist on the third passivation layer and using electron beam lithography to define the etching area, using dry etching to form the groove, and then removing the photoresist mask; Step S10: depositing a gate dielectric layer on the surface and sidewalls of the groove using atomic layer deposition based on step S9; Step S11: Based on step S10, spin-coating photoresist on the gate dielectric layer and using electron beam lithography to define an etching area, etching a dielectric layer window at the bottom of the groove by dry / wet etching, and then removing the photoresist mask; Step S12: Based on step S11, a channel layer (12) is deposited on the surface and sidewall of the groove by atomic layer deposition; Step S13: Based on step S12, a filling layer (13) is deposited inside the groove by atomic layer deposition; Step S14: Based on step S13, magnetron sputtering is used on the channel layer and the filling layer to prepare a vertical channel FET drain layer as a drain.

3. The method for preparing a high-density memory based on vertical channel transistors according to claim 2, wherein: In step S2, the pinning layer material includes Ru, Co, [Pt / Co] x , Pt, Ta; the reference layer materials include CoFeB, Ta, W, [Co / Pt] x , Co; the material of the barrier layer is MgO; The materials of the free layer include: MgO, CoFeB, Ta; In steps S4, S6 and S8, the materials of the first passivation layer, the second passivation layer and the third passivation layer are SiN, SiO2 or Al2O3; In steps S5 and S14, the source layer and the drain layer are made of Ti, Pt, Au or ITO; In step S7, the gate material is Ni, Pt, Au, polycrystalline Si or ITO; In step S10, the material of the gate dielectric layer includes Al2O3, HfO2, ZrO2, La2O3, HfAlO x 、HfSiO x 、HfLaO x 、HfZrO x , one or more of HfSiON; In step S12, the material of the channel layer is a semiconductor material, including oxide semiconductor, polycrystalline silicon or amorphous silicon; the oxide semiconductor is zinc oxide ZnO, indium oxide In2O3, tin oxide SnO2, gallium oxide Ga2O3, indium gallium zinc oxide IGZO, indium tin oxide ITO or indium zinc oxide IZO; In step S13, the material of the filling layer is one or more of SiN, SiO2, and Al2O3.

4. The method for preparing a high-density memory based on vertical channel transistors according to claim 2, wherein: The first passivation layer forms an isolation structure at the sidewall of the magnetic tunnel junction MTJ, the second passivation layer forms an isolation structure between the gate and the source, and the third passivation layer forms an isolation structure between the gate and the drain.

5. The method for preparing a high-density memory based on vertical channel transistors according to claim 2, wherein: The transistor channel of the high-density memory based on the vertical channel transistor is made of oxide semiconductor material.

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