Silicon wafer and processing method thereof

Abstract

The present application discloses a silicon wafer and a processing method thereof. The silicon wafer processing method is used for processing a silicon wafer to be processed, and includes: thinning the silicon wafer; annealing the thinned silicon wafer; edge-polishing the annealed silicon wafer, where the annealing time t0 and the annealing temperature T0 satisfy: 3.6 °C / min < T0 / t0 < 5.6 °C / min. Since during the process of CZ silicon crystal growing and cooling to room temperature, due to the growth zone temperature being higher than the nucleation zone, the amount of as-grown oxygen precipitates generated is very small, and most of the oxygen exists in the interstitial state. During the device preparation process, the silicon wafer will experience different times in various different temperature ranges, and the interstitial oxygen in the crystal gradually reaches an equilibrium state, and the supersaturated interstitial oxygen atoms aggregate to form oxygen precipitates. The silicon wafer processing method provided by the present application can increase the density of bulk microdefects in the silicon wafer by annealing the thinned silicon wafer.

Description

Technical Field

[0001] The present application relates to the field of semiconductor manufacturing technology, and in particular to a silicon wafer and a processing method thereof. Background Art

[0002] With the development of the semiconductor industry, the demand for semiconductor material silicon is increasing, and at the same time, higher requirements are placed on the quality and products of silicon. The development of silicon semiconductor materials has entered a mature stage, and its broad application prospects have always attracted much attention at home and abroad. The density of bulk micro defects (BMD) in silicon wafer semiconductors has both beneficial and harmful effects on the yield of components. In the process of manufacturing components, BMD can absorb some metal impurities (such as fast-diffusing elements such as Cu, Fe, and Na), which is referred to as internal impurities. Therefore, how to increase the density of BMD in the process of silicon wafer processing is a problem that needs to be solved urgently. Summary of the invention

[0003] The purpose of the present application is to provide a silicon wafer processing method that can improve the bulk micro-defect density; the present application also provides a silicon wafer that is prepared using the above-mentioned silicon wafer processing method and has a higher bulk micro-defect density.

[0004] The present application provides a method for processing a silicon wafer, which is used to process a silicon wafer to be processed. The processing method includes:

[0005] Performing a thinning process on the silicon wafer;

[0006] Annealing the thinned silicon wafer;

[0007] Performing edge polishing on the silicon wafer after annealing;

[0008] The annealing treatment has an annealing time t 0 , the annealing treatment has an annealing temperature T 0 , meet: 3.6℃ / min <T 0 / t 0 <5.6℃ / min.

[0009] In some embodiments, the annealing time t 0 The range is 120~180min.

[0010] In some embodiments, the annealing treatment has an annealing temperature T 0 , the annealing temperature T 0 The range is 655~665℃.

[0011] In some embodiments, after the silicon wafer is thinned, the method further comprises:

[0012] Cleaning the silicon wafer after thinning;

[0013] The cleaned silicon wafer is placed in an annealing furnace, and the annealing furnace is heated from a first temperature T 1 Heating to annealing temperature T 0 .

[0014] In some embodiments, the first temperature T 1 The range is 600~620℃.

[0015] In some embodiments, the heating time is 3 to 8 minutes.

[0016] In some embodiments, the heating rate is 1-5°C / min.

[0017] In some embodiments, before the annealed silicon wafer is subjected to edge polishing, the method further comprises:

[0018] The annealing furnace is set to the annealing temperature T 0 Cool down to the second temperature T 2 ;

[0019] The silicon wafer after annealing is cleaned after annealing.

[0020] In some embodiments, the second temperature T 2 The range is 600~620.

[0021] In some embodiments, the cooling time is 3 to 8 minutes.

[0022] In some embodiments, the cooling rate is 3-8°C / min.

[0023] In some embodiments, the annealing treatment has an annealing time t 0 , the thinning process has a thinning time t 3 The side throwing process has a side throwing time t 4 , satisfying: t 3 ≤t 4 <t 0 .

[0024] In some embodiments, the thinning time t 3 The range is 3 to 5 minutes.

[0025] In some embodiments, the side throw time t 4 The range is 5 to 8 minutes.

[0026] In some embodiments, before the silicon wafer is thinned, the method further comprises:

[0027] Using a corrosive liquid to perform corrosion treatment on the silicon wafer;

[0028] The silicon wafer after the etching treatment is cleaned after etching.

[0029] In some embodiments, the etching solution includes hydrofluoric acid, nitric acid and acetic acid; based on the total mass of the etching solution, the mass percentage of the hydrofluoric acid is 20-30%, the mass percentage of the nitric acid is 20-30%, and the mass percentage of the acetic acid is 50-60%.

[0030] In some embodiments, the silicon wafer to be processed is obtained by the following steps:

[0031] Providing silicon source;

[0032] Placing the silicon source in a quartz crucible to perform crystal pulling growth to obtain a crystal rod;

[0033] The crystal rod is cut to obtain the silicon wafer to be processed.

[0034] In some embodiments, the heating power of the quartz crucible is 20-80Kw.

[0035] In some embodiments, the rotation speed of the quartz crucible is 8-20 rpm.

[0036] In some embodiments, the oxygen content of the silicon wafer is 11.8 to 13.9 ppma.

[0037] Accordingly, the present application provides a silicon wafer, which is prepared by the processing method as described above, and the density of the bulk micro defects of the silicon wafer is in the range of 4E9 to 1E10 ea / cm 3 .

[0038] The beneficial effects of this application are:

[0039] It is understandable that in the process of CZ silicon crystal from growth to cooling to room temperature, since the temperature of the growth zone is higher than that of the nucleation zone, the amount of native oxygen precipitate (BMD) generated is very small, and most of the oxygen exists in an interstitial state. In the device preparation process, the silicon wafer will experience different times in various temperature ranges, and the interstitial oxygen in the crystal gradually reaches an equilibrium state, and the supersaturated interstitial oxygen atoms gather to form oxygen precipitates (BMD). The processing method of silicon wafers provided in this application can increase the density of bulk micro defects by annealing the thinned silicon wafers, and by controlling the ratio between the annealing time and temperature to meet the following requirements: 3.6°C / min <T 0 / t 0 <5.6℃ / min, which can further increase the density of micro defects.

[0040] The present application provides a silicon wafer, which is prepared by the silicon wafer processing method as described above, and the density of the bulk micro defects of the silicon wafer is in the range of 4E9 to 1E10 ea / cm 3 , improving the performance of silicon wafer materials. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1 A flow chart of a silicon wafer processing method provided in this application;

[0042] Figure 2 A microscopic image of micro defect density in the silicon wafer prepared in Example 1 provided in the present application;

[0043] Figure 3 A microscopic image of micro defect density in the silicon wafer prepared in Example 7 provided in the present application;

[0044] Figure 4 A microscopic image of micro defect density in the silicon wafer prepared in Example 8 provided in the present application;

[0045] Figure 5 A microscopic image of micro defect density in the silicon wafer prepared in Example 10 provided in the present application;

[0046] Figure 6 A microscopic image of the micro-defect density contained in the silicon wafer prepared in Comparative Example 1 provided in the present application. DETAILED DESCRIPTION

[0047] The technical solution of the present application will be described clearly and completely below in conjunction with the embodiments and drawings of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application. The various embodiments of the present application may exist in the form of a range; it should be understood that the description in the form of a range is only for convenience and simplicity, and should not be understood as a rigid limitation on the scope of the present application; therefore, it should be considered that the range description has specifically disclosed all possible sub-ranges and single values ​​within the range. For example, it should be considered that the range description from 1 to 6 has specifically disclosed sub-ranges, such as from 1 to 3, from 1 to 4, from 1 to 5, from 2 to 4, from 2 to 6, from 3 to 6, etc., as well as single numbers within the range, such as 1, 2, 3, 4, 5 and 6, which are applicable regardless of the range. In addition, whenever a numerical range is indicated in this article, it is meant to include any quoted numbers (fractions or integers) within the indicated range.

[0048] like Figure 1 As shown, a silicon wafer processing method is used to process the silicon wafer to be processed, and the processing method includes:

[0049] Step S1: thinning the silicon wafer;

[0050] Step S2: annealing the thinned silicon wafer;

[0051] Step S3: polishing the annealed silicon wafer; the annealing treatment has an annealing time t 0 , the annealing treatment has an annealing temperature T 0 , meet: 3.6℃ / min <T 0 / t 0 <5.6℃ / min. Specifically, T 0 / t 0 The value (in °C / min) can be any one of 3.64, 3.8, 4.0, 4.2, 4.4, 4.6, 4.8, 5.0, 5.2, 5.4, 5.54, or a range consisting of any two of them.

[0052] It is understandable that in the process of CZ (Czochralski) silicon crystal from growth to cooling to room temperature, since the temperature of the growth zone is higher than that of the nucleation zone, the amount of native oxygen precipitate (BMD) generated is very small, and most of the oxygen exists in the interstitial state. In the device preparation process, the silicon wafer will experience different times in various temperature ranges, and the interstitial oxygen in the crystal will gradually reach a state of equilibrium, and the supersaturated interstitial oxygen atoms will gather to form oxygen precipitate (BMD). By annealing the silicon wafer and controlling the ratio between the annealing time and temperature to meet: 3.6℃ / min <T 0 / t 0 <5.6℃ / min, which can increase the density of micro defects, thereby improving the performance of silicon wafer materials, reducing leakage of products made from the silicon wafer, and improving the yield of products.

[0053] In some embodiments, the annealing time t 0 and annealing temperature T 0 , meet: 3.64℃ / min≤T 0 / t 0 ≤5.54℃ / min. Specifically, T 0 / t 0 The value (in °C / min) can be any one of 3.64, 3.8, 4.0, 4.2, 4.4, 4.6, 4.8, 5.0, 5.2, 5.4, 5.54, or a range consisting of any two of them.

[0054] In some embodiments, the annealing time t 0 The range of annealing time is 120 to 180 min. 0The time may be any one of 120 min, 130 min, 140 min, 150 min, 160 min, 170 min, and 180 min, or a range consisting of any two of them.

[0055] It can be understood that at the annealing temperature T 0 Under the same conditions, by extending the annealing time t 0 , can increase the density of micro defects in silicon wafers. When the annealing time t 0 After reaching a certain value, as the annealing time t 0 With the extension of the time, the density of bulk micro-defects in the silicon wafer no longer changes.

[0056] In some embodiments, the annealing temperature T 0 The range of annealing temperature is 655-665°C. 0 The temperature may be any one of 655°C, 656°C, 657°C, 658°C, 659°C, 660°C, 661°C, 662°C, 663°C, 664°C, and 665°C, or any combination of the two.

[0057] In some embodiments, after the silicon wafer is thinned, the method further comprises:

[0058] Cleaning the silicon wafer after thinning;

[0059] The cleaned silicon wafer is placed in an annealing furnace, and the annealing furnace is heated from a first temperature T 1 Heating to annealing temperature T 0 .

[0060] It is understandable that the product yield of the silicon wafer can be improved by first cleaning the thinned silicon wafer to remove impurities on the surface of the silicon wafer and then annealing the silicon wafer.

[0061] In some embodiments, the first temperature T 1 The range of the first temperature T is 600-620°C. 1 The temperature may be any one of 600°C, 605°C, 610°C, 615°C, and 620°C, or a range consisting of any two of them.

[0062] In some embodiments, the heating time is 3 to 8 minutes. Specifically, the heating time is any one of 3 minutes, 4 minutes, 5 minutes, 6 minutes, 7 minutes, and 8 minutes, or any two of them.

[0063] In some embodiments, the heating rate is 1-5°C / min. Specifically, the heating rate is any one of 1°C / min, 2°C / min, 3°C / min, 4°C / min, 5°C / min, or any two of them.

[0064] It is understandable that the heating rate will affect the surface stress of the silicon wafer. The present application can reduce the surface stress of the silicon wafer and improve the product yield of the silicon wafer by controlling the heating rate to 1-5°C / min.

[0065] In some embodiments, before the annealed silicon wafer is subjected to edge polishing, the method further comprises:

[0066] The annealing furnace is set at annealing temperature T 0 Cool down to the second temperature T 2 ;

[0067] The annealed silicon wafer is cleaned after annealing.

[0068] It is understandable that the product yield of the silicon wafer can be improved by cleaning the annealed silicon wafer after annealing to remove impurities on the surface of the silicon wafer and then polishing the silicon wafer.

[0069] In some embodiments, the second temperature T 2 The range of the second temperature T is 600-620°C. 2 The range is any one of 600, 605°C, 610°C, 615°C, and 620°C, or a range consisting of any two of them.

[0070] In some embodiments, the cooling time is 3 to 8 minutes. Specifically, the cooling time can be any one of 3 minutes, 4 minutes, 5 minutes, 6 minutes, 7 minutes, and 8 minutes, or any two of them.

[0071] In some embodiments, the cooling rate is 3-8°C / min. Specifically, the cooling rate can be any one of 3°C / min, 4°C / min, 5°C / min, 6°C / min, 7°C / min, 8°C / min, or any two of them.

[0072] It is understandable that the cooling rate will affect the surface stress of the silicon wafer. The present application can reduce the surface stress of the silicon wafer and improve the product yield of the silicon wafer by controlling the cooling rate to 3-8°C / min.

[0073] In some embodiments, the thinning process has a thinning time t 3 , the side-throwing process has a side-throwing time t 4 , satisfying: t 3 ≤t4 <t 0 .

[0074] It can be understood that by controlling the thinning time t 3 , side throwing time t 4 , annealing time t 0 Satisfy: t 3 ≤t 4 <t 0 , which can increase the density of micro defects, thereby improving the performance of silicon wafer materials, reducing leakage of products made from the silicon wafer, and thus improving the yield of the products.

[0075] In some embodiments, the thinning time t 3 The range of thinning time is 3 to 5 minutes. 3 The time period may be any one of 3 min, 4 min, and 5 min, or any two of them.

[0076] In some embodiments, the side throw time t 4 The range of the side throwing time t is 5 to 8 minutes. 4 The time period may be any one of 5 min, 6 min, 7 min, and 8 min, or a range consisting of any two of them.

[0077] In some embodiments, before thinning the silicon wafer, the method further includes:

[0078] The silicon wafer is corroded by using a corrosive liquid;

[0079] The silicon wafer after etching is cleaned after etching.

[0080] It is understandable that the product yield of the silicon wafer can be improved by using a corrosive solution to corrode the silicon wafer, removing the damaged layer on the surface of the silicon wafer, and then performing post-corrosion cleaning on the corroded silicon wafer.

[0081] In some embodiments, the etching solution includes hydrofluoric acid, nitric acid and acetic acid; based on the total mass of the etching solution, the mass percentage of hydrofluoric acid is 20-30%, the mass percentage of nitric acid is 20-30%, and the mass percentage of acetic acid is 50-60%. Specifically, the mass percentage of hydrofluoric acid can be any one of 20%, 21%, 22%, 23%, 24%, 25%, 26%, 27%, 28%, 29%, 30%, or any two of them; the mass percentage of nitric acid can be any one of 20%, 21%, 22%, 23%, 24%, 25%, 26%, 27%, 28%, 29%, 30%, or any two of them; the mass percentage of acetic acid can be any one of 50%, 51%, 52%, 53%, 54%, 55%, 56%, 57%, 58%, 59%, 60%, or any two of them.

[0082] It can be understood that the nitric acid in the etching solution reacts with the silicate in the silicon wafer to form silicon dioxide and nitrogen oxides, the hydrofluoric acid in the etching solution reacts with silicon dioxide, and the acetic acid in the etching solution acts as a buffer to adjust the concentration of nitric acid and hydrofluoric acid to control the etching rate of the silicon wafer.

[0083] In some embodiments, the silicon wafer to be processed is obtained by the following steps:

[0084] Providing silicon source;

[0085] Placing a silicon source in a quartz crucible and performing crystal pulling growth to obtain a crystal rod;

[0086] The crystal rod is cut to obtain silicon wafers to be processed.

[0087] It is understandable that when a silicon source is placed in a quartz crucible for crystal pulling growth, oxygen in the air will enter the interior of the single crystal and be located in the interstitial position.

[0088] In some embodiments, the silicon source includes polycrystalline silicon.

[0089] In some embodiments, the heating power of the quartz crucible is 20-80Kw. Specifically, the heating power of the quartz crucible can be any one of 20Kw, 30Kw, 40Kw, 50Kw, 60Kw, 70Kw, and 80Kw, or any two of them.

[0090] It can be understood that the heating power of the quartz crucible affects the heating temperature of the quartz crucible, that is, the temperature of single crystal growth, and the temperature of single crystal growth affects the oxygen content in the single crystal. The present application controls the heating power of the quartz crucible to 20~80Kw, so that the heating temperature of the quartz crucible is suitable for single crystal growth and the oxygen content in the single crystal is increased.

[0091] In some embodiments, the rotation speed of the quartz crucible is 8-20 rpm. Specifically, the rotation speed of the quartz crucible is any one of 8 rpm, 10 rpm, 12 rpm, 14 rpm, 16 rpm, 18 rpm, and 20 rpm, or any two of them.

[0092] It is understandable that the rotation speed of the quartz crucible affects the oxygen content in the single crystal. The present application can increase the oxygen content in the single crystal by controlling the rotation speed of the quartz crucible to 8-20 rpm.

[0093] In some embodiments, the oxygen content of the silicon wafer is 11.8 to 13.9 ppma. Specifically, the oxygen content of the silicon wafer is in the range of any one of 11.8 ppma, 11.9 ppma, 12.0 ppma, 12.1 ppma, 12.2 ppma, 12.3 ppma, 12.4 ppma, 12.5 ppma, 12.6 ppma, 12.7 ppma, 12.8 ppma, 12.9 ppma, 13.0 ppma, 13.1 ppma, 13.2 ppma, 13.3 ppma, 13.4 ppma, 13.5 ppma, 13.6 ppma, 13.7 ppma, 13.8 ppma, and 13.9 ppma, or any two of the above.

[0094] It is understandable that in the process of CZ (Czochralski) silicon crystal from growth to cooling to room temperature, since the temperature of the growth zone is higher than that of the nucleation zone, the amount of native oxygen precipitate (BMD) generated is very small, and most of the oxygen exists in the interstitial state. In the device preparation process, the silicon wafer will experience different times in various temperature ranges, and the interstitial oxygen in the crystal will gradually reach a state of equilibrium, and the supersaturated interstitial oxygen atoms will gather to form oxygen precipitates (BMD). Therefore, the oxygen content of the silicon wafer will also affect the density of the final oxygen precipitate.

[0095] Accordingly, the present application also provides a silicon wafer, which is prepared by the processing method as described above, and the density of the micro defects of the silicon wafer is in the range of 4E9 to 1E10 ea / cm 3 Specifically, the density of micro defects in the silicon wafer can be 4E9ea / cm 3 、5E9ea / cm 3 、6E9ea / cm 3 、7E9ea / cm 3 、8E9ea / cm 3 、9E9ea / cm 3 、1E10ea / cm 3 The range consisting of any one or any two of the .

[0096] Example 1

[0097] Providing polycrystalline silicon; placing the polycrystalline silicon in a quartz crucible to perform crystal pulling and growth to obtain a crystal rod; cutting the crystal rod to obtain a silicon wafer to be processed; using an etching solution to corrode the silicon wafer, the etching solution comprising 25wt% hydrofluoric acid, 25wt% nitric acid and 50wt% acetic acid; cleaning the silicon wafer after the etching treatment; performing a thinning treatment on the silicon wafer; cleaning the silicon wafer after the thinning treatment; placing the cleaned silicon wafer in an annealing furnace, and heating the annealing furnace from a first temperature T 1 Heating to annealing temperature T 0 , annealing the silicon wafer; the annealing furnace is set at an annealing temperature T 0 Cool down to the second temperature T 2 ; Clean the annealed silicon wafer after annealing. Polish the annealed silicon wafer.

[0098] Embodiments 2 to 7

[0099] The processing methods of Examples 2 to 7 are the same as those of Example 1, except that the annealing time t is adjusted. 0 .

[0100] Embodiments 8 to 12

[0101] The processing methods of Examples 8 to 12 are the same as those of Example 1, except that the heating power of the quartz crucible is adjusted.

[0102] Embodiments 13 to 17

[0103] The processing methods of Examples 13 to 17 are the same as those of Example 1, except that the rotation speed of the quartz crucible is adjusted.

[0104] Comparative Example 1

[0105] Comparative Example 1 is processed in the same manner as Example 1, except that the annealing time t 0 For 40 minutes.

[0106] Comparative Example 2

[0107] Comparative Example 2 is processed in the same manner as Example 1, except that the annealing time t 0 For 100 minutes.

[0108] Comparative Example 3

[0109] Comparative Example 3 is processed in the same manner as Example 1, except that the annealing time t 0 For 200 minutes.

[0110] Test method:

[0111] 1. Measurement method of oxygen content in silicon wafers

[0112] When infrared light of a certain frequency is focused and irradiated on the sample to be analyzed, if the vibration frequency of a certain group in the substance is the same as the frequency of the irradiated infrared light, it will resonate and absorb infrared light of a certain frequency. If the light is recorded by an instrument, a spectrum that fully reflects the characteristics of the sample's components can be obtained, and the composition and concentration of the substance can be obtained.

[0113] 2. Measurement method of bulk micro defect (BMD) density in silicon wafers

[0114] The phenomenon that infrared light can pass through silicon is used. When the infrared light encounters defects in the silicon body, it is scattered. The scattered light is emitted from the cross-section of the silicon wafer, and the defect density is obtained after signal processing.

[0115] Table 1 shows the parameter settings and test results of Examples 1 to 17 and Comparative Examples 1 to 3

[0116]

[0117]

[0118] Results Analysis

[0119] It can be seen from the test results of Examples 1 to 7, Comparative Examples 1 to 3 and Table 1 that the body micro defect density in the silicon wafer can be increased by extending the annealing time. When the annealing time reaches a certain value, the body micro defect density in the silicon wafer no longer changes with the extension of the annealing time. For details, please refer to Figure 2 , Figure 3 as well as Figure 6 .

[0120] It can be seen from the test results of Examples 1, 8 to 12 and Table 1 that the oxygen content in the formed silicon wafer can be changed by adjusting the heating power of the crucible. For details, please refer to Figure 2 , Figure 4 as well as Figure 5 .

[0121] It can be seen from the test results of Example 1, Examples 13 to 17 and Table 1 that the oxygen content in the formed silicon wafer can be changed by adjusting the rotation speed of the crucible.

[0122] The above is a detailed introduction to the present application. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for technical personnel in this field, according to the idea of ​​the present application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A method for processing a silicon wafer, characterized in that: For processing a silicon wafer to be processed, the processing method comprises: The silicon wafer is thinned; the silicon wafer after thinning is cleaned, and the cleaned silicon wafer is placed in an annealing furnace, and the annealing furnace is heated from a first temperature T1 to an annealing temperature T0; the first temperature T1 is in the range of 600-620° C.; the heating time is 3-8 minutes; Annealing the thinned silicon wafer; cooling the annealing furnace from the annealing temperature T0 to a second temperature T2; the second temperature T2 is in the range of 600-620° C.; and the cooling time is 3-8 minutes; Performing edge polishing on the silicon wafer after annealing; The annealing treatment has an annealing time t0, and the annealing treatment has an annealing temperature T0, which satisfies: 3.6°C / min <T0 / t0<5.6℃ / min; The annealing time t0 is in the range of 120-180 min; the annealing temperature T0 is in the range of 655-665°C to increase the density of micro defects in the silicon wafer; the density of micro defects in the silicon wafer is in the range of 4E9-1E10ea / cm 3 .

2. The method for processing a silicon wafer according to claim 1, characterized in that: The heating rate is 1-5°C / min.

3. The method for processing a silicon wafer according to claim 1, characterized in that: Before the annealed silicon wafer is subjected to edge polishing, the method further comprises: The silicon wafer after annealing is cleaned after annealing.

4. The method for processing a silicon wafer according to claim 1, characterized in that: The cooling rate is 3-8°C / min.

5. The method for processing a silicon wafer according to claim 1, characterized in that: The thinning process has a thinning time t3, and the edge polishing process has an edge polishing time t4, satisfying: t3≤t4 <t0。 6. The method for processing a silicon wafer according to claim 5, characterized in that: The thinning time t3 is in the range of 3 to 5 minutes; and / or, The side throwing time t4 ranges from 5 to 8 minutes.

7. The method for processing a silicon wafer according to claim 1, characterized in that: Before thinning the silicon wafer, the method further comprises: Using a corrosive liquid to perform corrosion treatment on the silicon wafer; The silicon wafer after the etching treatment is cleaned after etching.

8. The method for processing a silicon wafer according to claim 7, characterized in that: The etching solution includes hydrofluoric acid, nitric acid and acetic acid; based on the total mass of the etching solution, the mass percentage of the hydrofluoric acid is 20-30%, the mass percentage of the nitric acid is 20-30%, and the mass percentage of the acetic acid is 50-60%.

9. The method for processing a silicon wafer according to claim 1, characterized in that: The silicon wafer to be processed is obtained by the following steps: Providing silicon source; Placing the silicon source in a quartz crucible to perform crystal pulling growth to obtain a crystal rod; The crystal rod is cut to obtain the silicon wafer to be processed.

10. The method for processing a silicon wafer according to claim 9, characterized in that: The heating power of the quartz crucible is 20-80Kw; and / or, The rotation speed of the quartz crucible is 8-20 rpm.

11. The method for processing a silicon wafer according to claim 1, characterized in that: The oxygen content of the silicon wafer is 11.8-13.9 ppma.

12. A silicon wafer, characterized in that: A silicon wafer is prepared by the processing method as described in any one of claims 1 to 11.

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