Heterojunction bipolar transistor and preparation method thereof, radio frequency amplifier and radio frequency module

Abstract

Embodiments of the present application provide a heterojunction bipolar transistor, a preparation method thereof, a radio frequency amplifier and a radio frequency module. The heterojunction bipolar transistor comprises an isolation region, the isolation region has a substrate and a semiconductor layer stacked on the substrate, the isolation region is further provided with a collector contact layer, the substrate is provided with a back hole corresponding to the collector contact layer, the back hole is provided with a first metal layer electrically connected with the collector contact layer, and the semiconductor layer is provided with an isolation groove around the collector contact layer, and the depth of the isolation groove is greater than or equal to one half of the thickness of the semiconductor layer. In this embodiment, the isolation groove is arranged around the collector contact layer corresponding to the back hole on the semiconductor layer, the leakage path of the device is isolated by the isolation groove, the risk of device leakage of the heterojunction bipolar transistor is reduced, and the product performance of the heterojunction bipolar transistor is improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a heterojunction bipolar transistor, a method for fabricating a heterojunction bipolar transistor, a radio frequency amplifier, and a radio frequency module. Background Technology

[0002] Heterojunction bipolar transistors (HBTs) offer advantages such as high efficiency, high power density, and high linearity, making them widely used in high-frequency applications such as wireless communication, radar, and electronic systems. HBT power devices have a back via on the substrate. During operation, the collector current flows through the collector contact layer to the back via and then to ground. This collector current can leak through the isolation region to the adjacent collector contact layer connected to the back via, resulting in device leakage current. This leakage current affects the radio frequency characteristics of the power device; therefore, reducing leakage current in heterojunction bipolar transistors is a critical technical problem that needs to be solved. Summary of the Invention

[0003] Therefore, in order to overcome at least some of the defects and deficiencies in the prior art, the present invention provides a heterojunction bipolar transistor, a method for fabricating a heterojunction bipolar transistor, an RF amplifier, and an RF module, which can isolate the leakage path of the device and reduce the possibility of device leakage of the heterojunction bipolar transistor.

[0004] Specifically, in one aspect, the heterojunction bipolar transistor provided in the embodiments of the present invention includes an isolation region, the isolation region having a substrate and a semiconductor layer stacked on the substrate, the isolation region further having a collector contact layer, the substrate having a back hole corresponding to the collector contact layer, a first metal layer electrically connected to the collector contact layer being disposed in the back hole, the semiconductor layer having an isolation trench surrounding the collector contact layer, the depth of the isolation trench being greater than or equal to half the thickness of the semiconductor layer, and the thickness of the semiconductor layer being the distance from the surface of the semiconductor layer away from the substrate to the surface of the substrate in contact with the semiconductor layer.

[0005] On the other hand, embodiments of the present invention also provide a method for fabricating a heterojunction bipolar transistor, comprising: step S10: preprocessing an epitaxial structure to obtain a first basic structure, the first basic structure including a device region and an isolation region disposed adjacent to the device region, the isolation region having a substrate and a semiconductor layer stacked on the substrate; step S20: forming an isolation trench on the semiconductor layer and forming a collector contact layer in the isolation region, wherein the isolation trench is disposed around the collector contact layer, and the depth of the isolation trench is greater than or equal to half the thickness of the semiconductor layer, the thickness of the semiconductor layer being the distance from the surface of the semiconductor layer away from the substrate to the surface of the substrate in contact with the semiconductor layer; step S30: forming a back hole on the substrate corresponding to the collector contact layer, and forming a first metal layer connecting the collector contact layer in the back hole.

[0006] In another aspect, embodiments of the present invention also provide a radio frequency amplifier, including the heterojunction bipolar transistor described above.

[0007] In another aspect, embodiments of the present invention also provide a radio frequency module, including the radio frequency amplifier described above.

[0008] As can be seen from the above, the embodiments of the present invention provide an isolation trench around the collector contact layer corresponding to the back hole on the semiconductor layer. The isolation trench can isolate the path between the collector layer of the device region and the collector contact layer of the adjacent connecting back hole, thereby isolating the path of device leakage current, reducing the risk of device leakage current of heterojunction bipolar transistor, and improving the product performance of heterojunction bipolar transistor. Attached Figure Description

[0009] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0010] Figure 1 This is a schematic diagram of a heterojunction bipolar transistor provided in an embodiment of the present invention.

[0011] Figure 2A for Figure 1 Top view of a heterojunction bipolar transistor.

[0012] Figure 2B This is another schematic diagram of a heterojunction bipolar transistor.

[0013] Figure 3 This is a schematic diagram of another heterojunction bipolar transistor provided in an embodiment of the present invention.

[0014] Figure 4 for Figure 3 Top view of a heterojunction bipolar transistor.

[0015] Figures 5A to 5M for Figure 1 A schematic diagram of the fabrication process of a heterojunction bipolar transistor.

[0016] Figures 6A to 6M for Figure 3 A schematic diagram of the fabrication process of a heterojunction bipolar transistor.

[0017]

Main Component Labels

[0018] 01. First chip; 02. Second chip; 03. Cutaway; 100. Base layer; 110. Base contact layer; 200. Emitter layer; 210. Emitter mesa; 220. Emitter contact layer; 101. Device region; 102. Isolation region; 10. Substrate; 20. Semiconductor layer; 21. Buffer layer; 22. Secondary collector layer; 23. Collector layer; 30. Collector contact layer; 40. Back via; 50. Isolation trench; 61. First metal layer; 62. Passivation layer; 70. Second metal layer; 001. First photoresist; 002. Second photoresist; 003. Contact layer receiving trench; 004. Third photoresist; 005. Fourth photoresist. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments described in the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of the present invention.

[0020] It should be noted that all directional indicators (such as up, down, left, right, front, back, top, and bottom) in the embodiments of this invention are only used to explain the relative positional relationship and movement of the components in a specific posture (as shown in the attached figures). If the specific posture changes, the directional indicator will also change accordingly. Furthermore, the term "vertical" in the embodiments and claims refers to an angle of 90° between two components or a deviation of -5° to +5°, and the term "parallel" refers to an angle of 0° between two components or a deviation of -5° to +5°.

[0021] In the embodiments of this invention, descriptions involving "first," "second," etc., are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first" or "second" may explicitly or implicitly include at least one of that feature.

[0022] See Figure 1 The heterojunction bipolar transistor provided in this embodiment of the invention may include, for example, an isolation region 102 and a device region 101, with the device region 101 and the isolation region 102 disposed adjacent to each other. The isolation region 102 has a substrate 10 and a semiconductor layer 20 stacked on the substrate 10, and the isolation region 102 also has a collector contact layer 30. A back hole 40 is provided on the substrate 10 corresponding to the collector contact layer 30, and a first metal layer 61 is disposed within the back hole 40, and the first metal layer 61 is electrically connected to the collector contact layer 30. An isolation trench 50 is provided around the collector contact layer 30, and the isolation trench 50 may be, for example, an annular structure, with the collector contact layer 30 corresponding to the back hole 40 disposed in the middle of the annular structure.

[0023] Device region 101 may, for example, have a substrate 10 and a semiconductor layer 20 stacked on the substrate 10, and device region 101 is also provided with a collector contact layer 30. The substrate 10 and semiconductor layer 20 of device region 101 and isolation region 102 may, for example, have the same layer structure and the same material, and the substrate 10 of device region 101 and isolation region 102 may, for example, be formed simultaneously, that is, the substrate 10 of device region 101 and isolation region 102 are connected substrate 10, and the semiconductor layer 20 of device region 101 and isolation region 102 is also connected semiconductor layer 20. Helium ions may, for example, be implanted into the semiconductor layer 20 of isolation region 102, and isolation region 102 is formed by ion implantation, thereby distinguishing device region 101 and isolation region 102. Semiconductor layer 20 may, for example, include a buffer layer 21, a secondary collector layer 22 and a collector layer 23 sequentially stacked on the substrate 10. The collector contact layer 30 of device region 101 may, for example, be disposed on the upper surface of the secondary collector layer 22 away from the substrate 10. The current output from the collector layer 23 of device region 101 is connected to the back hole 40 through the collector contact layer 30 of isolation region 102 and then grounded through the first metal layer 61.

[0024] When the isolation effect of isolation region 102 is poor, the current output from collector layer 23 will leak through isolation region 102 to collector contact layer 30 of adjacent connection back hole 40, resulting in leakage. By setting isolation trench 50 around collector contact layer 30 corresponding to back hole 40 in semiconductor layer 20, the current leakage path from device region 101 to isolation region 102 can be isolated, preventing the current generated by collector layer 23 of device region 101 from leaking from semiconductor layer 20 to collector contact layer 30 of isolation region 102, reducing the risk of device leakage of heterojunction bipolar transistor, and improving the product performance of heterojunction bipolar transistor.

[0025] Specifically, the depth H of the isolation trench 50 can be, for example, greater than half the thickness of the semiconductor layer 20, where the thickness of the semiconductor layer 20 is the distance from the surface of the semiconductor layer 20 away from the substrate 10 to the surface where the substrate 10 contacts the semiconductor layer 20. For instance, the depth H of the isolation trench 50 can be, for example, two-thirds the thickness of the semiconductor layer 20, meaning the depth H of the isolation trench 50 is the distance from the surface of the semiconductor layer 20 away from the substrate 10 to two-thirds of the thickness of the semiconductor layer 20; the depth H of the isolation trench 50 can also be, for example, the distance from the surface of the semiconductor layer 20 away from the substrate 10 to the surface where the substrate 10 contacts the semiconductor layer 20, i.e., the thickness of the semiconductor layer 20. By setting the depth range of the isolation trench 50 to be greater than or equal to half the thickness of the semiconductor layer 20, poor isolation performance when the isolation trench 50 is shallow can be avoided, preventing partial current leakage and thus affecting the product performance of the heterojunction bipolar transistor. In one embodiment of this example, the groove extends further into the secondary collector layer 22, reaching a depth equal to half the sum of the thicknesses of the secondary collector layer 22 and the buffer layer 21. That is, the distance from the bottom of the groove to the substrate is half the sum of the thicknesses of the secondary collector layer 22 and the buffer layer 21, which has a better effect. It should be noted that the groove can also extend further into the buffer layer 21.

[0026] In one embodiment of this invention, the isolation trench 50 may further extend to the substrate 10, that is, the isolation trench 50 extends below the surface of the substrate 10 that contacts the semiconductor layer 20, and the depth of the isolation trench 50 within the substrate 10 ranges from 0 to 2000 angstroms. 1 Angstrom=10 -10(e.g., 20 angstroms, 500 angstroms, 1000 angstroms, 1500 angstroms, 2000 angstroms, etc.) By extending the isolation trench 50 into the substrate 10, it is possible to further ensure that current does not leak from the semiconductor layer 20 to the collector contact layer 30 of the isolation region 102. By utilizing the non-conductivity of the substrate 10 to isolate the leakage path, the isolation effect of the current leakage path is improved, further reducing the risk of device leakage of the heterojunction bipolar transistor, thereby improving the product performance of the heterojunction bipolar transistor. Furthermore, setting the depth range of the isolation trench 50 within the substrate 10 to 0–2000 angstroms can avoid the impact on the substrate 10 when the depth is too large. In this embodiment, the isolation trench 50 may also be covered with a passivation layer 62, for example.

[0027] In this embodiment, the semiconductor layer 20 may include, for example, a buffer layer 21, a secondary collector layer 22, and a collector layer 23 sequentially stacked on the substrate 10. The substrate 10 is, for example, a GaAs (gallium arsenide) layer, the buffer layer 21 is, for example, a GaAs (gallium arsenide) layer, the secondary collector layer 22 is, for example, a GaAs (gallium arsenide) layer, and the collector layer 23 is, for example, an n-type semiconductor layer. - (n-type lightly doped) GaAs layer. See also Figure 2A and Figure 2B For example, a base layer 100 and an emitter layer 200 may also be disposed on the collector layer 23 of the device region 101. The base layer 100 may include, for example, a base contact layer 110 and a second metal layer 70 disposed on the base contact layer 110. The base contact layer 110 is disposed on the side of the collector layer 23 of the device region 101 away from the substrate 10, and the second metal layer 70 is disposed on the side of the base contact layer 110 away from the substrate 10. The emitter layer 200 may include, for example, an emitter mesa 210, an emitter contact layer 220, and a second metal layer 70. The emitter mesa 210 is disposed on the side of the collector layer 23 of the device region 101 away from the substrate 10, the emitter contact layer 220 is disposed on the side of the base contact layer 110 away from the substrate 10, and the second metal layer 70 is disposed on the side of the emitter contact layer 220 away from the substrate 10. The heterojunction bipolar transistor of this embodiment can refer to the material design of the conventional HBT structure hierarchy, but this embodiment is not limited thereto.

[0028] See Figure 1 and Figure 2AIn the heterojunction bipolar transistor provided in this embodiment, the collector contact layer 30 of the isolation region 102 is disposed on the side of the secondary collector layer 22 away from the substrate 10, that is, the collector contact layer 30 corresponding to the back hole 40 is disposed on the surface of the secondary collector layer 22, and the collector contact layer 30 of the device region 101 is also disposed on the surface of the secondary collector layer 22. An isolation trench 50 is disposed on the semiconductor layer 20 of the isolation region 102, that is, the isolation trench 50 penetrates the collector layer 23, the secondary collector layer 22 and the buffer layer 21, and the isolation trench 50 surrounds the collector contact layer 30, and the isolation trench 50 has a ring structure. The isolation trench 50 can be disposed, for example, on the semiconductor layer 20 between the collector contact layer 30 of the device region 101 and the collector contact layer 30 of the isolation region 102. That is, the isolation trench 50 is disposed in the middle of the leakage path. The isolation trench 50 can isolate the semiconductor layer 20 of the device region 101 and the isolation region 102, thereby isolating the current leakage path from the device region 101 to the collector contact layer 30 of the isolation region 102. This prevents the current generated by the collector layer 23 of the device region 101 from leaking from the semiconductor layer 20 to the collector contact layer 30 of the isolation region 102, reducing the risk of device leakage of the heterojunction bipolar transistor and improving the product performance of the heterojunction bipolar transistor. In this embodiment, the collector layer 23 may, for example, also be provided with a contact layer receiving groove 003. The collector contact layer 30 is disposed at the bottom of the contact layer receiving groove 003. The isolation groove 50 and the contact layer receiving groove 003 may be provided at intervals, and the interval width W2 between the isolation groove 50 and the contact layer receiving groove 003 ranges from 0.5 to 2 micrometers, specifically, for example, 0.5 micrometers, 1 micrometer, 1.7 micrometers, 2 micrometers, etc. By providing an interval between the isolation groove 50 and the contact layer receiving groove 003, the effect on the product can be avoided. Different interval widths can be set according to the influence of different epitaxial thicknesses, thereby preventing the morphology of the collector contact layer 30 from being affected during the etching process of the isolation groove 50. Further, in this embodiment, the width W1 of the isolation groove 50 ranges from 1.5 to 3 micrometers, specifically, for example, 1.5 micrometers, 2 micrometers, 2.8 micrometers, 3 micrometers, etc.

[0029] See Figure 3 and Figure 4In this embodiment of the heterojunction bipolar transistor, the collector contact layer 30 of the isolation region 102 is disposed on the surface of the substrate 10, that is, the collector contact layer 30 corresponding to the back hole 40 is disposed on the surface of the substrate near the semiconductor layer 20, and the collector contact layer 30 of the device region 101 is disposed on the surface of the secondary collector layer 22 away from the substrate 10. In this embodiment, the isolation trench 50 is disposed adjacent to the collector contact layer 30, that is, there is no gap between the isolation trench 50 and the collector contact layer 30. The isolation trench 50 surrounds the collector contact layer 30, and the isolation trench 50 may also be, for example, a ring structure. The isolation trench 50 may be disposed, for example, on the semiconductor layer 20 between the collector contact layer 30 of the device region 101 and the collector contact layer 30 of the isolation region 102. In this embodiment, the semiconductor layer 20 may, for example, also be provided with a contact layer receiving trench 003. The collector contact layer 30 is disposed at the bottom of the contact layer receiving trench 003. The bottom of the contact layer receiving trench 003 is the surface where the substrate 10 contacts the semiconductor layer 20. An isolation trench 50 is formed between the trench wall of the contact layer receiving trench 003 and the collector contact layer 30. That is, the isolation trench 50 is disposed at the end position of the leakage path. By isolating the semiconductor layer 20 of the device region 101 and the collector contact layer 30 of the isolation region 102, the device region 101 to the isolation region 102 can be isolated. The isolation trench 50 is positioned at the end of the leakage path of the collector contact layer 30 of the device region 101 to prevent the current generated by the collector layer 23 of the device region 101 from leaking from the semiconductor layer 20 to the collector contact layer 30 of the isolation region 102. This reduces the risk of device leakage in the heterojunction bipolar transistor and improves the product performance of the heterojunction bipolar transistor. Furthermore, this arrangement simplifies the formation process of the isolation trench 50, improves production efficiency, and allows for different spacing widths W1 to be set according to the influence of different epitaxial thicknesses and the thickness and morphology of the photoresist in the process, thereby enhancing the leakage isolation effect. In this embodiment, the width W1 of the isolation trench 50 ranges from 0.2 to 1 micrometer, specifically, for example, 0.2 micrometers, 0.6 micrometers, 1 micrometer, etc.

[0030] See Figure 2A and Figure 4 The heterojunction bipolar transistor may, for example, include multiple chips, including, for example, a first chip 01 and a second chip 02. A dicing channel 03 may be provided between the first chip 01 and the second chip 02 to separate them. In this embodiment, the distance W3 between the edge of the isolation trench 50 near the dicing channel 03 and the dicing channel 03 is greater than 10 micrometers, specifically, the distance W3 between the outer edge of the isolation trench 50 and the outer edge of the first chip 01 is greater than 10 micrometers, and may be, for example, 10 to 15 micrometers. By positioning the isolation trench 50 away from the dicing channel 03, both process capability requirements can be met while effectively avoiding the impact of the dicing channel 03 during the cutting process.

[0031] This invention also provides a method for fabricating a heterojunction bipolar transistor to prepare the heterojunction bipolar transistor provided in the above embodiments. Specifically, the method for fabricating the heterojunction bipolar transistor provided in this embodiment may include, for example, the following steps:

[0032] Step S10: Preprocess the epitaxial structure to obtain a first basic structure, the first basic structure including an isolation region, the isolation region having a substrate and a semiconductor layer stacked on the substrate;

[0033] Step S20: An isolation trench is formed on the semiconductor layer, and a collector contact layer is formed in the isolation region, wherein the isolation trench is disposed around the collector contact layer, and the depth of the isolation trench is greater than or equal to half the thickness of the semiconductor layer, and the thickness of the semiconductor layer is the distance from the surface of the semiconductor layer away from the substrate to the surface of the substrate in contact with the semiconductor layer;

[0034] Step S30: A back hole corresponding to the collector contact layer is formed on the substrate, and a first metal layer connecting the collector contact layer is formed in the back hole.

[0035] For example, the epitaxial structure includes a substrate 10 and a semiconductor layer 20 stacked on the substrate 10. The semiconductor layer 20 may include, for example, a buffer layer 21, a secondary collector layer 22, and a collector layer 23 sequentially stacked on the substrate 10.

[0036] In one embodiment of this example, step S20 may include, for example, the following steps:

[0037] Step S211: Form an isolation trench in the semiconductor layer;

[0038] Step S212: A contact layer receiving groove is formed on the collector layer, the bottom of the contact layer receiving groove being the surface of the secondary collector layer away from the substrate;

[0039] Step S213: The current collector contact layer is formed on the bottom of the contact layer receiving groove, wherein the isolation groove surrounds the current collector contact layer.

[0040] See Figures 5A to 5M , Figures 5A to 5M for Figure 1 The diagram shows a schematic representation of the fabrication process of a heterojunction bipolar transistor. Figure 5A As shown, the first basic structure is obtained after preprocessing the extensional structure. Figure 5AThis is a schematic diagram of the first basic structure. The first basic structure may, for example, include a device region 101 and an isolation region 102, which are arranged adjacent to each other. The first basic structure here may, for example, be a single, integral structure, where the regions of device region 101 and isolation region 102 are artificially divided. The first basic structure may, for example, include a substrate 10 and a semiconductor layer 20 stacked on the substrate 10. The semiconductor layer 20 may, for example, include a buffer layer 21, a secondary collector layer 22, and a collector layer 23 sequentially stacked on the substrate 10. The isolation region 102 has the substrate 10 and the semiconductor layer 20 stacked on the substrate 10, and the semiconductor layer 20 of the isolation region 102 is implanted with helium ions; similarly, the device region 101 also has a substrate 10 and a semiconductor layer 20 stacked on the substrate 10.

[0041] Then, step S20 is performed: an isolation trench 50 is formed on the semiconductor layer 20 of the first basic structure, and a collector contact layer is formed in the isolation region 102, wherein the isolation trench 50 is disposed around the collector contact layer 30. Specifically, step S20 may include, for example: step S211: forming an isolation trench in the semiconductor layer; step S212: forming a contact layer receiving trench in the collector layer, the bottom of the contact layer receiving trench being the surface of the secondary collector layer away from the substrate; step S213: forming the collector contact layer on the bottom of the contact layer receiving trench, wherein the isolation trench surrounds the collector contact layer.

[0042] Step S211: Form an isolation trench in the semiconductor layer. For example, see... Figure 5B A first photoresist 001 may be coated, for example, on the surface of the semiconductor layer 20 of the first basic structure; see [link / reference]. Figure 5C The first photoresist 001 is photolithographically developed, specifically, for example, at the location where the isolation trench 50 needs to be set; see [link to relevant documentation]. Figure 5D Then, an isolation trench 50 is formed on the semiconductor layer 20 by etching using the first photoresist 001. The isolation trench 50 may be, for example, a ring structure; see [link to documentation]. Figure 5E The first photoresist 001 is removed, thus forming an isolation trench 50 on the semiconductor layer 20. In one embodiment of this example, the depth of the isolation trench 50 may be, for example, the depth of the semiconductor layer 20. In another embodiment of this example, the isolation trench 50 may extend into the substrate 10, that is, the isolation trench 50 extends below the surface of the substrate 10, and the depth of the isolation trench 50 within the substrate 10 ranges from 1000 to 2000 angstroms.

[0043] Step S212: A contact layer receiving trench is formed on the collector layer, the bottom of the contact layer receiving trench being the surface of the secondary collector layer away from the substrate. For example, see... Figure 5F ,exist Figure 5EA second photoresist 002 is then coated onto the surface of the semiconductor layer 20; see [link / reference]. Figure 5G The second photoresist 002 is photolithographically developed. Specifically, photolithography can be performed, for example, at the location where the collector contact layer 30 needs to be set. The photolithographically developed location may include, for example, the corresponding position of the collector contact layer 30 in the device region 101 and the corresponding position of the collector contact layer 30 in the isolation region 102. The corresponding position of the collector contact layer 30 in the isolation region 102 may, for example, be inside the inner circle of the annular structure of the isolation trench 50; see [link to previous section]. Figure 5H Then, the contact layer receiving trench 003 is formed on the semiconductor layer 20 by etching with the second photoresist 002. In this embodiment, the contact layer receiving trench 003 of the device region 101 and the isolation region 102 may be located, for example, on the collector layer 23. The bottom of the contact layer receiving trench 003 is the surface of the secondary collector layer 22 away from the substrate 10.

[0044] Step S213: The current collector contact layer is formed on the bottom of the contact layer receiving groove, wherein the isolation groove surrounds the current collector contact layer. For example, see... Figure 5I For example, the collector contact layer 30 of the device region 101 and the isolation region 102 can be formed on the bottom of the contact layer receiving tank 003 by a metal evaporation process; see Figure 5J The second photoresist 002 is removed to form a collector contact layer 30, wherein the isolation groove 50 surrounds the collector contact layer 30 of the isolation region 102.

[0045] For example, see Figure 5K After step S20, a passivation layer 62 may be deposited, for example, by depositing a passivation layer of silicon nitride to form a protective layer. The passivation layer 62 may be deposited, for example, on the surface of the collector layer 23 and the inner surface of the isolation trench 50, and an opening may be made at the connection of the corresponding collector contact layer 30; see also Figure 5L A second metal layer 70 is formed on the surface of the collector contact layer 30 away from the substrate 10 by a metal interconnect process.

[0046] Then, step S30 is performed: a back hole corresponding to the collector contact layer is formed on the substrate, and a first metal layer connecting the collector contact layer is formed within the back hole. (See also...) Figure 5M On the back side of the substrate 10 away from the semiconductor layer 20, a back hole 40 can be formed, for example, by etching, and a first metal layer 61 can be formed within the back hole 40, for example, by a back gold process. The above steps result in... Figure 1 The heterojunction bipolar transistor structure shown is shown.

[0047] In another embodiment of this example, step S20 may include, for example, the following steps:

[0048] Step S221: A contact layer receiving trench is formed on the semiconductor layer, wherein the bottom of the contact layer receiving trench is the surface of the substrate;

[0049] Step S222: The current collector contact layer is formed on the bottom of the contact layer receiving groove, and the isolation groove is formed between the groove wall of the contact layer receiving groove and the current collector contact layer.

[0050] See Figures 6A to 6K , Figures 6A to 6K for Figure 3 The diagram shows a schematic representation of the fabrication process of a heterojunction bipolar transistor. Figure 6A As shown, the first basic structure is obtained after preprocessing the extensional structure. Figure 6A This is a schematic diagram of the first basic structure. The first basic structure may, for example, include a device region 101 and an isolation region 102, which are arranged adjacent to each other. The first basic structure here may, for example, be a single, integral structure, where the regions of device region 101 and isolation region 102 are artificially divided. The first basic structure may, for example, include a substrate 10 and a semiconductor layer 20 stacked on the substrate 10. The semiconductor layer 20 may, for example, include a buffer layer 21, a secondary collector layer 22, and a collector layer 23 sequentially stacked on the substrate 10. The isolation region 102 has the substrate 10 and the semiconductor layer 20 stacked on the substrate 10; similarly, the device region 101 also has a substrate 10 and the semiconductor layer 20 stacked on the substrate 10.

[0051] Then, step S20 is performed: an isolation trench 50 is formed on the semiconductor layer 20 of the first basic structure, and a collector contact layer is formed in the isolation region 102, wherein the isolation trench 50 is disposed around the collector contact layer 30. Specifically, step S20 may include, for example, step S221: forming a contact layer receiving trench on the semiconductor layer, the bottom of the contact layer receiving trench being the surface of the substrate; step S222: forming the collector contact layer on the bottom of the contact layer receiving trench, and forming the isolation trench between the trench wall of the contact layer receiving trench and the collector contact layer.

[0052] For example, before performing step S20, a collector contact layer 30 may be formed in device region 101. See specifically... Figure 6B A third photoresist 004 may be coated, for example, on the surface of the semiconductor layer 20 of the first basic structure; and the third photoresist 004 may be photolithographically developed, specifically, for example, at the location of the collector contact layer 30 corresponding to the device region 101; see Figure 6CThen, a contact layer receiving trench 003 is formed on the semiconductor layer 20 by etching with a third photoresist 004. In this embodiment, the contact layer receiving trench 003 of the device region 101 may be located, for example, on the collector layer 23, that is, the bottom of the contact layer receiving trench 003 is the surface of the secondary collector layer 22 away from the substrate 10; see also Figure 6D For example, the collector contact layer 30 of the device region 101 can be formed on the bottom of the contact layer receiving tank 003 by a metal evaporation process; see [link to relevant documentation]. Figure 6E The third photoresist 004 is removed to form the collector contact layer 30 of the device region 101.

[0053] Then, a collector contact layer 30 and an isolation trench 50 are formed on the isolation region 102. Specifically, step S221 is first performed: a contact layer receiving trench is formed on the semiconductor layer, the bottom of the contact layer receiving trench being the surface of the substrate. For example, see... Figure 6F ,exist Figure 6E A fourth photoresist 005 is then coated onto the surface of the semiconductor layer 20, and the fourth photoresist 005 is photolithographically developed. Specifically, photolithography can be performed, for example, at the location of the collector contact layer 30 in the isolation region 102; see [link to relevant documentation]. Figure 6G and Figure 6H Then, a contact layer receiving trench 003 is formed on the semiconductor layer 20 by etching with a fourth photoresist 005. In this embodiment, the contact layer receiving trenches 003 of the isolation region 102 may all be located on the semiconductor layer 20, and the bottom of the contact layer receiving trench 003 is the surface of the substrate 10. In this step, it may be formed by a single etching or by multiple etchings. In one embodiment of this embodiment, the depth of the contact layer receiving trench 003 is the same as the depth of the semiconductor layer 20; in another embodiment of this embodiment, the depth of the contact layer receiving trench 003 may extend into the substrate 10, and the depth range of the contact layer receiving trench 003 in the substrate 10 may be, for example, 1000 to 2000 angstroms.

[0054] Then, step S222 is executed: the current collector contact layer is formed on the bottom of the contact layer receiving groove, and the isolation groove is formed between the groove wall of the contact layer receiving groove and the current collector contact layer. For example, see... Figure 6I For example, the collector contact layer 30 of the isolation region 102 can be formed on the bottom of the contact layer receiving tank 003 by a metal evaporation process, and the collector contact layer 30 of the isolation region 102 is located on the surface of the substrate 10; see Figure 6JThe fourth photoresist 005 is removed to form a collector contact layer 30. The collector contact layer 30 may be located, for example, within a contact layer receiving groove 003, and a gap is provided between the edge of the collector contact layer 30 and the groove wall of the contact layer receiving groove 003. The gap is an isolation groove 50, that is, an isolation groove 50 is formed between the groove wall of the contact layer receiving groove 003 and the collector contact layer 30. The isolation groove 50 surrounds the collector contact layer 30 of the isolation area 102, and the isolation groove 50 is arranged adjacent to the collector contact layer 30.

[0055] For example, see Figure 6K After step S20, a passivation layer 62 may be deposited, for example, by depositing a passivation layer of silicon nitride to form a protective layer. The passivation layer 62 may be deposited, for example, on the surface of the collector layer 23 and the inner surface of the isolation trench 50, and an opening may be made at the connection of the corresponding collector contact layer 30; see also Figure 6L A second metal layer 70 is formed on the surface of the collector contact layer 30 away from the substrate 10 by a metal interconnect process.

[0056] Then, step S30 is performed: a back hole corresponding to the collector contact layer is formed on the substrate, and a first metal layer connecting the collector contact layer is formed within the back hole. (See also...) Figure 6M On the back side of the substrate 10 away from the semiconductor layer 20, a back hole 40 can be formed, for example, by etching, and a first metal layer 61 can be formed within the back hole 40, for example, by a back gold process. The above steps result in... Figure 3 The heterojunction bipolar transistor structure shown is shown.

[0057] In summary, the method for fabricating a heterojunction bipolar transistor provided in this embodiment of the invention forms an isolation trench 50 in the semiconductor layer 20 of the isolation region 102, and the isolation trench 50 surrounds the collector contact layer 30 of the isolation region 102. By setting the isolation trench 50 around the collector contact layer 30 corresponding to the back hole 40 in the semiconductor layer 20, the path of current leakage from the device region 101 to the isolation region 102 can be isolated, and the current generated by the collector layer 23 of the device region 101 is prevented from leaking from the semiconductor layer 20 to the collector contact layer 30 of the isolation region 102, thereby reducing the risk of device leakage of the heterojunction bipolar transistor and improving the product performance of the heterojunction bipolar transistor.

[0058] This invention also provides a radio frequency amplifier, which includes a heterojunction bipolar transistor as provided in the above embodiments, or a heterojunction bipolar transistor prepared by the method described in the above embodiments.

[0059] This invention also provides a radio frequency (RF) module, which includes the RF amplifier described in the above embodiments. The RF module can be applied, for example, to mobile phones, base stations, radar, communication systems, or remote sensing applications; however, this embodiment is not limited thereto.

[0060] Furthermore, it is understood that the foregoing embodiments are merely illustrative examples of the present invention. Provided that the technical features do not conflict, the structure is not contradictory, and the purpose of the invention is not violated, the technical solutions of the various embodiments can be arbitrarily combined and used.

[0061] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A heterojunction bipolar transistor, characterized in that, The device includes an isolation region having a substrate and a semiconductor layer stacked on the substrate. The isolation region also has a collector contact layer. The substrate has a back hole corresponding to the collector contact layer. A first metal layer electrically connected to the collector contact layer is disposed in the back hole. The semiconductor layer has an isolation trench around the collector contact layer. The depth of the isolation trench is greater than or equal to half the thickness of the semiconductor layer. The thickness of the semiconductor layer is the distance from the surface of the semiconductor layer away from the substrate to the surface of the substrate in contact with the semiconductor layer.

2. The heterojunction bipolar transistor as described in claim 1, characterized in that, The isolation groove is covered with a passivation layer.

3. The heterojunction bipolar transistor as described in claim 1, characterized in that, The isolation trench extends into the substrate, and the depth of the isolation trench within the substrate ranges from 0 to 2000 angstroms.

4. The heterojunction bipolar transistor as described in claim 1, characterized in that, The semiconductor layer includes a buffer layer, a secondary collector layer, and a collector layer sequentially stacked on the substrate.

5. The heterojunction bipolar transistor as described in claim 4, characterized in that, The collector contact layer is disposed on the side of the secondary collector layer away from the substrate.

6. The heterojunction bipolar transistor as described in claim 5, characterized in that, The current collector layer is further provided with a contact layer receiving groove, the current collector contact layer is disposed at the bottom of the contact layer receiving groove, and the isolation groove is disposed at an interval from the contact layer receiving groove.

7. The heterojunction bipolar transistor as described in claim 6, characterized in that, The spacing between the isolation groove and the contact layer receiving groove ranges from 0.5 to 2 micrometers.

8. The heterojunction bipolar transistor as described in claim 5, characterized in that, The width of the isolation groove ranges from 1.5 to 3 micrometers.

9. The heterojunction bipolar transistor as described in claim 4, characterized in that, The semiconductor layer is further provided with a contact layer receiving groove, the bottom of the contact layer receiving groove is the surface of the substrate in contact with the semiconductor layer, the collector contact layer is disposed at the bottom of the contact layer receiving groove, and the isolation groove is formed between the groove wall of the contact layer receiving groove and the collector contact layer.

10. The heterojunction bipolar transistor as described in claim 9, characterized in that, The width of the isolation groove is 0.2 to 1 micrometer.

11. A method for fabricating a heterojunction bipolar transistor, characterized in that, include: Step S10: Preprocess the epitaxial structure to obtain a first basic structure, the first basic structure including an isolation region, the isolation region having a substrate and a semiconductor layer stacked on the substrate; Step S20: An isolation trench is formed on the semiconductor layer, and a collector contact layer is formed in the isolation region, wherein the isolation trench is disposed around the collector contact layer, and the depth of the isolation trench is greater than or equal to half the thickness of the semiconductor layer, and the thickness of the semiconductor layer is the distance from the surface of the semiconductor layer away from the substrate to the surface of the substrate in contact with the semiconductor layer; Step S30: A back hole corresponding to the collector contact layer is formed on the substrate, and a first metal layer connecting the collector contact layer is formed in the back hole.

12. The method for fabricating a heterojunction bipolar transistor as described in claim 11, characterized in that, The semiconductor layer includes: a buffer layer, a secondary collector layer, and a collector layer sequentially stacked on the substrate; step S20 specifically includes: Step S211: Form an isolation trench in the semiconductor layer; Step S212: A contact layer receiving groove is formed on the collector layer, the bottom of the contact layer receiving groove being the surface of the secondary collector layer away from the substrate; Step S213: The current collector contact layer is formed on the bottom of the contact layer receiving groove, wherein the isolation groove surrounds the current collector contact layer.

13. The method for fabricating a heterojunction bipolar transistor as described in claim 11, characterized in that, Step S20 specifically includes: Step S221: A contact layer receiving trench is formed on the semiconductor layer, wherein the bottom of the contact layer receiving trench is the surface of the substrate; Step S222: The current collector contact layer is formed on the bottom of the contact layer receiving groove, and the isolation groove is formed between the groove wall of the contact layer receiving groove and the current collector contact layer.

14. A radio frequency amplifier, characterized in that, Including the heterojunction bipolar transistor as described in any one of claims 1 to 10.

15. A radio frequency module, characterized in that, Includes the radio frequency amplifier as described in claim 14.

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