A dual-pulse test system and a dual-pulse test failure protection circuit

Abstract

The present invention discloses a dual-pulse test system, which is configured to include: a load inductor, a test power supply is connected to a power device under test through the load inductor; a first freewheeling device, after the power device under test is tested, it forms a freewheeling loop with the load inductor; a pulse generator, which is used to provide the dual pulses required for testing the power device under test; and a failure protection circuit, when the power device under test is in a failure state, it cuts off the test power supply and constructs a freewheeling loop to make the loop current no longer increase. The present invention is configured with a failure protection circuit, which can timely cut off the power supply when the power device under test is in a failure state, and can form a freewheeling loop to realize that the loop current no longer increases, preventing the device from being burned out due to the failure of the power device under test, and playing a protective role.

Description

Technical Field

[0001] The present invention belongs to the field of circuits, and in particular relates to a double-pulse test system and a double-pulse test failure protection circuit. Background Art

[0002] Figure 1 A double-pulse test circuit structure is shown. In the figure, a DC power supply provides a suitable test DC voltage. The capacitor C is used for energy storage to provide a large current for the power device G under the on state of the power device under test. A voltage of 0 to -30V is applied between the GE poles of the power device G1 to make it in the off (cut-off) state. Two positive pulses are applied between the GE poles of the power device G under test for double-pulse test.

[0003] When performing a double-pulse test on a power device, a large voltage and current need to be applied. When the applied voltage and current exceed the maximum voltage and current that the power device can withstand, it will cause the power device to fail, that is, there is a situation of device failure. The failed power device will make the power device in a short-circuit uncontrollable state, resulting in the continuous conduction of the loop composed of the DC power supply, the capacitor C, the load inductor L, and the power device G under test, causing the loop current to continuously increase until the power device under test burns out and opens. After the power device under test is disconnected, the energy stored in the inductor (including the load inductor L and parasitic stray inductance) in the loop will be discharged through the freewheeling diode of G1. Due to the characteristic that the inductor current cannot change suddenly, a relatively high current will flow through G1, which will also pose a risk of overcurrent burnout to G1. The current will continuously increase until the devices in the loop burn out. This uncontrollable state will damage the pulse generation circuit, the drive circuit (the circuit for driving the power device to turn off and on), damage the test equipment, and even cause casualties. Summary of the Invention

[0004] The present invention provides a double-pulse test system, which can timely cut off the circuit when the power device under test fails to avoid the continuous increase of the loop current caused by the failure of the power device under test.

[0005] The double-pulse test system provided by the present invention is configured to include:

[0006] A load inductor, and the test power supply is connected to the power device under test through the load inductor;

[0007] A first freewheeling device, which forms a freewheeling loop with the load inductor after the test of the power device under test is completed;

[0008] A pulse generator, which is used to provide the double pulses required for the test for the power device under test; and

[0009] A failure protection circuit, which cuts off the test power supply when the power device under test is in a failure state and constructs a freewheeling loop to make the loop current no longer increase.

[0010] In some embodiments, the fail-safe circuit is configured to include:

[0011] A first unit, configured to determine whether the power device under test is in a failed state, and generate a control signal when the power device under test is in a failed state;

[0012] A second unit, configured to cut off the power supply connected to the power device under test under the control of the control signal;

[0013] A third unit, when the power device under test is in a failed state, forms a freewheeling circuit with the load inductor and the branch where the power device under test is located, so that there is a freewheeling circuit for the branch where the power device under test is located, the branch where the load inductor is located, and the stray inductance in the fail-safe circuit.

[0014] In some embodiments, the fail-safe circuit is configured to include:

[0015] A first unit, configured to determine whether the power device under test is in a failed state, and generate a control signal when the power device under test is in a failed state;

[0016] A second unit, configured to cut off the power supply connected to the power device under test under the control of the control signal;

[0017] A third unit, when the power device under test is in a failed state, forms a freewheeling circuit with the load inductor, so that the loop current no longer increases.

[0018] In some embodiments, the first unit includes a non-contact current detector for sensing the loop current and an overcurrent detection circuit.

[0019] In some embodiments, the first unit includes a sampling resistor for collecting the loop current and an overcurrent detection circuit.

[0020] The present invention also provides a dual-pulse test fail-safe circuit, which is used to cut off the test power supply connected to the power device under test when the power device under test is in a failed state, and construct a freewheeling circuit so that the loop current no longer increases.

[0021] Advantages of the present invention:

[0022] 1) The present invention configures a fail-safe circuit, which can timely cut off the power supply when the power device under test is in a failed state, and can form a freewheeling circuit to make the loop current no longer increase, preventing the device from being burned out due to the failure of the power device under test, and playing a protective role.

[0023] 2) The present invention configures a fail-safe circuit to form a freewheeling loop with the load inductor L and the branch where the power device G under test is located, enabling a freewheeling loop for the branch where the power device G under test is located, the branch where the load inductor L is located, and the stray inductance in the fail-safe circuit. When the power device under test fails, the stray inductance can be effectively dissipated, improving the stability and reliability of the fail-safe circuit, and thus enhancing the stability of the entire test system.

[0024] 3) The present invention configures non-contact current detection, reducing the design difficulty of the overcurrent detection circuit, increasing the measurement range of the current, and reducing the installation difficulty. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] To more clearly illustrate the embodiments of the present application, the following will briefly introduce the drawings used or involved in the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application. Without creative efforts, other drawings can be obtained based on these drawings:

[0026] Figure 1 It is the schematic diagram of the double-pulse test circuit described in the present invention;

[0027] Figures 2 - 7 It is the schematic diagram of the test system described in the present invention;

[0028] Figure 8 It is the schematic diagram of the overcurrent detection circuit described in the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0029] This part describes the present invention more comprehensively with reference to the drawings, in which illustrative embodiments of the present invention are shown. However, the present invention can be embodied in many different forms and should not be construed as limited to the embodiments described herein. On the contrary, these embodiments are provided so that this disclosure is thorough and complete, and fully conveys the scope of the present invention to those skilled in the art.

[0030] The terms used herein are for the purpose of describing particular embodiments only and are not intended to limit the present invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and "comprising", when used herein, specify the presence of the stated features, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, steps, operations, elements, components, and / or combinations thereof.

[0031] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0032] Figure 1 A dual-pulse test circuit structure is shown. The circuit includes a transistor G1 as the first freewheeling device, a capacitor C, and a load inductor L. The first plate of the capacitor C serves as the first connection terminal of the test circuit for connecting to the positive pole of the power supply DC for testing, and the second plate serves as the second connection terminal of the test circuit for connecting to the negative pole of the power supply DC for testing; the collector of the transistor G1 is connected to the first plate of the capacitor C, and the emitter serves as the third connection terminal of the test circuit for connecting to the power device under test; one end of the load inductor L is connected to the first plate of the capacitor C, and the other end is connected to the emitter of the transistor G1.

[0033] During testing, the collector of the transistor G as the power device under test is connected to the third connection terminal of the test circuit, and the emitter is connected to the second connection terminal of the test circuit. A voltage of 0 to -30V is applied between the BE electrodes of the transistor G1 to turn it off (cut off). The DC power supply is connected to the transistor G through the load inductor L to provide a linear current to slowly access the transistor G. The test process is as follows: First, a positive pulse is applied between the BE of the transistor G to turn it on, and the current flowing through the load inductor L and the transistor G continuously increases. When the current reaches the rated test current, a negative pulse is applied between the BE of the transistor G to turn it off, and the VBE and VCE voltage waveforms of the transistor and the current waveform flowing through the transistor G are captured. Data analysis is performed on the turn-off state of the transistor G at the rated current to evaluate the turn-off characteristics of the transistor G; after the rated turn-off time, a positive pulse is applied between the BE of the transistor G again, and the transistor G is turned on again. Due to the presence of the load inductor L, the current flowing through the transistor G will reach the current value before turn-off again. The VBE and VCE voltage waveforms of the transistor G and the current waveform flowing through the transistor G are captured, and data analysis is performed on the turn-off state of the transistor G at the rated current to evaluate the turn-on characteristics of the transistor; finally, the transistor G is turned off after the rated turn-on time, and the test ends. In addition, by controlling the on-time of the second pulse, the current flowing through the transistor G can be controlled to reach two to three times the rated value (the specific multiple is given according to specific test standards). If the device fails, it can be determined that the device has defects or insufficient performance. This process can be used for the over-current capacity evaluation and performance screening of the transistor G.

[0034] After the test, transistor G is turned off (cut off), and transistor G1 remains in the off state. The current across the load inductor L is consumed by the inter-pole diode between the collector and emitter of transistor G1. The load inductor L and the inter-pole diode form a freewheeling circuit, preventing the current stored in the load inductor L from increasing the current in transistor G and burning out the power device under test.

[0035] In addition, the load inductor L also acts as an analog motor. When the bridge drive circuit composed of transistor G1 and transistor G is applied to drive a motor, the motor is an inductive load. During the test, by configuring the load inductor L, the simulation of the actual device to be driven is realized, improving the test accuracy and the adaptability of the bridge drive circuit composed of transistor G1 and transistor G.

[0036] Figure 1 The first freewheeling device shown in the figure is configured as a transistor. It can be understood that the first freewheeling device can also be configured as a diode, whose cathode is connected to the first electrode plate of the capacitor C, and the anode serves as the second connection terminal of the test circuit.

[0037] The double pulses on the power device under test are generated by a pulse generator, and the pulse signal frequency is set according to the power device under test.

[0038] When performing a double-pulse test on a power device, a large voltage and current need to be applied, and there is a situation where the power device under test fails. The failed power device will put the power device in a short-circuit uncontrollable state, causing the current in the circuit where the power device under test is located to continuously increase and burn out the power device under test. Therefore, this test system is configured with a failure protection circuit that cuts off the power supply when the power device under test is in a failure state and constructs a freewheeling circuit, so that the current in the circuit where the power device under test is located no longer increases, effectively preventing the power device under test from being burned out due to the failure of the power device under test.

[0039] The failure protection circuit configured in this test system includes:

[0040] The first unit is used to determine whether the power device under test is in a failure state and generate a control signal when the power device under test is in a failure state;

[0041] The second unit cuts off the power supply connected to the power device under test under the control of the control signal;

[0042] The third unit forms a freewheeling circuit with the load inductor and the branch where the power device under test is located when the power device under test is in a failure state, so that there is a freewheeling circuit for the branch where the power device under test is located, the branch where the load inductor is located, and the stray inductance in the failure protection circuit; or, the third unit forms a freewheeling circuit with the load inductor when the power device under test is in a failure state, so that the current in the circuit where the power device under test is located no longer increases.

[0043] The test system configured with a fail-safe circuit will be described in detail in conjunction with the following embodiments.

[0044] Embodiment 1

[0045] As Figure 2 , the test system provided in this embodiment includes a capacitor C, a transistor G1 as the first freewheeling device, a load inductor L, and a fail-safe circuit. The first unit in the fail-safe circuit is configured to include a sampling resistor R and an overcurrent detection circuit; the second unit is configured to include a controllable device, here a transistor G2 is configured, and it can also be a thyristor or a diode; the third unit includes a second freewheeling device, here a diode D1 is configured.

[0046] As Figure 2 shown, the first electrode plate of the capacitor C serves as the first connection terminal of the test system for connecting to the positive pole of the test power supply DC, and the second electrode plate serves as the second connection terminal of the test system for connecting to the negative pole of the test power supply DC; the collector of the transistor G1 is connected to the first electrode plate of the capacitor C, and the emitter serves as the third connection terminal of the test system for connecting to the power device under test; one end of the sampling resistor R is connected to the second electrode plate of the capacitor C, and the other end serves as the fourth connection terminal of the test system for connecting to the power device under test; one end of the load inductor L is connected to the emitter of the transistor G1, and the other end is connected to the emitter of the transistor G2. The diode D1 is connected in parallel across the load inductor L; the collector of the transistor G2 is connected to the first electrode plate of the capacitor C, and the base is connected to the output terminal of the overcurrent detection circuit.

[0047] During the test, the collector of the transistor G serving as the power device under test is connected to the third connection terminal of the test system, the emitter is connected to the fourth connection terminal of the test system, and the base is connected to the output terminal of the pulse generator; the pulse signal generated by the pulse generator is applied to the base of the transistor G to control the turn-off (cut-off) and turn-on (conductivity) of the transistor G for double-pulse testing.

[0048] After the power device under test is connected to the test system, a voltage of 0 to -30V is applied between the BE electrodes of the transistor G1 to make it in the off (cut-off) state; the positive and negative poles of the DC power supply are respectively connected to the first connection terminal and the second connection terminal of the test system, and the transistor G2 is in the on (conductive) state. The test power supply provided by the DC power supply is connected to the collector of the transistor G (power device under test) through the transistor G2 and the load inductor L to provide a collector bias signal. The pulse signal is applied to the base of the transistor G to control the turn-off and turn-on of the transistor G; parameters such as the turn-off voltage, turn-on voltage, and inter-electrode voltage when the transistor G is turned off, turned on, or in a holding state are obtained through an external test terminal (such as an oscilloscope) to achieve double-pulse testing of the power device.

[0049] If the power device under test is in a non-failure state, the sampling resistor R obtains Figure 2In the circuit within the dashed-line box, the current input of the circuit is connected to an overcurrent detection circuit. The control signal output by the overcurrent detection circuit is connected to transistor G2 to keep the transistor in an open (conductive) state. After the test is completed, the DC power supply is cut off, and the diode between the collector and emitter of transistors G1 and G2 and the load inductor L form a freewheeling circuit to consume the electrical energy stored in the load inductor L.

[0050] If the power device under test fails (transistor G is always in the open state), Figure 2 the current in the circuit within the dashed-line box will change. At this time, the sampling resistor R obtains the current input of the circuit and connects it to the overcurrent detection circuit. The control signal output by the overcurrent detection circuit is connected to transistor G2 to turn off the transistor, and the DC power supply is cut off. In this state, the load inductor L and diode D1 form a freewheeling circuit, and the electrical energy stored in the load inductor L is consumed, so that Figure 2 the current in the circuit within the dashed-line box no longer increases, reducing the voltage across the power device under test and reducing the risk of failure of the power device under test being burned out, thereby playing a protective role.

[0051] Figure 2 The shown test system has a certain protective effect, but the circuit uses a series resistor R for current sampling to judge overcurrent. This method will increase the connection length between the DC bus capacitor and the power device under test, resulting in an increase in the stray inductance of the test circuit. As a result, when the power device under test (transistor G) undergoes a double-pulse test, the turn-off voltage spike increases, increasing the risk of failure; the current switching frequency at the placement position of resistor R is relatively high, increasing the design difficulty of the overcurrent detection circuit (the layout interval between resistor R and the overcurrent detection circuit is relatively far, with large stray signals, so the overcurrent detection circuit needs to have strong anti-interference ability, thus increasing the design difficulty of this circuit).

[0052] When the test current of the device under test is relatively large, resistor R generates heat seriously, affecting the test accuracy. Using the sampling resistor R to detect current requires it to be connected in series to the circuit, resulting in cumbersome installation.

[0053] Embodiment 2

[0054] The test system provided in this embodiment includes a capacitor C, a transistor G1 as the first freewheeling device, a load inductor L, and a failure protection circuit. The first unit in the failure protection circuit is configured to include a non-contact current detector I for sensing the circuit current and an overcurrent detection circuit; the second unit is configured to include a controllable device, here configured as transistor G2, and can also be a thyristor or a diode; the third unit includes a second freewheeling device, here configured as diode D1.

[0055] As Figure 3As shown, the first electrode plate of the capacitor C serves as the first connection terminal of the test system for connecting to the positive electrode of the power supply DC for testing, and the second electrode plate serves as the second connection terminal of the test system for connecting to the negative electrode of the power supply DC for testing; the collector of the transistor G1 is connected to the first electrode plate of the capacitor C, and the emitter serves as the third connection terminal of the test system for connecting to the power device under test; one end of the load inductor L is connected to the emitter of the transistor G1, and the other end is connected to the emitter of the transistor G2. The diode D1 is connected in parallel across the load inductor L; the collector of the transistor G2 is connected to the first electrode plate of the capacitor C, and the base is connected to the output terminal of the overcurrent detection circuit.

[0056] In this embodiment, the non-contact current detector I is used to sense Figure 3 the loop current in the dashed box. The test principle and the fail-safe principle are the same as those in Embodiment 1 and will not be elaborated here.

[0057] Embodiment 3

[0058] Due to the package structure and installation structure of the power device under test, there are three segments of stray inductance, LS1, LS2, and LS3 (as Figure 4 shown). The diode D1 is connected in parallel across the load inductor L. When the power device under test is in a failure state and the transistor G2 is turned off (cut off) by the control signal output by the overcurrent detection circuit, there is no freewheeling loop for the three segments of stray inductance, LS1, LS2, and LS3, which will increase the voltage across the transistor G2 and increase the risk of failure of the transistor G2.

[0059] The test system provided in this embodiment includes a capacitor C, a transistor G1 as the first freewheeling device, a load inductor L, and a fail-safe circuit. The first unit in the fail-safe circuit is configured to include a non-contact current detector I for sensing the loop current and an overcurrent detection circuit; the second unit is configured to include a controllable device, and here the transistor G2 is configured; the third unit includes a second freewheeling device, and here the diode D1 is configured.

[0060] As Figure 5 shown, the first electrode plate of the capacitor C serves as the first connection terminal of the test system for connecting to the positive electrode of the power supply DC for testing, and the second electrode plate serves as the second connection terminal of the test system for connecting to the negative electrode of the power supply DC for testing; the collector of the transistor G1 is connected to the first electrode plate of the capacitor C, and the emitter serves as the third connection terminal of the test system for connecting to the power device under test; one end of the load inductor L is connected to the emitter of the transistor G1, and the other end is connected to the emitter of the transistor G2. The end of the load inductor L connected to the emitter of the transistor G2 is also connected to the cathode of the diode D, and the anode of the diode D is connected to the second electrode plate of the capacitor C; the collector of the transistor G2 is connected to the first electrode plate of the capacitor C, and the base is connected to the output terminal of the overcurrent detection circuit.

[0061] During the test, the collector of the transistor G, which is the power transistor under test, is connected to the third connection terminal of the test system, the emitter is connected to the second connection terminal of the test system, and the base is connected to the output terminal of the pulse generator. The pulse signal generated by the pulse generator is applied to the base of the transistor G to control the turn-off (cut-off) and turn-on (conductivity) of the transistor G for double-pulse testing.

[0062] After the power device under test is connected to the test system, a voltage of 0 to -30V is applied between the BE poles of the transistor G1 to make it in the off (cut-off) state; the positive and negative poles of the DC power supply are respectively connected to the first connection terminal and the second connection terminal of the test system, and the transistor G2 is in the on (conductive) state. The test power supply provided by the DC power supply passes through the transistor G2 and the load inductor L and is connected to the collector of the transistor G (the power device under test) to provide a collector bias signal for the transistor G. The pulse signal is applied to the base of the transistor G to control the turn-off and turn-on of the transistor G; parameters such as the turn-off voltage, turn-on voltage, and inter-electrode voltage at the moment of turn-off or turn-on or the holding state of the transistor G are obtained through an external test terminal (such as an oscilloscope) to achieve double-pulse testing of the power device.

[0063] If the power device under test is in a non-failure state, the non-contact current detector I senses Figure 5 the current in the loop in the dashed box in the figure and inputs it to the over-current detection circuit. The control signal output by the over-current detection circuit is applied to the transistor G2 to keep this transistor in the on state; after the test is completed, the DC power supply is cut off, and the CE inter-electrode diodes in the transistors G1 and G2 and the load inductor L form a freewheeling loop to consume the electrical energy stored in the load inductor L.

[0064] If the power device under test fails (the transistor G is always in the on state), Figure 5 the current in the loop in the dashed box in the figure will change. At this time, the non-contact current detector I senses the current in the loop and inputs it to the over-current detection circuit. The control signal output by the over-current detection circuit is applied to the transistor G2 to turn off this transistor, and the DC power supply is cut off; in this state, the load inductor L and the diode D1 form a freewheeling loop, and this loop includes the branch where the power device under test is located. This loop is shown by Figure 6 the dashed box in the figure. The electrical energy stored in the load inductor L and the electrical energy stored in the stray inductors LS1, LS2, and LS3 in the loop are consumed through the Figure 6 freewheeling loop shown in the figure, so that the loop current no longer increases, reducing the voltages across the power device under test and the transistor G2, reducing the failure risk of the power device under test and the transistor G2 being burned out, and improving the stability of the entire test system.

[0065] Figure 6 The stray inductors shown in the figure are only exemplary. It can be understood that the loop not only includes the stray inductors LS1, LS2, and LS3, and those not shownFigure 6 The electrical energy existing in the stray inductance of the circuit shown can also be consumed through Figure 6 the freewheeling circuit shown.

[0066] Embodiment 4

[0067] The test system provided in this embodiment includes a capacitor C, a transistor G1 as a first freewheeling device, a load inductor L, and a failure protection circuit. The first unit in the failure protection circuit is configured to include a sampling resistor R for sensing the loop current and an overcurrent detection circuit; the second unit is configured to include a controllable device, and here a transistor G2 is configured; the third unit includes a second freewheeling device, and here a diode D1 is configured.

[0068] As Figure 7 shown, the first electrode plate of the capacitor C serves as the first connection end of the test system for connecting to the positive electrode of the test power supply DC, and the second electrode plate serves as the second connection end of the test system for connecting to the negative electrode of the test power supply DC; the collector of the transistor G1 is connected to the first electrode plate of the capacitor C, and the emitter serves as the third connection end of the test system for connecting to the power device under test; one end of the sampling resistor R is connected to the second electrode plate of the capacitor C, and the other end serves as the fourth connection end of the test system. One end of the load inductor L is connected to the emitter of the transistor G1, and the other end is connected to the emitter of the transistor G2. The end of the load inductor L connected to the emitter of the transistor G2 is also connected to the cathode of the diode D, and the anode of the diode D is connected to the second electrode plate of the capacitor C; the collector of the transistor G2 is connected to the first electrode plate of the capacitor C, and the base is connected to the output end of the overcurrent detection circuit.

[0069] During the test, the collector of the transistor G serving as the power transistor under test is connected to the third connection end of the test system, the emitter is connected to the fourth connection end of the test system, and the base is connected to the output end of the pulse generator. The pulse signal generated by the pulse generator is applied to the base of the transistor G to control the turn-off (cut-off) and turn-on (conductance) of the transistor G for double-pulse testing.

[0070] The test system of this embodiment is configured with a sampling resistor R to realize the acquisition of the loop current. The test principle and the failure protection principle are the same as those in Embodiment 3, and will not be elaborated here.

[0071] This test system realizes the device failure protection function by connecting a second unit (transistor G2) in series in the load circuit, connecting a second freewheeling device (diode D1) between the load output terminal and the negative pole of the DC bus capacitor, and applying a non-contact current measurer I on the load circuit to read the loop current value. The non-contact current measuring device continuously detects the main loop current value and feeds the measured current value back to the overcurrent detection circuit. When the power device under test is not failed, the overcurrent detection circuit keeps the transistor G2 in the open (conducting) state for normal testing. When the power device under test is in the failed state, the overcurrent detection circuit turns off the transistor G3, cutting off the connection between the main loop and the power supply, so that the load current no longer increases until it decays to 0, and the loop current also no longer increases. At the same time when the second unit is turned off, the second freewheeling device conducts at this time to provide a freewheeling loop for the load inductor, protecting the second unit from being damaged by overvoltage. Thus, the entire failure protection process is completed.

[0072] Figures 2 - 7 It is shown in the figure that the second freewheeling device is configured as a diode, but those skilled in the art can understand that the second freewheeling device can also be configured as a transistor, such as the transistor G1 shown in the figure.

[0073] Figure 3 、 5 、The current sampling position of the test system shown in Figure 6 is changed from the sampling resistor R located between the negative pole of the power supply and the power device under test ( Figure 2 、 4 、Figure 7) to the load output terminal. The measured current includes the current during the freewheeling process of the double-pulse test, so it can more comprehensively monitor whether there is an abnormal state during the test process. The current sampling method is changed from series resistance sampling to non-contact current detection, isolating the overcurrent detection module from the high-voltage main loop and improving the safety of the system. The current sampling method is changed from series resistance sampling to non-contact current detection, making the current measurement range wider, compatible with both large-current and small-current tests, and more convenient and simple to install and replace.

[0074] As Figure 8 shown, the overcurrent detection circuit in this test system includes a comparator. The output of the non-contact current sensor / resistor R is connected to the inverting input terminal of the comparator. The non-inverting input terminal of the comparator is connected to a set value REF as a threshold, and an output control signal is used to control the turn-off and turn-on of the second unit. The output of the non-contact current sensor and resistor R is connected to the comparator and compared with the set value. If it is lower than the set value, it is judged as not failed and a high level is output, keeping the second unit in the open state for normal testing. When it is higher than the set overcurrent value, it is judged as failed, and a low level is output to turn off the second unit, cutting off the connection between the main loop and the power supply, and then cooperating with the freewheeling loop to make the load current no longer increase until it decays to 0.

[0075] When the second unit is configured as a transistor, the output of the overcurrent detection circuit is directly connected to the base of the transistor or connected to the base of the transistor through a drive circuit.

[0076] In this test system, the non-contact current detector I can be located at any position capable of sensing the current in the loop, such as at the load output (the non-contact current detector I is located between the load inductor L and the emitter of the transistor G1), and the rate of change of the current waveform decreases, thereby reducing the design difficulty of the overcurrent detection circuit; or it is connected in series with the power device under test.

[0077] The transistors described in this article should be understood as power devices such as NPN transistors, PNP transistors, IGBT transistors, and MOS transistors. The described collector, emitter, and base correspond according to the configured power device. For example, when configured as an NPN transistor or a PNP transistor, they are the collector, emitter, and base; for an IGBT transistor, they are the collector, emitter, and gate; and for a MOS transistor, they are the drain, source, and gate. The non-contact current detector I described in this article is configured as a Hall current sensor.

[0078] The loop described in the embodiments of this article is only exemplary. It can be understood that the loop described in the embodiments of this article, in addition to including the components contained in the attached Figures 2 - 7 dashed box, may also include a capacitor C, a DC power supply, and G1 that are not contained in the dashed box; or, it includes the capacitor C, the DC power supply, or G1.

[0079] The present disclosure has been described by the above related embodiments. However, the above embodiments are only examples of implementing the present disclosure. It must be pointed out that the disclosed embodiments do not limit the scope of the present disclosure. On the contrary, changes and modifications made without departing from the spirit and scope of the present disclosure fall within the patent protection scope of the present disclosure.

Claims

1. A double-pulse test system, characterized in that The system is configured to include: A load inductor, through which a test power supply is connected to the power device under test; A first freewheeling device, which forms a freewheeling loop with the load inductor after the test of the power device under test is completed; A pulse generator, which is used to provide double pulses required for the test for the power device under test; and A failure protection circuit, which cuts off the test power supply when the power device under test is in a failure state and constructs a freewheeling loop to prevent the loop current from increasing further. The failure protection circuit includes: A third unit, which forms a freewheeling loop with the load inductor and the branch where the power device under test is located when the power device under test is in a failure state, so that the stray inductances in the branch where the power device under test is located, the branch where the load inductor is located, and the failure protection circuit have a freewheeling loop; or, the third unit forms a freewheeling loop with the load inductor when the power device under test is in a failure state, so that the current in the loop where the power device under test is located no longer increases.

2. The dual-pulse test system according to claim 1, wherein The failure protection circuit is configured to include: A first unit, which is used to judge whether the power device under test is in a failure state and generates a control signal when the power device under test is in a failure state; A second unit, which cuts off the power supply connected to the power device under test under the control of the control signal.

3. The dual-pulse test system according to claim 2, wherein The first unit includes a non-contact current detector for sensing the loop current and an overcurrent detection circuit.

4. The dual-pulse test system according to claim 2, wherein The first unit includes a sampling resistor for collecting the loop current and an overcurrent detection circuit.

5. A dual-pulse test failure protection circuit, characterized in that, This circuit is used to cut off the test power supply connected to the power device under test when the power device under test is in a failure state and construct a freewheeling loop to prevent the loop current from increasing further. The circuit includes: A third unit, which forms a freewheeling loop with the load inductor and the branch where the power device under test is located when the power device under test is in a failure state, so that the stray inductances in the branch where the power device under test is located, the branch where the load inductor is located, and the failure protection circuit have a freewheeling loop; or, the third unit forms a freewheeling loop with the load inductor when the power device under test is in a failure state, so that the current in the loop where the power device under test is located no longer increases.

6. The double-pulse test failure protection circuit according to claim 5, characterized in that This circuit is configured to include: A first unit, which is used to judge whether the power device under test is in a failure state and generates a control signal when the power device under test is in a failure state; A second unit, which cuts off the power supply connected to the power device under test under the control of the control signal.

7. The dual-pulse test failure protection circuit according to claim 6, characterized in that, The first unit includes a non-contact current detector for sensing the loop current and an overcurrent detection circuit.

8. The dual-pulse test failure protection circuit according to claim 6, wherein The first unit includes a sampling resistor for collecting the loop current and an overcurrent detection circuit.

Images