Method for manufacturing a semiconductor device

Abstract

The present invention discloses a method for manufacturing a semiconductor device, belonging to the field of semiconductor technology. The manufacturing method comprises: providing a substrate, comprising a first region and a second region; forming a shallow trench isolation structure between the first region and the second region; forming a first patterned photoresist layer on the substrate with the long side of the opening parallel to the channel width direction of the semiconductor device, and exposing the first region and part of the shallow trench isolation structure on both sides; performing two tilted ion implantations on the first region to form a first channel doping region; re-forming a second patterned photoresist layer with the long side of the opening parallel to the channel width direction of the semiconductor device, and exposing the second region and part of the shallow trench isolation structure; performing two tilted ion implantations on the second region to form a second channel doping region; forming a gate on the channel doping region; and forming lightly doped regions on both sides of the gate. The manufacturing method of the semiconductor device provided by the present invention can improve the performance of the semiconductor device.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductors, and in particular relates to a method for manufacturing a semiconductor device. Background Art

[0002] In low-power circuits, high threshold voltage devices are needed to reduce leakage in the circuit. The threshold voltage of the device can be adjusted by the channel doping ion concentration. For example, in 55nm devices, three different threshold voltage devices, low voltage, medium voltage and high voltage, can be made by different channel doping concentrations. However, in high threshold voltage metal oxide semiconductor field effect transistors (MOS), when the impurity ion concentration near the source and drain regions and the gate overlap region increases, the gate-induced drain leakage (GIDL) will increase, resulting in increased leakage of the MOS transistor.

[0003] In the traditional MOS transistor manufacturing process, channel doping ions are uniformly injected into the channel region and the source and drain regions, but the channel doping in the source and drain regions is ineffective. Instead, it increases the impurity ion concentration in the source and drain regions, exacerbating GIDL leakage. On the other hand, the doping type of the lightly doped drain (LDD) is opposite to the channel doping. In order to offset the channel doping previously performed in the source and drain regions, it is necessary to increase the LDD concentration, that is, increase the impurity ion concentration in the source and drain regions, which will also exacerbate GIDL leakage. Summary of the invention

[0004] The object of the present invention is to provide a method for manufacturing a semiconductor device. Through the method for manufacturing a semiconductor device provided by the present invention, the ion concentration in the lightly doped region formed subsequently can be reduced, the gate induced drain leakage current can be reduced, at least two photoresists can be saved, the manufacturing process can be simplified, the production efficiency can be accelerated, and the enterprise cost can be reduced.

[0005] In order to solve the above technical problems, the present invention provides a method for manufacturing a semiconductor device, comprising the following steps:

[0006] Providing a substrate, the substrate comprising at least a first region and a second region;

[0007] forming a shallow trench isolation structure between the first region and the second region;

[0008] Forming a first patterned photoresist layer on the substrate, wherein the long side direction of the opening of the first patterned photoresist layer is parallel to the channel width direction of the semiconductor device, and the first patterned photoresist layer exposes the first region and a portion of the shallow trench isolation structure on both sides of the first region;

[0009] Using the first patterned photoresist layer as a mask, performing two oblique ion implantations on the first region to form a first channel doping region;

[0010] Removing the first patterned photoresist layer, forming a second patterned photoresist layer on the substrate, wherein the long side direction of the opening of the second patterned photoresist layer is parallel to the channel width direction of the semiconductor device, and the second patterned photoresist layer exposes the second region and a portion of the shallow trench isolation structure on both sides of the second region;

[0011] Using the second patterned photoresist layer as a mask, performing two oblique ion implantations on the second region to form a second channel doping region;

[0012] forming a gate on the first channel doping region and the second channel doping region; and

[0013] Lightly doped regions are formed on both sides of the gate.

[0014] In an embodiment of the present invention, the first channel doping region includes a first sub-portion and a second sub-portion, and the second sub-portion is located at two sides of the first sub-portion.

[0015] In one embodiment of the present invention, the doping concentration of the first section is twice the doping concentration of the second section, and the widths of the second sections on both sides of the first section are equal.

[0016] In an embodiment of the present invention, the second channel doping region includes a third section and a fourth section, and the fourth section is located at two sides of the third section.

[0017] In one embodiment of the present invention, the doping concentration of the third section is twice the doping concentration of the fourth section, and the widths of the fourth sections on both sides of the third section are equal.

[0018] In one embodiment of the present invention, the gate is disposed on the first sub-portion and the third sub-portion, and an edge of the gate is aligned with an edge of the first sub-portion or the third sub-portion.

[0019] In one embodiment of the present invention, when performing two tilted ion implantations, after the first tilted ion implantation, the substrate is rotated 180° in plane, or the ion implantation direction is adjusted, and the second tilted ion implantation is performed.

[0020] In one embodiment of the present invention, when two inclined ion implantations are performed in the first region or the second region, a pad oxide layer is provided on the substrate, the pad oxide layer is used as an ion implantation buffer layer, a well region is formed in the first region or the second region, and a channel doping region is provided on the well region.

[0021] In one embodiment of the present invention, the two inclined ion implantations in the first region or the second region have equal implantation angles and equal implanted ion quantities.

[0022] In one embodiment of the present invention, the injection angle α of the inclined ion implantation is obtained according to the formula α=arctan(H / D), wherein the injection angle α is the angle between the ion implantation direction and the substrate, H is the thickness of the first patterned photoresist layer or the second patterned photoresist layer on the pad oxide layer, and D is the distance from the boundary of the gate to the adjacent edge of the first patterned photoresist layer or the second patterned photoresist layer.

[0023] In summary, the present invention provides a method for manufacturing a semiconductor device. The unexpected technical effect of the present application is that when forming a channel doping region, the channel doping concentration in the region where the source and drain are located can be reduced, thereby reducing the ion concentration in the lightly doped region formed subsequently, and reducing the gate-induced drain leakage current. It can save at least two photoresists, simplify the manufacturing process, speed up production efficiency, and reduce enterprise costs. Different types of semiconductor devices can be formed on the same substrate, which improves process integration, shortens the process cycle, and reduces the cost of manufacturing. It can accurately obtain the injection angle, flexibly control the width of the formed channel region, adjust the performance of the semiconductor device, and at the same time reduce the impurity ion concentration in the source and drain regions on both sides to reduce leakage.

[0024] Of course, any product implementing the present invention does not necessarily need to achieve all of the advantages described above at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for describing the embodiments are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0026] Figure 1 FIG. 1 is a top view of a semiconductor device according to an embodiment of the invention.

[0027] Figure 2 For along Figure 1 Schematic diagram of forming a pad oxide layer and a pad nitride layer on a substrate in the AA direction.

[0028] Figure 3 For along Figure 1 Schematic diagram of forming the first photoresist layer in the AA direction.

[0029] Figure 4 For along Figure 1Schematic diagram of forming a shallow trench isolation structure in the AA direction.

[0030] Figure 5 FIG. 4 is a top view of a first patterned photoresist layer according to an embodiment of the present invention.

[0031] Figure 6 For along Figure 1 Schematic diagram of forming the first well region in the AA direction.

[0032] Figure 7 For along Figure 1 Schematic diagram of the first tilted ion implantation in the first well region in the AA direction.

[0033] Figure 8 For along Figure 1 Schematic diagram of the second tilted ion implantation in the first well region in the AA direction.

[0034] Fig. 9 For along Figure 1 Schematic diagram of forming a second channel doping region in the AA direction.

[0035] Fig.10 For along Figure 1 Schematic diagram of forming a gate in the AA direction.

[0036] Fig.11 For along Figure 1 Schematic diagram of forming a lightly doped region in the AA direction.

[0037] Fig.12 For along Figure 1 Schematic diagram of the side wall structure formed in the AA direction.

[0038] Fig.13 FIG. 4 is a schematic diagram of a semiconductor device according to an embodiment of the present invention.

[0039] Description of labels:

[0040] 10. substrate; 100. first region; 200. second region; 101. first well region; 102. second well region; 11. pad oxide layer; 12. pad nitride layer; 13. first photoresist layer; 131. opening; 14. shallow trench isolation structure; 15. first patterned photoresist layer; 151. first recess; 161. first doped region; 162. second doped region; 17. second patterned photoresist layer; 171. first division; 172. second division; 173. second recess; 181. third division; 182. fourth division; 19. gate oxide layer; 20. gate; 21. first light doping; 22. second light doping; 23. sidewall structure; 24. first heavily doped region; 25. second heavily doped region. DETAILED DESCRIPTION

[0041] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0042] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0043] In the description of this specification, it should be understood that the directions or positional relationships indicated by the terms "center", "upper", "lower", "front", "back", "left", "right", etc. are based on the directions or positional relationships shown in the drawings, and are only for the convenience of describing this solution and simplifying the description, rather than indicating or implying that the device or component referred to must have a specific direction, be constructed and operated in a specific direction, and therefore cannot be understood as a limitation on this solution. In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance.

[0044] The present invention provides a method for manufacturing a semiconductor device, which can reduce the channel doping concentration in the source and drain regions, thereby reducing the ion concentration in the lightly doped region formed subsequently, and can reduce the gate-induced drain leakage current. At the same time, it can save at least two photoresists, simplify the manufacturing process, increase production efficiency, and reduce enterprise costs. The semiconductor device prepared by the present invention can be widely used in various fields such as optical communication, digital display, image reception, optical integration, transportation, energy, medicine, household appliances, and aerospace. In this embodiment, for example, Figure 1 Taking the AA direction in the middle as an example, the production method is explained, among which, Figure 1 The AA direction is the channel length direction of the semiconductor device. Figure 1 The BB direction is the channel width direction of the semiconductor device.

[0045] See also Figures 1 to 4As shown, in one embodiment of the present invention, a substrate 10 is first provided, and the substrate 10 includes a first region 100 and a second region 200, and the first region 100 and the second region 200 are used to form different types of semiconductor devices. In this embodiment, the first region 100 is used to form a P-type metal oxide semiconductor field effect transistor (Positive Channel Metal Oxide Semiconductor, PMOS), and the second region 200 is used to form an N-type metal oxide semiconductor field effect transistor (Negative Channel Metal Oxide Semiconductor, NMOS), and the first region 100 and the second region 200 are isolated by a shallow trench isolation structure 14. The present application does not limit the device type including PMOS transistors and NMOS transistors, such as static random access memory (Static Random-Access Memory, SRAM), CMOS image sensor or power device, etc. In this embodiment, the substrate 10 may be any material suitable for forming a semiconductor device, such as silicon carbide (SiC), gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), indium phosphide (InP), gallium arsenide (GaAs), silicon germanium (GeSi), sapphire, silicon wafer or other semiconductor materials formed by III / V compounds, etc., including a stacked structure composed of these semiconductor materials, or silicon on insulator, stacked silicon on insulator, silicon germanium on insulator, and germanium on insulator. In this embodiment, the substrate 10 is, for example, a silicon wafer semiconductor substrate. In other embodiments, the type of the substrate 10 is selected according to the semiconductor device to be manufactured.

[0046] See also Figure 2 As shown, in one embodiment of the present invention, a pad oxide layer 11 is formed on the substrate 10. The pad oxide layer 11, as a buffer layer, can improve the stress between the substrate 10 and the subsequently formed pad nitride layer 12. The pad oxide layer 11 is, for example, a dense silicon oxide material, and the pad oxide layer 11 can be formed, for example, by any one of the methods such as dry oxygen oxidation, wet oxygen oxidation, or in-situ steam growth (ISSG). In this embodiment, the pad oxide layer 11 is formed, for example, by dry oxygen oxidation. Specifically, the substrate 10 is placed in a furnace tube at a temperature of, for example, 900°C to 1150°C, and oxygen is introduced. The surface of the substrate 10 reacts with the oxygen at high temperature to generate a dense pad oxide layer 11, and the quality of the generated pad oxide layer 11 is good. Among them, the pad oxide layer 11 is, for example, silicon oxide, and the thickness of the pad oxide layer 11 is, for example, 10nm to 40nm, specifically, for example, 10nm, 20nm, 30nm or 40nm.

[0047] See also Figure 2As shown, in one embodiment of the present invention, a pad nitride layer 12 is formed on the pad oxide layer 11, and the pad nitride layer 12 is, for example, silicon nitride or a stack of silicon nitride and silicon oxide. In this embodiment, the pad nitride layer 12 is, for example, silicon nitride, and can be formed, for example, by a method such as low pressure chemical vapor deposition (LPCVD). Specifically, for example, the substrate 10 with the pad oxide layer 11 is placed in a furnace tube filled with dichlorosilane and ammonia, and reacts at a pressure of, for example, 2T~10T and a temperature of, for example, 700°C~900°C to deposit the pad nitride layer 12, and the thickness of the pad nitride layer 12 can be adjusted by controlling the heating time. The thickness of the pad nitride layer 12 is, for example, 50 nm to 80 nm, specifically, 50 nm, 60 nm, or 70 nm. By providing the pad nitride layer 12, the substrate 10 can be protected from the influence of the planarization process such as chemical mechanical polishing (CMP) involved in the process of manufacturing the shallow trench isolation structure 14. In addition, the pad nitride layer 12 can be used as a mask in the subsequent shallow trench isolation structure formation process to protect the substrate 10 from damage when etching the substrate 10.

[0048] See also Figures 2 to 4 As shown, in one embodiment of the present invention, after forming the pad nitride layer 12, a first photoresist layer 13 is formed on the pad nitride layer 12, and a plurality of openings 131 are formed on the first photoresist layer 13 through exposure and development processes, and the openings 131 are used to define the position of the shallow trench isolation structure 14. Using the first photoresist layer 13 as a mask, etching is performed to remove the pad nitride layer 12, the pad oxide layer 11 and a portion of the substrate 10 exposed by the opening 131 to form a shallow trench. In this embodiment, for example, dry etching is used to form a shallow trench (not shown in the figure), and after etching is completed, the first photoresist layer 13 is removed. After the shallow trench is formed, an insulating medium is deposited in the shallow trench until the insulating medium covers the surface of the pad nitride layer 12. The present invention does not limit the deposition method of the insulating medium, for example, a high-quality insulating medium can be formed by high-density plasma chemical vapor deposition (HDP-CVD) or high-aspect ratio chemical vapor deposition (HARP-CVD). In this embodiment, the insulating medium is, for example, silicon oxide. In other embodiments, the insulating medium can also be other insulating materials suitable for isolation.

[0049] See also Figures 2 to 4As shown, in one embodiment of the present invention, after the insulating medium is prepared, the insulating medium is planarized, for example, by using chemical mechanical polish (CMP) to planarize the insulating medium. For example, a portion of the insulating medium and a portion of the pad nitride layer 12 are removed by grinding, and then the pad nitride layer 12 is removed to obtain a shallow trench isolation structure 14, and the shallow trench isolation structure 14 is, for example, higher than the pad oxide layer 11 on both sides. The present invention does not limit the method for removing the pad nitride layer 12, such as by dry etching, wet etching, or a combination of dry etching and wet etching. In the present embodiment, for example, hot phosphoric acid is used to remove the pad nitride layer 12 to form a shallow trench isolation structure 14, and a plurality of shallow trench isolation structures 14 separate the substrate 10 into a plurality of regions to avoid the generation of leakage current in the device.

[0050] See also Figures 4 to 6 As shown, in one embodiment of the present invention, after the shallow trench isolation structure 14 is prepared, a first patterned photoresist layer 15 is formed on the shallow trench isolation structure 14 and the pad oxide layer 11, and a first recess 151 is provided on the first patterned photoresist layer 15, and the first recess 151 exposes the pad oxide layer 11 on the first region 100 and a portion of the shallow trench isolation structure 14 on both sides. In this embodiment, the long side direction of the opening of the first patterned photoresist layer 15 is parallel to the channel width direction of the semiconductor device, that is, the long side direction of the first recess 151 is parallel to the channel width direction of the semiconductor device. Figure 5 In the BB direction, the long side direction is the boundary extension direction of the first recess 151 and the first patterned photoresist layer 15, and the width of the shallow trench isolation structure 14 exposed on both sides of the first recess 151 is, for example, half of the width of the shallow trench isolation structure 14.

[0051] See also Figures 6 to 8 As shown, in one embodiment of the present invention, after forming the first patterned photoresist layer 15, the first patterned photoresist layer 15 is used as a mask, the pad oxide layer 11 is used as an ion implantation buffer layer, and N-type doping ions, such as phosphorus (P) or arsenic (As), are vertically implanted into the substrate 10 to form a first well region 101, so that the first well region 101 is used as a formation region of the PMOS transistor. In this embodiment, the implantation conditions of the doping ions are controlled, and the depth of the formed first well region 101 is less than or equal to the depth of the shallow trench isolation structure 14, and the surface of the first well region 101 has a preset distance from the surface of the substrate 10, so as to form a first channel doping region.

[0052] See also Figures 6 to 8As shown, in one embodiment of the present invention, after forming the first well region 101, the substrate 10 of the first region 100 is subjected to two tilted ion implantations using the first patterned photoresist layer 15 as a mask and the pad oxide layer 11 as an ion implantation buffer layer to form a first channel doping region. Specifically, during the first tilted ion implantation, due to the blocking effect of the first patterned photoresist layer 15, a first doping region 161 is formed on the first well region 101, one side of the first doping region 161 is in contact with the adjacent shallow trench isolation structure 14, and the other side is located on the first well region 101, that is, part of the substrate 10 on the first well region 101 is not doped, and the other side of the first doping region 161 has an undoped region with the adjacent shallow trench isolation structure 14. Then, the substrate 10 is rotated 180° in plane, or the ion implantation direction is adjusted, and a second tilted ion implantation is performed, and similarly due to the blocking effect of the first patterned photoresist layer 15, a second doping region 162 is formed on the first well region 101. The first doping region 161 and the second doping region 162 partially overlap. In this embodiment, the two tilted ion implantations on the first region 100 have the same implantation angle α and the same amount of implanted ions, wherein the implantation angle α is the angle between the ion implantation direction and the substrate. The ion types of the two tilted implantations on the first region 100 are, for example, N-type doping ions such as phosphorus or arsenic.

[0053] See also Figures 8 to 9 As shown, in one embodiment of the present invention, the first doping region 161 and the second doping region 162 are defined as the first channel doping region, and the first channel doping region includes a first sub-portion 171 and a second sub-portion 172. The first sub-portion 171 is the overlapping region of the first doping region 161 and the second doping region 162, and the second sub-portion 172 is located on both sides of the first sub-portion 171, and is the first doping region 161 or the second doping region 162 that is only ion-implanted once. In this embodiment, since the angle and the amount of the two oblique implantations are the same, the doping concentration of the first sub-portion 171 is twice the doping concentration of the second sub-portion 172, and the widths of the second sub-portions 172 on both sides of the first sub-portion 171 are equal. In this embodiment, the doping concentration of the first sub-portion 171 is greater than the doping concentration in the first well region 101, and the first sub-portion 171 is used to form the channel region of the PMOS transistor, and the second sub-portion 172 is used to form the source and drain regions of the PMOS transistor. By performing two tilted ion implantations, the doping concentrations of the source and drain regions can be reduced when forming the channel doping region, thereby reducing the impurity ion concentration in the lightly doped region formed subsequently and reducing GIDL leakage.

[0054] See also Figure 8As shown, in one embodiment of the present invention, when performing tilted ion implantation, in order to obtain an accurate channel region, the implantation angle α of the tilted implantation is adjusted. In this embodiment, the implantation angle α is obtained according to the formula α=arctan(H / D), wherein H is the thickness of the first patterned photoresist layer 15 on the pad oxide layer 11, and D is the distance from the boundary of the first subdivision 171 and the second subdivision 172 to the adjacent edge of the first patterned photoresist layer 15, that is, the distance from the subsequent gate boundary to the adjacent edge of the first patterned photoresist layer 15. When designing a chip, the active area, shallow trench isolation structure, and the width of the channel region of the first region 100 are set, and D is equal to the sum of half of the width of the active area minus half of the width of the channel region and half of the width of the shallow trench isolation structure, and then the thickness of the first patterned photoresist layer 15 on the pad oxide layer is set, thereby determining the implantation angle α. Therefore, the present application can accurately obtain the implantation angle, flexibly control the width of the formed channel region, adjust the performance of the semiconductor device, and simultaneously reduce the impurity ion concentration of the source and drain regions on both sides, thereby reducing GIDL leakage.

[0055] See also Figures 8 to 9 As shown, in one embodiment of the present invention, after forming the first channel doping region, the first patterned photoresist layer 15 is removed, for example, by wet etching or dry etching, and a second patterned photoresist layer 17 is formed on the shallow trench isolation structure 14 and the pad oxide layer 11. A second recess 173 is provided on the second patterned photoresist layer 17, and the second recess 173 exposes the pad oxide layer 11 on the second region 200 and a portion of the shallow trench isolation structure 14 on both sides. In this embodiment, the long side direction of the opening of the second patterned photoresist layer 17 is parallel to the channel width direction of the semiconductor device, that is, the long side direction of the second recess 173 is parallel to the channel width direction of the semiconductor device. Figure 1 In the BB direction, the width of the shallow trench isolation structure 14 exposed at both sides of the second recess 173 is, for example, half of the width of the shallow trench isolation structure 14.

[0056] See also Fig. 9 As shown, in one embodiment of the present invention, after forming the second patterned photoresist layer 17, the second patterned photoresist layer 17 is used as a mask, the pad oxide layer 11 is used as an ion implantation buffer layer, and P-type doping ions, such as boron (B) or gallium (Ga), are vertically implanted into the substrate 10 to form a second well region 102, so that the second well region 102 is used as a formation region of the NMOS transistor. In this embodiment, the implantation conditions of the doping ions are controlled, and the depth of the formed second well region 102 is less than or equal to the depth of the shallow trench isolation structure 14, and is equal to the depth of the first well region 101, for example, and the surface of the second well region 102 is at a preset distance from the surface of the substrate 10, so as to form a second channel doping region.

[0057] See also Fig. 9As shown, in one embodiment of the present invention, after forming the second well region 102, the second patterned photoresist layer 17 is used as a mask, the pad oxide layer 11 is used as an ion implantation buffer layer, and the substrate 10 of the second region 200 is subjected to secondary oblique ion implantation on both sides to form a second channel doping region. In the present application, the doping ions in the second channel doping region are, for example, P-type doping ions such as boron or gallium, and the formation method is similar to that of the first channel doping region, which will not be elaborated here. In the present embodiment, the second channel doping region includes a third subdivision 181 and a fourth subdivision 182, the doping concentration of the third subdivision 181 is twice the doping concentration of the fourth subdivision 182, and the widths of the fourth subdivision 182 on both sides of the third subdivision 181 are equal. In the present embodiment, the doping concentration of the third subdivision 181 is greater than the doping concentration in the second well region 102, the third subdivision 181 is used to form the channel region of the NMOS transistor, and the fourth subdivision 182 is used to form the source and drain regions of the NMOS transistor. By performing two tilted ion implantations, the doping concentration in the source and drain regions can be reduced when forming a channel doping region, thereby reducing the impurity ion concentration in the lightly doped region formed subsequently, and reducing GIDL leakage. In the present application, after forming a well region, when forming a channel doping region by performing two tilted ion implantations, the channel doping concentration in the source and drain regions can be reduced, thereby reducing the ion concentration in the lightly doped region formed subsequently, and reducing GIDL leakage, while saving at least two photoresists, simplifying the manufacturing process, accelerating production efficiency, and reducing enterprise costs.

[0058] See also Fig. 9 As shown, in one embodiment of the present invention, after forming the second channel doping region, the second patterned photoresist layer 17 is removed by, for example, wet etching or dry etching, and the substrate is subjected to a rapid thermal annealing process (RTA) so that the ion implantation in the first region 100 and the second region 200 is diffused to a suitable depth, and the avalanche breakdown resistance of the semiconductor device is improved. For another example, wet etching is used to etch the pad oxide layer 11, and the wet etching etchant is, for example, hydrofluoric acid or buffered oxide etchant (BOE).

[0059] See also Figures 9 and 10As shown, in one embodiment of the present invention, after removing the pad oxide layer, a gate oxide layer 19 is formed on the substrate 10. The gate oxide layer 19 is, for example, a silicon oxide layer, and the gate oxide layer 19 is, for example, formed by an in-situ water vapor growth method. The thickness of the gate oxide layer 19 is, for example, 8Å~100Å. After the gate oxide layer 19 is formed, a gate material layer (not shown in the figure) is deposited on the gate oxide layer 19 and the shallow trench isolation structure 14. The gate material layer is, for example, polysilicon. The thickness of the gate material layer is, for example, 100nm~300nm. After the gate material layer is formed, a photoresist layer (not shown in the figure) is formed on the gate material layer, and then the photoresist is exposed and developed to form a patterned photoresist layer. Then, using the patterned photoresist layer as a mask, the gate material layer is etched by, for example, a dry etching process, a wet etching process, or a combination of a dry etching process and a wet etching process to form a plurality of gates 20. During the etching process, the substrate 10 is used as an etching stop layer to etch the gate oxide layer 19 outside the gate 20. In this embodiment, for example, the gate 20 is formed on the first region 100 and the second region 200, respectively, and the gate 20 is formed on the first sub-portion 171 and the third sub-portion 181, and the edge of the gate 20 is aligned with the edge of the first sub-portion 171 or the third sub-portion 181.

[0060] See also Figure 10 to Figure 11 As shown, in one embodiment of the present invention, after forming the gate 20, a lightly doped region is formed in the substrate 10 on both sides of the gate 20. The doping ions in the lightly doped region are formed, for example, by ion implantation, and the type of the implanted ions is opposite to the type of ions in the well region and the channel doping region, and the depth of the lightly doped region is greater than or equal to the depth of the channel doping region. In this embodiment, a first lightly doped region 21 is formed in the first region 100, and the ions implanted in the first lightly doped region 21 are, for example, P-type ions such as boron or gallium, and the doping ions of the first lightly doped region 21 are opposite to the doping ions of the second sub-portion 172, and some of the P-type ions are used to offset the doping ions in the second sub-portion 172 previously formed in the source or drain region. A second lightly doped region 22 is formed in the second region 200, and the ions implanted in the second lightly doped region 22 are, for example, N-type ions such as phosphorus or arsenic, and the doping ions of the second lightly doped region 22 are opposite to the doping ions of the fourth sub-portion 182, and some of the N-type ions are used to offset the doping ions in the fourth sub-portion 182 previously formed in the source or drain region. By reducing the doping concentration of the second sub-portion 172 and the fourth sub-portion 182 when forming the channel doping region, the required lightly doped doping concentration will also be reduced, which will be beneficial to reducing the impurity ion concentration in the source or drain region, thereby reducing GIDL leakage.

[0061] See also Figure 11 to Figure 12As shown, in one embodiment of the present invention, after forming the lightly doped region, a sidewall structure 23 is formed on both sides of the dummy gate, wherein the sidewall structure 23 is, for example, a silicon oxide, silicon nitride, or a silicon oxide and silicon nitride stacked structure. Specifically, a sidewall dielectric layer is formed on the substrate 10, the gate 20, and the shallow trench isolation structure 14, and the material of the sidewall dielectric layer is, for example, a silicon oxide and silicon nitride stacked structure. After the sidewall dielectric layer is formed, the sidewall dielectric layer on the gate 20, the shallow trench isolation structure 14, and a portion of the substrate 10 is removed by, for example, dry etching or other etching processes, and the sidewall dielectric layer on both sides of the gate 20 is retained to form a sidewall structure 23. The height of the sidewall structure 23 is consistent with the height of the gate 20, and the shape of the sidewall structure 23 is, for example, an arc or L-shaped.

[0062] See also Figure 12 to Figure 13 As shown, in one embodiment of the present invention, after forming the spacer structure 23, a heavily doped region is formed in the substrate on both sides of the spacer structure 23, and the edge of the heavily doped region is aligned with the edge of the spacer structure 23 away from the gate 20. Specifically, in the first region 100 where the PMOS transistor is formed, a first heavily doped region 24 is formed on the first well region 101, and the first heavily doped region 24 is located on both sides of the gate 20, and is used to form the source and drain of the PMOS transistor. In the second region 200 where the NMOS transistor is formed, a second heavily doped region 25 is formed on the second well region 102, and the second heavily doped region 25 is located on both sides of the gate 20, and is used to form the source and drain of the NMOS transistor. The doping type of the first heavily doped region 24 is opposite to that of the first well region 101, and the doping type of the first heavily doped region 24 is, for example, P-type doping, and the doping type of the second heavily doped region 25 is opposite to that of the second well region 102, and the doping type of the second heavily doped region 25 is, for example, N-type doping, that is, the doping type of the first heavily doped region 24 and the second heavily doped region 25 are different. In this embodiment, the doping depth of the heavily doped region is, for example, greater than the depth of the lightly doped region, and the doping concentration of the heavily doped region is greater than the doping concentration of the lightly doped region. After the heavily doped region is formed, the heavily doped region and the lightly doped region are activated, for example, by performing rapid thermal annealing on the substrate 10. Through rapid thermal annealing, lattice defects generated during the manufacturing process can be repaired and doping ions can be activated, thereby activating the heavily doped region and the lightly doped region.

[0063] See also Fig.13 As shown, in one embodiment of the present invention, after forming the heavily doped region, a metal silicide layer (not shown in the figure) is formed on the heavily doped region and the gate 20 to improve the contact resistance of the conductive plug formed subsequently. After forming the metal silicide layer, a contact hole etching stop layer, a dielectric layer, a conductive plug, and a metal wiring layer are formed on the substrate, and any formation method can be selected for preparation, which will not be elaborated here.

[0064] In summary, the present invention provides a method for manufacturing a semiconductor device. By improving the method for manufacturing a semiconductor device, the unexpected technical effect of the present application is that when forming a channel doping region, the channel doping concentration in the region where the source and drain are located can be reduced, thereby reducing the ion concentration in the lightly doped region formed subsequently, and reducing the gate-induced drain leakage current. It can save at least two photoresists, simplify the manufacturing process, speed up production efficiency, and reduce enterprise costs. Different types of semiconductor devices can be formed on the same substrate, which improves process integration, shortens the process cycle, and reduces the cost of manufacturing. It can accurately obtain the injection angle, flexibly control the width of the formed channel region, adjust the performance of the semiconductor device, and at the same time reduce the impurity ion concentration in the source and drain regions on both sides to reduce leakage.

[0065] The above description of the illustrated embodiments of the present invention (including the contents described in the Abstract) is not intended to be an exhaustive list or to limit the present invention to the precise form disclosed herein. Although specific embodiments of the present invention and examples of the present invention are described herein for illustrative purposes only, various equivalent modifications are possible within the spirit and scope of the present invention as will be recognized and appreciated by those skilled in the art. As noted, these modifications may be made to the present invention in accordance with the above description of the embodiments described in the present invention, and these modifications will be within the spirit and scope of the present invention.

[0066] The above description is only a preferred embodiment of the present application and an explanation of the technical principles used. Those skilled in the art should understand that the scope of the invention involved in the present application is not limited to the technical solution formed by a specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the inventive concept, such as the technical solution formed by replacing the above features with the technical features with similar functions disclosed in this application (but not limited to). In addition to the technical features described in the specification, the remaining technical features are known technologies to those skilled in the art. In order to highlight the innovative features of the present invention, the remaining technical features will not be described in detail here.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: The following steps are involved: Providing a substrate, the substrate comprising at least a first region and a second region; forming a shallow trench isolation structure between the first region and the second region; Forming a first patterned photoresist layer on the substrate, wherein the long side direction of the opening of the first patterned photoresist layer is parallel to the channel width direction of the semiconductor device, and the first patterned photoresist layer exposes the first region and a portion of the shallow trench isolation structure on both sides of the first region; Using the first patterned photoresist layer as a mask, performing two oblique ion implantations on the first region to form a first channel doping region; the first channel doping region includes a first sub-portion and a second sub-portion, and the second sub-portion is located on both sides of the first sub-portion; Removing the first patterned photoresist layer, forming a second patterned photoresist layer on the substrate, wherein the long side direction of the opening of the second patterned photoresist layer is parallel to the channel width direction of the semiconductor device, and the second patterned photoresist layer exposes the second region and a portion of the shallow trench isolation structure on both sides of the second region; Using the second patterned photoresist layer as a mask, performing two oblique ion implantations on the second region to form a second channel doping region; the second channel doping region includes a third subdivision and a fourth subdivision, and the fourth subdivision is located on both sides of the third subdivision; forming a gate on the first channel doping region and the second channel doping region; as well as forming lightly doped regions on both sides of the gate; A heavily doped region is formed in the second sub-portion and the fourth sub-portion for forming a source and a drain.

2. The method for manufacturing a semiconductor device according to claim 1, wherein: The doping concentration of the first section is twice the doping concentration of the second section, and the widths of the second sections on both sides of the first section are equal.

3. The method for manufacturing a semiconductor device according to claim 1, wherein: The doping concentration of the third section is twice the doping concentration of the fourth section, and the widths of the fourth sections on both sides of the third section are equal.

4. The method for manufacturing a semiconductor device according to claim 3, wherein: The gate is disposed on the first subsection and the third subsection, and an edge of the gate is aligned with an edge of the first subsection or the third subsection.

5. The method for manufacturing a semiconductor device according to claim 1, wherein: When performing two tilted ion implantations, after the first tilted ion implantation, the substrate is rotated 180 degrees in plane, or the ion implantation direction is adjusted, and the second tilted ion implantation is performed.

6. The method for manufacturing a semiconductor device according to claim 1, wherein: When two oblique ion implantations are performed in the first region or the second region, a pad oxide layer is provided on the substrate, the pad oxide layer is used as an ion implantation buffer layer, a well region is formed in the first region or the second region, and a channel doping region is provided on the well region.

7. The method for manufacturing a semiconductor device according to claim 6, wherein: The two inclined ion implantations in the first region or the second region have the same implantation angles and the same implanted ion amounts.

8. The method for manufacturing a semiconductor device according to claim 6, wherein: The injection angle α of the inclined ion implantation is obtained according to the formula α=arctan(H / D), wherein the injection angle α is the angle between the ion implantation direction and the substrate, H is the thickness of the first patterned photoresist layer or the second patterned photoresist layer on the pad oxide layer, and D is the distance from the boundary of the gate to the adjacent edge of the first patterned photoresist layer or the second patterned photoresist layer.

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