A three-dimensional electrode detector and its fabrication method

Abstract

This invention provides a three-dimensional electrode detector and its fabrication method, relating to the field of three-dimensional electrode detector technology. The fabrication process of the three-dimensional electrode detector provided by this invention does not involve multiple deep trench etching processes, and the fabrication process provided by this invention is simple, making it highly feasible.

Description

Technical Field

[0001] This invention relates to the field of three-dimensional electrode detector technology, and more specifically, to a three-dimensional electrode detector and its fabrication method. Background Technology

[0002] Three-dimensional electrode detectors (TEDs) have promising applications in high-energy particle or X-ray photon detection in radiation-related fields such as large scientific facilities, aerospace, and nuclear medicine due to their superior response speed, radiation resistance, low total depletion voltage, and high integration. However, the fabrication process of existing TEDs is relatively complex, resulting in poor feasibility. Summary of the Invention

[0003] In view of this, the present invention provides a three-dimensional electrode detector and its manufacturing method, which effectively solves the technical problems existing in the prior art, simplifies the manufacturing process of the three-dimensional electrode detector, and makes it more feasible.

[0004] To achieve the above objectives, the technical solution provided by the present invention is as follows:

[0005] A method for fabricating a three-dimensional electrode detector, the method comprising:

[0006] A substrate structure is provided, the substrate structure comprising a semiconductor bottom layer, an intermediate dielectric buried layer and a semiconductor top layer stacked sequentially;

[0007] Ion implantation doping is performed on the surface of the semiconductor top layer to form multiple guard ring doped portions and intermediate doped portions located in the guard ring doped portions;

[0008] The semiconductor top layer is etched outside the doped portion of the protective ring until the intermediate dielectric buried layer is exposed to form multiple monomer structures spaced apart from each other;

[0009] Initial doped portions are formed on the outer surface of the exposed surfaces of the monomer structure and the intermediate dielectric buried layer;

[0010] At the monomer structure, a mask layer is formed on the side of the initial doped portion away from the semiconductor substrate and outside the guard ring doped portion;

[0011] The initial doped portion is etched to form an edge doped portion corresponding to the monomer structure, and the intermediate dielectric buried layer is etched to form a monomer dielectric buried layer corresponding to the monomer structure. The edge doped portion, the monomer dielectric buried layer, and the monomer structure constitute a monomer electrode structure. The edge doped portion exposes the guard ring doped portion and the surrounding area of ​​the guard ring doped portion. Adjacent edge doped portions are isolated at intervals between adjacent monomer structures, and adjacent monomer dielectric buried layers are isolated at intervals between adjacent monomer structures.

[0012] Remove the mask layer;

[0013] An insulating layer is formed on the side of the single electrode structure away from the semiconductor substrate. The insulating layer includes an edge cutout and a center cutout. The edge cutout exposes the edge doped portion, and the center cutout exposes the center doped portion.

[0014] An edge connection electrode is formed at the edge cutout and contacts the edge doped portion, and an intermediate connection electrode is formed at the middle cutout and contacts the intermediate doped portion.

[0015] Optionally, after forming the edge connecting electrode and the intermediate connecting electrode, the fabrication method further includes:

[0016] A passivation layer is formed to cover the insulating layer, the edge connection electrode, and the middle connection electrode on the surface opposite to the semiconductor bottom layer;

[0017] The passivation layer is etched to form pad cutouts that expose the edge connection electrode and the middle connection electrode.

[0018] Optionally, etching the semiconductor top layer outside the doped portion of the guard ring until the intermediate dielectric buried layer is exposed to form a plurality of spaced-apart monomer structures includes:

[0019] The semiconductor top layer is etched outside the doped portion of the protective ring until the intermediate dielectric buried layer is exposed to form a plurality of spaced-apart monomer structures. The cross-section of the monomer structure in the first direction tends to decrease in the second direction. The second direction is the direction from the semiconductor top layer to the semiconductor bottom layer, and the first direction is perpendicular to the second direction.

[0020] Optionally, the step of forming an initial doped portion on the exposed surface of the monomer structure and the intermediate dielectric buried layer includes:

[0021] An initial doped portion is formed on the outer side of the exposed surface of the monomer structure and the intermediate dielectric buried layer by employing an in-situ doping process or a phosphorus silicate glass doping process.

[0022] Optionally, forming a mask layer at the monomer structure on the side of the initial doped portion away from the semiconductor substrate and located outside the guard ring doped portion includes:

[0023] A deposition mask material layer covers the surface of the initial doped portion away from the semiconductor substrate, and also covers the region between adjacent monomer structures that is separated from the semiconductor substrate.

[0024] The mask material layer is etched to form a mask layer, wherein, at the monomer structure, the mask layer is located on the side of the initial doped portion away from the semiconductor substrate and outside the guard ring doped portion.

[0025] Optionally, etching the initial doped portion to form an edge doped portion corresponding to the monomer structure, and etching the intermediate dielectric buried layer to form a monomer dielectric buried layer corresponding to the monomer structure, includes:

[0026] The initial doped portion and the intermediate dielectric buried layer are etched using a back etching process. The initial doped portion is etched to form an edge doped portion corresponding to the monomer structure, and the intermediate dielectric buried layer is etched to form a monomer dielectric buried layer corresponding to the monomer structure.

[0027] Based on the same inventive concept, the present invention also provides a three-dimensional electrode detector, comprising:

[0028] Semiconductor substrate;

[0029] A plurality of single-cell electrode structures are located on the semiconductor substrate. Each single-cell electrode structure includes: a single-cell dielectric buried layer on the semiconductor substrate and a single-cell structure located on the side of the single-cell dielectric buried layer away from the semiconductor substrate. Each single-cell structure includes a single-cell semiconductor top layer located on the side of the single-cell dielectric buried layer away from the semiconductor substrate, a guard ring doped portion formed by ion implantation doping on the surface of the single-cell semiconductor top layer, and an intermediate doped portion located within the guard ring doped portion. Furthermore, each single-cell electrode structure includes: an edge doped portion covering the surface of the single-cell dielectric buried layer away from the semiconductor substrate and the exposed surface of the single-cell structure, the edge doped portion exposing the guard ring doped portion and the surrounding region of the guard ring doped portion.

[0030] An insulating layer located on the side of the single electrode structure opposite to the semiconductor bottom layer, the insulating layer includes edge cutouts and center cutouts, the edge cutouts exposing the edge doped portion, and the center cutouts exposing the center doped portion;

[0031] In addition, an edge connection electrode located at the edge cutout and in contact with the edge doped portion, and an intermediate connection electrode located at the middle cutout and in contact with the middle doped portion.

[0032] Optionally, the three-dimensional electrode detector further includes:

[0033] A passivation layer that at least covers the insulating layer, the passivation layer including pad cutouts that expose the edge connection electrode and the intermediate connection electrode.

[0034] Optionally, the cross-section of the monomer structure in the first direction tends to decrease in the second direction, where the second direction is the direction from the top layer of the monomer semiconductor to the bottom layer of the semiconductor, and the first direction is perpendicular to the second direction.

[0035] Optionally, at least one of the semiconductor bottom layer and the single semiconductor top layer is made of one or more combinations of Si, GaN, SiC, HgI2, GaAs, TiBr, CdTe, CdZnTe, CdSe, GaP, HgS, PbI2 and AlSb.

[0036] The thickness of the top layer of the single semiconductor is 5-20 micrometers;

[0037] The thickness of the monomeric medium buried layer is 1-3 micrometers.

[0038] Compared with the prior art, the technical solution provided by the present invention has at least the following advantages:

[0039] This invention provides a three-dimensional electrode detector and its fabrication method. The fabrication method includes: providing a substrate structure; performing ion implantation doping on the surface of the top semiconductor layer to form multiple guard ring doped portions and intermediate doped portions located within the guard ring doped portions; etching the top semiconductor layer outside the guard ring doped portions until the intermediate dielectric buried layer is exposed to form multiple spaced-apart monomer structures; doping to form initial doped portions outside the exposed surfaces of the monomer structures and the intermediate dielectric buried layer; forming a mask layer at the monomer structure on the side of the initial doped portion away from the bottom semiconductor layer and located outside the guard ring doped portions; etching the initial doped portion... An edge-doped portion corresponding to the monomer structure is formed by etching the intermediate dielectric buried layer, and a monomer dielectric buried layer corresponding to the monomer structure is formed by etching the intermediate dielectric buried layer. The edge-doped portion, the monomer dielectric buried layer, and the monomer structure constitute a monomer electrode structure. The mask layer is removed. An insulating layer is formed on the side of the monomer electrode structure away from the semiconductor substrate. The insulating layer includes edge cutouts and center cutouts. The edge cutouts expose the edge-doped portion, and the center cutouts expose the intermediate-doped portion. An edge connecting electrode is formed at the edge cutout to contact and connect with the edge-doped portion, and an intermediate connecting electrode is formed at the center cutout to contact and connect with the intermediate-doped portion. It can be seen that the fabrication process of the three-dimensional electrode detector provided by the present invention does not involve multiple deep trench etching processes. The fabrication process provided by the present invention is simple, making it highly feasible. Attached Figure Description

[0040] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0041] Figure 1 A flowchart illustrating a method for fabricating a three-dimensional electrode detector according to an embodiment of the present invention;

[0042] Figure 2 A flowchart illustrating another method for fabricating a three-dimensional electrode detector as provided in an embodiment of the present invention;

[0043] Figures 3a to 3k for Figure 2 The corresponding structural diagrams for each step in the process. Detailed Implementation

[0044] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0045] As described in the background section, three-dimensional electrode detectors, due to their superior response speed, radiation resistance, low total depletion voltage, and high integration, have promising applications in the detection of high-energy particles or X-ray photons in radiation fields such as large scientific facilities, aerospace, and nuclear medicine. However, the fabrication process of existing three-dimensional electrode detectors is relatively complex, resulting in poor feasibility.

[0046] Based on this, embodiments of the present invention provide a three-dimensional electrode detector and its fabrication method, effectively solving the technical problems existing in the prior art, simplifying the fabrication process of the three-dimensional electrode detector, and making it more feasible. The three-dimensional electrode detector provided by the embodiments of the present invention, by changing the dimensions of related components, can be applied to scenarios such as lidar detection, medical diagnosis, large scientific facilities, aerospace, and other high-radiation environments.

[0047] To achieve the above objectives, the technical solutions provided by the embodiments of the present invention are as follows, in detail... Figures 1 to 3k The technical solutions provided in the embodiments of the present invention will be described in detail.

[0048] refer to Figure 1The diagram shows a flowchart of a method for fabricating a three-dimensional electrode detector according to an embodiment of the present invention. The method for fabricating the three-dimensional electrode detector includes:

[0049] S1. Provide a substrate structure, the substrate structure comprising a semiconductor bottom layer, an intermediate dielectric buried layer and a semiconductor top layer stacked sequentially.

[0050] S2. Ion implantation doping is performed on the surface of the semiconductor top layer to form multiple guard ring doped portions and intermediate doped portions located in the guard ring doped portions.

[0051] S3. Etch the semiconductor top layer outside the doped portion of the protective ring until the intermediate dielectric buried layer is exposed to form multiple monomer structures spaced apart from each other.

[0052] S4. Initial doped portions are formed on the outer side of the exposed surface of the monomer structure and the intermediate dielectric buried layer.

[0053] S5. At the monomer structure, a mask layer is formed on the side of the initial doped portion away from the semiconductor bottom layer and located outside the doped portion of the protective ring.

[0054] S6. Etching the initial doped portion to form an edge doped portion corresponding to the monomer structure, and etching the intermediate dielectric buried layer to form a monomer dielectric buried layer corresponding to the monomer structure, wherein the edge doped portion, the monomer dielectric buried layer, and the monomer structure constitute a monomer electrode structure, wherein the edge doped portion exposes the guard ring doped portion and the surrounding area of ​​the guard ring doped portion, adjacent edge doped portions are isolated at intervals between adjacent monomer structures, and adjacent monomer dielectric buried layers are isolated at intervals between adjacent monomer structures.

[0055] S7. Remove the mask layer.

[0056] S8. An insulating layer is formed on the side of the single electrode structure away from the semiconductor substrate. The insulating layer includes edge cutouts and center cutouts. The edge cutouts expose the edge doped portion, and the center cutouts expose the center doped portion.

[0057] S9. An edge connection electrode is formed at the edge hollowing-out area to contact and connect with the edge doped part, and an intermediate connection electrode is formed at the middle hollowing-out area to contact and connect with the intermediate doped part.

[0058] As can be seen from the above, the technical solution provided by the embodiments of the present invention uses the intermediate doped portion in the three-dimensional electrode detector as the collecting electrode, which has a small capacitance. Furthermore, during the fabrication of the three-dimensional electrode detector, the top layer of the semiconductor is etched into multiple monomer structures, resulting in a more uniform electric field distribution within the effective sensitive area, thus improving the performance of the three-dimensional electrode detector. For example, the three-dimensional electrode detector has advantages such as radiation resistance, fast response, and better electric field distribution. The three-dimensional electrode detector provided by the embodiments of the present invention can even simulate human cells for use in microdosimetry. In addition, the fabrication process of the three-dimensional electrode detector provided by the embodiments of the present invention does not involve multiple deep trench etching processes; therefore, the fabrication process of the three-dimensional electrode detector provided by the embodiments of the present invention is simple, making it highly feasible.

[0059] To further improve the performance of the three-dimensional electrode detector, the three-dimensional electrode detector provided in this embodiment of the invention may further include a passivation layer. (Reference) Figure 2 The diagram shows a flowchart of another method for fabricating a three-dimensional electrode detector according to an embodiment of the present invention. After forming the edge connecting electrode and the intermediate connecting electrode in step S9, the fabrication method further includes:

[0060] S10. A passivation layer is formed to cover the insulating layer, the edge connection electrode, and the middle connection electrode on the side of the semiconductor substrate facing away from the substrate.

[0061] S11. Etch the passivation layer to form pad cutouts that expose the edge connection electrode and the middle connection electrode.

[0062] Combination Figures 2 to 3k The technical solutions provided in the embodiments of the present invention will be described in more detail below. Figures 3a to 3k for Figure 2 The corresponding structural diagrams for each step in the process.

[0063] like Figure 3a As shown, corresponding to step S1, a substrate structure is provided.

[0064] The substrate structure provided in this embodiment of the invention is formed by SOI (Silicon-On-Insulator) related processes. The substrate structure includes a semiconductor bottom layer 110, an intermediate dielectric buried layer 120 and a semiconductor top layer 130 stacked sequentially.

[0065] In one embodiment of the present invention, at least one of the semiconductor bottom layer 110 and the semiconductor top layer 130 provided in this embodiment is made of one or more combinations of Si, GaN, SiC, HgI2, GaAs, TiBr, CdTe, CdZnTe, CdSe, GaP, HgS, PbI2, and AlSb. The thickness of the semiconductor top layer 130 is 5-20 micrometers. Furthermore, the intermediate dielectric buried layer 120 can be a pre-buried N-type doped layer or a P-type doped layer. Optionally, the intermediate dielectric buried layer 120 provided in this embodiment is a silicon dioxide layer, wherein the thickness of the intermediate dielectric buried layer 120 is 1-3 micrometers.

[0066] like Figure 3b As shown, corresponding to step S2, ion implantation doping is performed on the surface of the semiconductor top layer 130 to form a plurality of guard ring doped portions 210 and intermediate doped portions 220 located in the guard ring doped portions 210.

[0067] First, protective ion implantation is performed on the surface of the top semiconductor layer 130 on the side opposite to the bottom semiconductor layer 110 to form a protective ring doped region 210. The protective ring doped region 210 is P-type doped with a doping concentration ranging from 1×10⁻⁶. 16 cm- 3 -1×10 19 cm- 3 The protective ring doped portion 210 can be a closed or non-closed ring, such as a circular ring, a square ring, or a polygonal ring, and the present invention does not impose specific limitations on this.

[0068] Then, protective ion implantation is performed on the surface of the top semiconductor layer 130 facing away from the bottom semiconductor layer 110, within the surrounding region of the ring-shaped doped portion 210, to form an intermediate doped portion 220. The intermediate doped portion 220 can be dot-shaped (e.g., circular or elliptical dots) or sheet-shaped (e.g., rectangular or polygonal sheets), and the implantation energy is slightly higher than that of the protective ring doped portion 210, such as above 200 keV. The intermediate doped portion 220 is either P-type or N-type doped, and the doping type of the intermediate doped portion 220 is opposite to that of the intermediate dielectric buried layer 120 (e.g., if the intermediate doped portion 220 is N-type doped, then the intermediate dielectric buried layer 120 is P-type doped; or if the intermediate doped portion 220 is P-type doped, then the intermediate dielectric buried layer 120 is N-type doped). The doping concentration range of the intermediate doped portion 220 is 1 × 10⁻⁶. 16 cm- 3 -1×10 19 cm- 3 .

[0069] like Figure 3cAs shown, corresponding to step S3, the semiconductor top layer 130 is etched on the outside of the doped portion 210 of the protection ring until the intermediate dielectric buried layer 120 is exposed to form a plurality of interspaced monomer structures, wherein the semiconductor top layer 130 is etched into a monomer semiconductor top layer 131 in the monomer structure.

[0070] In one embodiment of the present invention, the etching of the semiconductor top layer 130 provided in this embodiment can be performed using a wet etching process or a dry etching process, and the present invention does not impose specific limitations on this. Specifically, after etching the semiconductor top layer 130, gradient holes can be formed between adjacent individual semiconductor top layers; that is, the etching of the semiconductor top layer outside the doped portion 210 of the guard ring until the intermediate dielectric buried layer 120 is exposed to form a plurality of mutually spaced individual structures provided in this embodiment of the present invention includes: etching the semiconductor top layer 130 outside the doped portion 210 of the guard ring until the intermediate dielectric buried layer 120 is exposed to form a plurality of mutually spaced individual structures, wherein the cross section of the individual structure in the first direction X has a decreasing trend in the second direction Y, the second direction Y is the direction from the semiconductor top layer 130 toward the semiconductor bottom layer 110, and the first direction X is perpendicular to the second direction Y.

[0071] In other words, the cross-section of the single semiconductor top layer 131 in the first direction X provided in this embodiment of the invention has a decreasing trend in the second direction Y, where the second direction Y is the direction from the single semiconductor top layer 131 toward the semiconductor bottom layer 110, and the first direction X is perpendicular to the second direction Y. Optionally, the cross-section of the single structure (i.e., the single semiconductor top layer 131) in the second direction Y provided in this embodiment of the invention can be trapezoidal, or the side line of the cross-section of the single structure (i.e., the single semiconductor top layer 131) in the second direction Y can be curved. Thus, by fabricating the single structure into a near-hemispherical electrode, a more uniform electric field distribution is achieved within the effective sensitive area, and there is no local high electric field, thereby improving the performance of the three-dimensional electrode detector.

[0072] like Figure 3d As shown, corresponding to step S4, an initial doped portion 300 is formed on the outer side of the exposed surface of the monomer structure and the intermediate medium buried 120.

[0073] The initial doped portion 300 provided in this embodiment of the invention can be P-type doped or N-type doped, and the doping type of the initial doped portion 300 is the same as the doping type of the intermediate dielectric buried layer 120, while the doping type of the initial doped portion 300 is opposite to the doping type of the intermediate doped portion 220; that is, when the initial doped portion 300 and the intermediate dielectric buried layer 120 are N-type doped, the intermediate doped portion 220 is P-type doped; or, when the initial doped portion 300 and the intermediate dielectric buried layer 120 are P-type doped, the intermediate doped portion 220 is N-type doped. The doping concentration range of the initial doped portion 300 is 1 × 10⁻⁶. 16 cm- 3 -1×10 19 cm- 3 .

[0074] In one embodiment of the present invention, the method of forming an initial doped portion 300 on the outer side of the exposed surface of the monomer structure and the intermediate dielectric buried layer 130 provided by the present invention includes: forming the initial doped portion 300 on the outer side of the exposed surface of the monomer structure and the intermediate dielectric buried layer 120 by using an in-situ doping process or a phosphorus silicate glass doping process with better step coverage, wherein, at the gap between adjacent monomer structures, that is, at the groove etched between adjacent monomer structures, the initial doped portion 300 does not seal the opening of the groove.

[0075] like Figure 3e As shown, corresponding to step S5, at the monomer structure, a mask layer 400 is formed on the side of the initial doped portion 300 away from the semiconductor bottom layer 110 and outside the protective ring doped portion 210.

[0076] In one embodiment of the present invention, the mask layer 400 provided in this embodiment can be an oxide layer. Specifically, the step of forming a mask layer 400 at the monomer structure on the side of the initial doped portion 300 away from the semiconductor substrate 110 and outside the guard ring doped portion 210 includes: depositing a mask material layer to cover the surface of the initial doped portion 300 away from the semiconductor substrate 110 and to cover the region between adjacent monomer structures that is separated from the semiconductor substrate 110; etching the mask material layer to form the mask layer 400, wherein, at the monomer structure, the mask layer 400 is located on the side of the initial doped portion 300 away from the semiconductor substrate 110 and outside the guard ring doped portion 210.

[0077] The mask material layer provided in this embodiment of the invention can be an oxide material layer deposited by CVD (Chemical Vapor Deposition) or other methods, and then the mask material layer is etched by photolithography combined with dry etching to obtain mask layer 400.

[0078] like Figure 3f As shown, corresponding to step S6, the initial doped portion 300 is etched to form an edge doped portion 310 corresponding to the monomer structure, and the intermediate dielectric buried layer 120 is etched to form a monomer dielectric buried layer 121 corresponding to the monomer structure. The edge doped portion 310, the monomer dielectric buried layer 121, and the monomer structure constitute a monomer electrode structure. The edge doped portion 310 exposes the guard ring doped portion 210 and the surrounding area of ​​the guard ring doped portion 210. Adjacent edge doped portions 310 are isolated at intervals between adjacent monomer structures, and adjacent monomer dielectric buried layers 121 are isolated at intervals between adjacent monomer structures.

[0079] In one embodiment of the present invention, the etching of the initial doped portion 300 and the intermediate dielectric buried layer 120 can be performed using a back-etch process. Specifically, the etching of the initial doped portion 300 to form the edge doped portion 310 corresponding to the monomer structure, and the etching of the intermediate dielectric buried layer 120 to form the monomer dielectric buried layer 121 corresponding to the monomer structure, provided in this embodiment of the present invention, includes: etching the initial doped portion 300 and the intermediate dielectric buried layer 120 using a back-etch process; etching the initial doped portion 300 to form the edge doped portion 310 corresponding to the monomer structure; and etching the intermediate dielectric buried layer 120 to form the monomer dielectric buried layer 121 corresponding to the monomer structure. The etching of the initial doped portion 300 and the intermediate dielectric buried layer 120 using the back-etch process can be divided into two steps: the first step is to quickly and uniformly etch away most of the material; the second step is to reduce the etching rate and continue etching to avoid pitting. Specifically, at the gaps between adjacent monomer structures, adjacent monomer dielectric buried layers 121 must be etched to isolate them and avoid electrical crosstalk between adjacent monomer electrode structures.

[0080] like Figure 3g As shown, corresponding to step S7, the mask layer 400 is removed.

[0081] Optionally, in embodiments of the present invention, the mask layer 400 can be removed using a dry or wet removal process.

[0082] like Figure 3hAs shown, corresponding to step S8, an insulating layer 500 is formed on the side of the single electrode structure away from the semiconductor bottom layer 110. The insulating layer 500 includes edge cutouts and center cutouts. The edge cutouts expose the edge doped portion 310, and the center cutouts expose the center doped portion 220.

[0083] The insulating layer provided in this embodiment of the invention can be an oxide layer. Specifically, an insulating material layer can be deposited or grown on the side of the single electrode away from the semiconductor substrate 110, and then the insulating material layer can be etched using a photolithography process to form an insulating layer 500. The insulating layer 500 includes edge cutouts of exposed edge doped portions 310 and intermediate cutouts including exposed intermediate doped portions 220.

[0084] like Figure 3i As shown, corresponding to step S9, an edge connection electrode 610 is formed at the edge hollow and is in contact with the edge doped portion 310, and an intermediate connection electrode 620 is formed at the middle hollow and is in contact with the intermediate doped portion 220.

[0085] The edge connecting electrode 610 and the middle connecting electrode 620 provided in this embodiment of the invention can be electrodes made of metal or alloy, such as metal Al or AlCu alloy, etc. They can be formed by combining metal magnetron sputtering process and metal patterning process. This invention does not impose specific limitations on this.

[0086] like Figure 3j As shown, corresponding to step S10, a passivation layer 600 is formed to cover the insulating layer 500, the edge connection electrode 610 and the intermediate connection electrode 620 on the side of the semiconductor bottom layer 110 away from the semiconductor bottom layer 110.

[0087] The passivation layer 600 provided in this embodiment of the invention can be a dielectric material such as silicon oxide or silicon nitride, and the invention does not impose specific limitations on it.

[0088] like Figure 3k As shown, corresponding to step S11, the passivation layer 600 is etched to form pad cutouts that expose the edge connection electrode and the middle connection electrode. The passivation layer 600 can be etched to form the pad cutouts using photolithography, and the present invention does not impose specific limitations on this.

[0089] Based on the same inventive concept, embodiments of the present invention also provide a three-dimensional electrode detector. Specifically, this can be combined with… Figure 3k The three-dimensional electrode detector shown includes:

[0090] Semiconductor bottom layer 110.

[0091] The semiconductor substrate 110 includes multiple single-electrode structures, each comprising: a single-electrode buried dielectric layer 121 on the semiconductor substrate 110 and a single-electrode structure on the side of the single-electrode buried dielectric layer 121 facing away from the semiconductor substrate 110. Each single-electrode structure includes a single-electrode semiconductor top layer 131 on the side of the single-electrode buried dielectric layer 121 facing away from the semiconductor substrate 110, a guard ring doped portion 210 formed by ion implantation doping on the surface of the single-electrode semiconductor top layer 131, and an intermediate doped portion 220 within the guard ring doped portion 210. Furthermore, each single-electrode structure includes an edge doped portion 310 covering the surface of the single-electrode buried dielectric layer 121 facing away from the semiconductor substrate 110 and the exposed surface of the single-electrode structure. The edge doped portion 310 exposes the guard ring doped portion 210 and the surrounding area of ​​the guard ring doped portion 210.

[0092] An insulating layer 500 is located on the side of the single electrode structure opposite to the semiconductor substrate 110. The insulating layer 500 includes edge cutouts and center cutouts. The edge cutouts expose the edge doped portion 310, and the center cutouts expose the intermediate doped portion 220. An edge connection electrode 610 is located at the edge cutout and in contact with the edge doped portion 310, and an intermediate connection electrode 620 is located at the center cutout and in contact with the intermediate doped portion 220.

[0093] Furthermore, the three-dimensional electrode detector provided in this embodiment of the invention further includes: a passivation layer 600 covering at least the insulating layer, the passivation layer 600 including pad cutouts exposing the edge connection electrode 610 and the intermediate connection electrode 620.

[0094] In one embodiment of the present invention, the cross-section of the monomer structure provided in the embodiment of the present invention in the first direction X has a decreasing trend in the second direction Y, the second direction Y being the direction from the top layer 131 of the monomer semiconductor to the bottom layer 110 of the semiconductor, and the first direction X is perpendicular to the second direction Y.

[0095] In one embodiment of the present invention, at least one of the semiconductor bottom layer 110 and the single semiconductor top layer 131 provided in the present invention is made of one or more combinations of Si, GaN, SiC, HgI2, GaAs, TiBr, CdTe, CdZnTe, CdSe, GaP, HgS, PbI2 and AlSb; the thickness of the single semiconductor top layer 131 is 5-20 micrometers; the thickness of the single dielectric buried layer 121 is 1-3 micrometers, wherein the thickness is the thickness of the structural layer in the second direction Y.

[0096] This invention provides a three-dimensional electrode detector and its fabrication method. The fabrication method includes: providing a substrate structure; performing ion implantation doping on the surface of the top semiconductor layer to form multiple guard ring doped portions and intermediate doped portions located within the guard ring doped portions; etching the top semiconductor layer outside the guard ring doped portions until the intermediate dielectric buried layer is exposed to form multiple spaced-apart monomer structures; doping the exposed surfaces of the monomer structures and the intermediate dielectric buried layer to form initial doped portions; forming a mask layer at the monomer structure on the side of the initial doped portion away from the bottom semiconductor layer and located outside the guard ring doped portions; etching the initial doped portion... The doped portion forms an edge doped portion corresponding to the monomer structure, and the intermediate dielectric buried layer is etched to form a monomer dielectric buried layer corresponding to the monomer structure. The edge doped portion, the monomer dielectric buried layer, and the monomer structure constitute a monomer electrode structure. The mask layer is removed. An insulating layer is formed on the side of the monomer electrode structure away from the semiconductor substrate. The insulating layer includes edge cutouts and center cutouts. The edge cutouts expose the edge doped portion, and the center cutouts expose the intermediate doped portion. An edge connecting electrode is formed at the edge cutout to contact and connect with the edge doped portion, and an intermediate connecting electrode is formed at the center cutout to contact and connect with the intermediate doped portion. It can be seen that the fabrication process of the three-dimensional electrode detector provided by the embodiment of the present invention does not involve multiple deep trench etching processes. The fabrication process provided by the embodiment of the present invention is simple, making it highly feasible.

[0097] In the description of this invention, it should be understood that terms such as "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0098] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0099] In this invention, unless otherwise explicitly specified and limited, terms such as "installation," "connection," "linking," and "fixing" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection, an electrical connection, or a connection that allows communication between components; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components, unless otherwise explicitly limited. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0100] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can mean that the first feature is in direct contact with the second feature, or that the first feature is in indirect contact with the second feature through an intermediate medium. Furthermore, "above," "over," and "on top" of the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0101] In this invention, the terms "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0102] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention.

Claims

1. A method for fabricating a three-dimensional electrode detector, characterized in that, The production method includes: A substrate structure is provided, the substrate structure comprising a semiconductor bottom layer, an intermediate dielectric buried layer and a semiconductor top layer stacked sequentially; Ion implantation doping is performed on the surface of the semiconductor top layer to form multiple guard ring doped portions and intermediate doped portions located in the guard ring doped portions; The semiconductor top layer is etched outside the doped portion of the protective ring until the intermediate dielectric buried layer is exposed to form multiple monomer structures spaced apart from each other; Initial doped portions are formed on the outer surface of the exposed surfaces of the monomer structure and the intermediate dielectric buried layer; At the monomer structure, a mask layer is formed on the side of the initial doped portion away from the semiconductor substrate and outside the guard ring doped portion; The initial doped portion is etched to form an edge doped portion corresponding to the monomer structure, and the intermediate dielectric buried layer is etched to form a monomer dielectric buried layer corresponding to the monomer structure. The edge doped portion, the monomer dielectric buried layer, and the monomer structure constitute a monomer electrode structure. The edge doped portion exposes the guard ring doped portion and the surrounding area of ​​the guard ring doped portion. Adjacent edge doped portions are isolated at intervals between adjacent monomer structures, and adjacent monomer dielectric buried layers are isolated at intervals between adjacent monomer structures. Remove the mask layer; An insulating layer is formed on the side of the single electrode structure away from the semiconductor substrate. The insulating layer includes an edge cutout and a center cutout. The edge cutout exposes the edge doped portion, and the center cutout exposes the center doped portion. An edge connection electrode is formed at the edge cutout and contacts the edge doped portion, and an intermediate connection electrode is formed at the middle cutout and contacts the intermediate doped portion.

2. The method for fabricating a three-dimensional electrode detector according to claim 1, characterized in that, After forming the edge connection electrode and the intermediate connection electrode, the fabrication method further includes: A passivation layer is formed to cover the insulating layer, the edge connection electrode, and the middle connection electrode on the surface opposite to the semiconductor bottom layer; The passivation layer is etched to form pad cutouts that expose the edge connection electrode and the middle connection electrode.

3. The method for fabricating a three-dimensional electrode detector according to claim 1, characterized in that, The etching of the semiconductor top layer outside the doped portion of the protective ring until the intermediate dielectric buried layer is exposed to form a plurality of spaced-apart monomer structures includes: The semiconductor top layer is etched outside the doped portion of the protective ring until the intermediate dielectric buried layer is exposed to form a plurality of spaced-apart monomer structures. The cross-section of the monomer structure in the first direction tends to decrease in the second direction. The second direction is the direction from the semiconductor top layer to the semiconductor bottom layer, and the first direction is perpendicular to the second direction.

4. The method for fabricating a three-dimensional electrode detector according to claim 1, characterized in that, The process of forming an initial doped portion on the exposed surface of the monomer structure and the intermediate dielectric buried layer includes: An initial doped portion is formed on the outer side of the exposed surface of the monomer structure and the intermediate dielectric buried layer by employing an in-situ doping process or a phosphorus silicate glass doping process.

5. The method for fabricating a three-dimensional electrode detector according to claim 1, characterized in that, The formation of a mask layer at the monomer structure, on the side of the initial doped portion away from the semiconductor substrate and located outside the guard ring doped portion, includes: A deposition mask material layer covers the surface of the initial doped portion away from the semiconductor substrate, and also covers the region between adjacent monomer structures that is separated from the semiconductor substrate. The mask material layer is etched to form a mask layer, wherein, at the monomer structure, the mask layer is located on the side of the initial doped portion away from the semiconductor substrate and outside the guard ring doped portion.

6. The method for fabricating a three-dimensional electrode detector according to claim 1, characterized in that, The etching of the initial doped portion to form an edge doped portion corresponding to the monomer structure, and the etching of the intermediate dielectric buried layer to form a monomer dielectric buried layer corresponding to the monomer structure, include: The initial doped portion and the intermediate dielectric buried layer are etched using a back etching process. The initial doped portion is etched to form an edge doped portion corresponding to the monomer structure, and the intermediate dielectric buried layer is etched to form a monomer dielectric buried layer corresponding to the monomer structure.

7. A three-dimensional electrode detector, characterized in that, include: Semiconductor substrate; A plurality of single-cell electrode structures are located on the semiconductor substrate. Each single-cell electrode structure includes: a single-cell dielectric buried layer on the semiconductor substrate and a single-cell structure located on the side of the single-cell dielectric buried layer away from the semiconductor substrate. Each single-cell structure includes a single-cell semiconductor top layer located on the side of the single-cell dielectric buried layer away from the semiconductor substrate, a guard ring doped portion formed by ion implantation doping on the surface of the single-cell semiconductor top layer, and an intermediate doped portion located within the guard ring doped portion. Furthermore, each single-cell electrode structure includes: an edge doped portion covering the surface of the single-cell dielectric buried layer away from the semiconductor substrate and the exposed surface of the single-cell structure, the edge doped portion exposing the guard ring doped portion and the surrounding region of the guard ring doped portion. An insulating layer located on the side of the single electrode structure opposite to the semiconductor bottom layer, the insulating layer includes edge cutouts and center cutouts, the edge cutouts exposing the edge doped portion, and the center cutouts exposing the center doped portion; In addition, an edge connection electrode located at the edge cutout and in contact with the edge doped portion, and an intermediate connection electrode located at the middle cutout and in contact with the middle doped portion.

8. The three-dimensional electrode detector according to claim 7, characterized in that, The three-dimensional electrode detector also includes: A passivation layer that at least covers the insulating layer, the passivation layer including pad cutouts that expose the edge connection electrode and the intermediate connection electrode.

9. The three-dimensional electrode detector according to claim 7, characterized in that, The cross-section of the monomer structure in the first direction tends to decrease in the second direction, where the second direction is the direction from the top layer of the monomer semiconductor to the bottom layer of the semiconductor, and the first direction is perpendicular to the second direction.

10. The three-dimensional electrode detector according to claim 7, characterized in that, At least one of the semiconductor bottom layer and the single semiconductor top layer is made of one or more combinations of Si, GaN, SiC, HgI2, GaAs, TiBr, CdTe, CdZnTe, CdSe, GaP, HgS, PbI2 and AlSb. The thickness of the top layer of the single semiconductor is 5-20 micrometers; The thickness of the monomeric medium buried layer is 1-3 micrometers.

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