Routing method between a printed circuit board, a processor, and a memory, and an electronic device

Abstract

The present invention discloses a wiring method between a printed circuit board, a processor and a memory, and an electronic device. The wiring method includes the steps of: (a) allowing the data signal routing path between the processor and the memory to be first from a first signal layer to a second signal layer, and then from the second signal layer to the first signal layer, wherein a first ground layer serving as a reference layer for the first signal layer and the second signal layer is located between the first signal layer and the second signal layer, and the first signal layer and the second signal layer both have a complete projection on the first ground layer; (b) allowing the address signal routing path between the processor and the memory to be first from a fourth signal layer to the second signal layer, and then from the second signal layer to the fourth signal layer, wherein a power supply layer serving as a reference layer for the fourth signal layer is located between the second signal layer and the fourth signal layer, and the fourth signal layer has a complete projection on the power supply layer.

Description

Technical Field

[0001] The present invention relates to a multilayer circuit board, and particularly to a wiring method between a printed circuit board, a processor, and a memory, and an electronic device. Background Art

[0002] In recent years, the technology of multilayer printed circuit boards has developed rapidly. Through multilayer layout, not only can more electronic components and circuits be accommodated in a limited space, enabling electronic devices using multilayer printed circuit boards to develop in the direction of miniaturization and light weight, but also a good wiring structure and multilayer protection can be provided to reduce the interference of external environmental factors on the circuit board. However, the design of printed circuit boards with a multilayer overlapping structure has also become complex, and the factors that need to be considered and noted during the design process have increased significantly. For example, how to ensure the return path of the multilayer printed circuit board during signal transmission is the key to ensuring the effective transmission of data. However, due to design defects in existing multilayer printed circuit boards, the ground layer cannot provide an effective return path for the signal layer, resulting in the signal layer being easily interfered by impedance mutations during signal propagation, causing signal emission and distortion, and thus leading to error codes or misoperations. Summary of the Invention

[0003] An object of the present invention is to provide a wiring method between a printed circuit board, a processor, and a memory, and an electronic device, wherein the ground layer and power layer of the printed circuit board are complete to provide a good return path for each signal layer.

[0004] An object of the present invention is to provide a wiring method between a printed circuit board, a processor, and a memory, and an electronic device, wherein during the process of transmitting signals on the signal layer of the printed circuit board, the impedance of the signal is the same at each moment, so that the characteristic impedance of the signal is constant, which is beneficial to avoiding error codes and misoperations.

[0005] An object of the present invention is to provide a wiring method between a printed circuit board, a processor, and a memory, and an electronic device, wherein the printed circuit board enables the signal return path to have a smaller impedance and ground noise.

[0006] An object of the present invention is to provide a wiring method between a printed circuit board, a processor, and a memory, and an electronic device, wherein the printed circuit board allows the equivalent lengths of each microstrip line and each stripline used to connect the processor pad and the memory pad to be equal, so as to meet the delay requirements of the signal.

[0007] According to an aspect of the present invention, the present invention provides a wiring method between a processor and a memory, wherein the wiring method includes the following steps:

[0008] (a)Allow the data signal routing path between the processor and the memory to first go from the first signal layer to the second signal layer, and then from the second signal layer to the first signal layer, where a first ground layer serving as the reference layer for the first signal layer and the second signal layer is located between the first signal layer and the second signal layer, and the first signal layer and the second signal layer both have a complete projection on the first ground layer; and

[0009] (b)Allow the address signal routing path between the processor and the memory to first go from the fourth signal layer to the second signal layer, and then from the second signal layer to the fourth signal layer, where a power supply layer serving as the reference layer for the fourth signal layer is located between the second signal layer and the fourth signal layer, and the fourth signal layer has a complete projection on the power supply layer.

[0010] In some possible implementation manners, in step (b), allow a second ground layer between the fourth signal layer and the power supply layer to couple the return path of the transmission line of the fourth signal layer to the power supply layer.

[0011] In some possible implementation manners, the dielectric thickness dimension parameter between the power supply layer and the second ground layer satisfies: 0.1mm ≤ ≤ 0.5mm.

[0012] In some possible implementation manners, in the above method, the first signal layer has a processor mounting area and a memory mounting area, and the memory mounting area extends from a position adjacent to one side of the processor mounting area in a direction perpendicular to this side of the processor mounting area.

[0013] In some possible implementation manners, in the above method, allow the equivalent lengths of the transmission lines connecting the processor pads and the memory pads of the first signal layer to be equal.

[0014] In some possible implementation manners, the step of equalizing the equivalent lengths of each transmission line further includes the following steps:

[0015] Obtain the equivalent length of each transmission line respectively;

[0016] Take the transmission line with the longest equivalent length as the reference line, and the remaining transmission lines as the target lines;

[0017] According to the equivalent length of the transmission line serving as the target line and the equivalent length of the transmission line serving as the reference line, obtain the length dimension that the transmission line serving as the target line needs to be extended;

[0018] According to the length dimension to be extended, extend the transmission line serving as the target line so that the equivalent length of the transmission line serving as the target line is equal to the equivalent length of the transmission line serving as the reference line.

[0019] In some possible embodiments, the equivalent length of the transmission line is the length of the microstrip line. In the step of extending the equivalent length of each of the target lines, according to the delay length, wind the wire on the outer layer to extend the actual length of each of the target lines.

[0020] In some possible embodiments, the equivalent length of the transmission line is the length of the stripline. In the step of extending the equivalent length of each of the target lines, according to the delay length, wind the wire on the inner layer to extend the actual length of each of the target lines.

[0021] According to another aspect of the present invention, the present invention further provides a printed circuit board, which includes:

[0022] A first signal layer located on the top layer;

[0023] A first ground layer located below the first signal layer, the first ground layer being the reference layer of the first signal layer, and the first signal layer having a complete projection on the first ground layer;

[0024] A second signal layer located below the first ground layer, the first ground layer being the reference layer of the second signal layer, and the second signal layer having a complete projection on the first ground layer;

[0025] A power supply layer located below the second signal layer;

[0026] A second ground layer and a third signal layer located below the power supply layer, the second ground layer and the third signal layer being on the same layer, the power supply layer being the reference layer of the third signal layer, and the third signal layer having a complete projection on the power supply layer; and

[0027] A fourth signal layer located below the second ground layer and the third signal layer, the power supply layer being the reference layer of the fourth signal layer, and the fourth signal layer having a complete projection on the power supply layer.

[0028] In some possible embodiments, the first signal layer has an adjacent processor mounting area and a memory mounting area, and the memory mounting area extends from a position adjacent to one side of the processor mounting area in a direction perpendicular to that side of the processor mounting area.

[0029] In some possible embodiments, the dielectric thickness dimension parameter between the power supply layer and the second ground layer Satisfies: 0.1mm ≤ ≤ 0.5mm.

[0030] In some possible embodiments, the equivalent lengths of all transmission lines for connecting the processor pads and the memory pads of the first signal layer are equal.

[0031] According to another aspect of the present invention, the present invention further provides an electronic device, which includes a printed circuit board, a processor and a memory mounted on the printed circuit board, wherein the printed circuit board includes:

[0032] A first signal layer located on the top layer;

[0033] A first ground layer located below the first signal layer, the first ground layer is the reference layer of the first signal layer, and the first signal layer has a complete projection on the first ground layer;

[0034] A second signal layer located below the first ground layer, the first ground layer is the reference layer of the second signal layer, and the second signal layer has a complete projection on the first ground layer;

[0035] A power layer located below the second signal layer;

[0036] A second ground layer and a third signal layer located below the power layer, the second ground layer and the third signal layer are on the same layer, the power layer is the reference layer of the third signal layer, and the third signal layer has a complete projection on the power layer; and

[0037] A fourth signal layer located below the second ground layer and the third signal layer, the power layer is the reference layer of the fourth signal layer, and the fourth signal layer has a complete projection on the power layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 is a three-dimensional schematic diagram of an electronic device according to a preferred embodiment of the present invention.

[0039] Figure 2 is a schematic diagram of the layer stack structure of a printed circuit board according to a preferred embodiment of the present invention.

[0040] Figure 3 is a schematic diagram of a top view perspective of a first signal layer of the printed circuit board according to the above preferred embodiment of the present invention.

[0041] Figure 4 is a schematic diagram of a top view perspective of a first ground layer of the printed circuit board according to the above preferred embodiment of the present invention.

[0042] Figure 5 is a schematic diagram of a top view perspective of a second signal layer of the printed circuit board according to the above preferred embodiment of the present invention.

[0043] Figure 6 It is a schematic top - view of a power supply layer of the printed circuit board according to the above - mentioned preferred embodiment of the present invention.

[0044] Figure 7 It is a schematic top - view of a second ground layer and a third signal layer of the printed circuit board according to the above - mentioned preferred embodiment of the present invention.

[0045] Figure 8 It is a schematic top - view of a fourth signal layer of the printed circuit board according to the above - mentioned preferred embodiment of the present invention.

[0046] Figure 9 It is a schematic diagram of the signal transmission process of the printed circuit board according to the above - mentioned preferred embodiment of the present invention. Detailed implementation manners

[0047] Before detailing any embodiment of the present invention, it should be understood that in its application, the present invention is not limited to the construction and arrangement details of the components described in the following description or illustrated in the following drawings. The present invention is capable of other embodiments and can be practiced or carried out in various ways. Additionally, it should be understood that the wording and terms used herein are for the purpose of description and should not be regarded as restrictive. As used herein, "including" or "having" and their variants are intended to cover the listed items and their equivalents as well as additional items. Unless otherwise specified or limited, the terms "mounted", "connected", "supported", and "coupled" and their variants are used broadly and cover direct and indirect mounting, connection, support, and coupling. Further, "connected" and "coupled" are not limited to physical or mechanical connection or coupling.

[0048] And, on the one hand, in the disclosure of the present invention, the orientation or positional relationship indicated by terms such as "longitudinal", "lateral", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, the above - mentioned terms should not be construed as limiting the present invention; on the other hand, the term "a" should be understood as "at least one" or "one or more". That is, in one embodiment, the number of an element can be one, while in other embodiments, the number of the element can be multiple. The term "a" should not be construed as limiting the quantity.

[0049] Appendix Figure 1An electronic device according to a preferred embodiment of the present invention is shown, wherein the electronic device includes a printed circuit board 10, a processor 20, and a memory 30. The processor 20 and the memory 30 are respectively mounted on the printed circuit board 10. The printed circuit board 10 provides a circuit for connecting the processor 20 and the memory 30, so that the processor 20 can execute instructions stored in the memory 30.

[0050] Appendix Figures 2 to 9 The specific structure of the printed circuit board 10 is shown, wherein the printed circuit board 10 is a multi-layer structure. Specifically, the printed circuit board 10 includes a first signal layer 11, a first ground layer 12, a second signal layer 13, a power layer 14, a second ground layer 15, a third signal layer 16, and a fourth signal layer 17.

[0051] The first signal layer 11 is located on the top layer. The first ground layer 12 is located below the first signal layer 11, wherein the first ground layer 12 is the reference layer of the first signal layer 11, and the first signal layer 11 has a complete projection on the first ground layer 12. The second signal layer 13 is located below the first ground layer 12, wherein the first ground layer 12 is the reference layer of the second signal layer 13, and the second signal layer 13 has a complete projection on the first ground layer 12. The power layer 14 is located below the second signal layer 13. The second ground layer 15 and the third signal layer 16 are on the same layer. The second ground layer 15 and the third signal layer 16 are located below the power layer 14, wherein the power layer 14 is the reference layer of the third signal layer 16, and the third signal layer 16 has a complete projection on the power layer 14. The fourth signal layer 17 is located below the second ground layer 15 and the third signal layer 16, wherein the power layer 14 is the reference layer of the fourth signal layer 17, and the fourth signal layer 17 has a complete projection on the power layer 14.

[0052] In the printed circuit board 10 of the present invention, by allowing the first signal layer 11 and the second signal layer 13 to have complete projections on the first ground layer 12 on opposite sides of the first ground layer 12 respectively, and the third signal layer 16 and the fourth signal layer 17 to have complete projections on the same side of the power layer 14 on the power layer 14, not only can the impedances of the first signal layer 11, the second signal layer 13, the third signal layer 16, and the fourth signal layer 17 be well controlled, but also the first ground layer 12 and the power layer 14 are complete, providing better return paths for the first signal layer 11, the second signal layer 13, the third signal layer 16, and the fourth signal layer 17.

[0053] It can be understood that in the printed circuit board 10 of the present invention, the first ground layer 12 is complete because both the first signal layer 11 and the second signal layer 13 have complete projections on the first ground layer 12. That is, when the first signal layer 11 is regarded as the top layer along the thickness direction of the printed circuit board 10, the first signal layer 11 is entirely located above the first ground layer 12, and the second signal layer 13 is entirely located below the first ground layer 12. Correspondingly, the power supply layer 14 is complete because both the third signal layer 16 and the fourth signal layer 17 have complete projections on the power supply layer 14. That is, when the first signal layer 11 is regarded as the top layer along the thickness direction of the printed circuit board 10, both the third signal layer 16 and the fourth signal layer 17 are located directly below the power supply layer 14.

[0054] In addition, since the first ground layer 12 and the power supply layer 14 are complete, the printed circuit board 10 can ensure that there is no problem of impedance mutation when signals are transmitted in the first signal layer 11, the second signal layer 13, the third signal layer 16, and the fourth signal layer 17, so that signal reflection and distortion will not be caused, thereby avoiding error codes and accidental touches. That is to say, the printed circuit board 10 can ensure that the characteristic impedance of the signals transmitted in the first signal layer 11, the second signal layer 13, the third signal layer 16, and the fourth signal layer 17 is constant, thus ensuring signal quality. It can be understood that the characteristic impedance of a signal can be measured by the instantaneous impedance of the signal. By making the first ground layer 12 and the power supply layer 14 complete, it can be ensured that the impedance at each moment during the signal propagation process is equal, so that the characteristic impedance of the signal is constant.

[0055] Refer to the appendix Figure 2, the printed circuit board 10 includes a first dielectric layer 18a, a first substrate 18b, a second dielectric layer 18c, a second substrate 18d, and a third dielectric layer 18e. The first dielectric layer 18a is located between the first signal layer 11 and the first ground layer 12, isolating the first signal layer 11 and the first ground layer 12 by the first dielectric layer 18a and ensuring that the first ground layer 12 is located below the first signal layer 11. The first substrate 18b is located between the first ground layer 12 and the second signal layer 13, isolating the first ground layer 12 and the second signal layer 13 by the first substrate 18b and ensuring that the second signal layer 13 is located below the first ground layer 12. The second dielectric layer 18c is located between the second signal layer 13 and the power supply layer 14, isolating the second signal layer 13 and the power supply layer 14 by the second dielectric layer 18c and ensuring that the power supply layer 14 is located below the second signal layer 13. The second substrate 18d is located between the power supply layer 14 and the second ground layer 15 and between the power supply layer 14 and the third signal layer 16, isolating the power supply layer 14 and the second ground layer 15 and isolating the power supply layer 14 and the third signal layer 16 by the second substrate 18d and ensuring that the second ground layer 15 and the third signal layer 16 are located below the power supply layer 14. The third dielectric layer 18e is located between the second ground layer 15 and the fourth signal layer 17 and between the third signal layer 16 and the fourth signal layer 17, isolating the second ground layer 15 and the fourth signal layer 17 and isolating the third signal layer 16 and the fourth signal layer 17 by the third dielectric layer 18e and ensuring that the fourth signal layer 17 is located below the second ground layer 15 and the third signal layer 16.

[0056] It is worth mentioning that the first dielectric layer 18a, the first substrate 18b, the second dielectric layer 18c, the second substrate 18d, and the third dielectric layer 18e can be, but are not limited to, polyimide (PI), polyester, or polyethylene naphthalate (PEN). This not only gives the first dielectric layer 18a, the first substrate 18b, the second dielectric layer 18c, the second substrate 18d, and the third dielectric layer 18e a certain hardness and thickness, but also makes them insulating. That is to say, in the printed circuit board 10 of the present invention, the materials of the dielectric layer and the substrate can be the same or different, and are selected according to needs.

[0057] In a specific example of the printed circuit board 10 of the present invention, the first signal layer 11 may be a graphic circuit obtained by patterning a copper foil attached to the upper surface of the first dielectric layer 18a. This graphic circuit is a microstrip line of a transmission line for transmitting signals. The first ground layer 12 may be formed by a copper foil attached to the lower surface of the first dielectric layer 18a. The second signal layer 13 may be a graphic circuit obtained by patterning a copper foil attached to the upper surface of the second dielectric layer 18c. This graphic circuit is a stripline of a transmission line, which is connected to the microstrip line for transmitting signals. The power supply layer 14 may be formed by a copper foil attached to the lower surface of the second dielectric layer 18c. The second ground layer 15 may be formed by a copper foil attached to the upper surface of the third dielectric layer 18e. The third signal layer 16 may be a graphic circuit obtained by patterning a copper foil attached to the upper surface of the third dielectric layer 18e. This graphic circuit is a stripline of a transmission line, which is connected to the microstrip line for transmitting signals. The fourth signal layer 17 may be a graphic circuit obtained by patterning a copper foil attached to the lower surface of the third dielectric layer 18e. This graphic circuit is a microstrip line of a transmission line, which is connected to the stripline or the microstrip line located on the top layer for transmitting signals.

[0058] By means of metallized vias, the microstrip line of the first signal layer 11 and the stripline of the second signal layer 13 can be conducted to form a transmission line. The microstrip line of the fourth signal layer 17 and the stripline of the second signal layer 13 can be conducted to form a transmission line. In this way, the data signal routing path between the processor 20 and the memory 30 can be first from the first signal layer 11 to the second signal layer 13, and then from the second signal layer 13 to the first signal layer 11. The address signal routing path between the processor 20 and the memory 30 can be first from the fourth signal layer 17 to the second signal layer 13, and then from the second signal layer 13 to the fourth signal layer 17.

[0059] Refer to the attached Figure 9 , when the data signal routing path between the processor 20 and the memory 30 is first from the first signal layer 11 to the second signal layer 13 and then from the second signal layer 13 to the first signal layer 11, since the reference layers of the first signal layer 11 and the second signal layer 13 are both the first ground layer 12, and the first ground layer 12 is located between the first signal layer 11 and the second signal layer 13 and the first ground layer 12 is complete, the first ground layer 12 provides a good return path and avoids the problem of impedance mutation when the signal is transmitted between the first signal layer 11 and the second signal layer 13, so as not to cause signal reflection and distortion, thereby avoiding error codes and misoperations.

[0060] Specifically, the instantaneous impedance during the transmission of signals on the first signal layer 11 and the second signal layer 13 can be estimated as , where the parameter is a constant, , the parameter is the dielectric constant of the material of the transmission line, the parameter is the distributed capacitance per unit length of the transmission line. Under the condition that the reference layers are the same, the parameters , , , , satisfy the relationship: , where the parameter is the thickness of the first dielectric layer 18a between the first signal layer 11 and the second signal layer 13, the parameter is the distance between two adjacent transmission lines, the parameter is the thickness of the transmission line, the parameter is the width of the transmission line. Generally, the parameters and are determined. Therefore, the impedance during the transmission of signals on the first signal layer 11 and the second signal layer 13 can be controlled by adjusting the width of the transmission line and the line spacing .

[0061] Refer to the appendix Figure 9 . When the address signal routing path between the processor 20 and the memory 30 is first from the fourth signal layer 17 to the second signal layer 13 and then from the second signal layer 13 to the fourth signal layer 17, since the reference layer of the fourth signal layer 17 is the power supply layer 14, and the fourth signal layer 17 is located below the power supply layer 14 and the power supply layer 14 is complete, the power supply layer 14 can provide a good return path and avoid the problem of impedance mutation during the transmission of signals between the fourth signal layers 17, so as not to cause signal reflection and distortion, thus avoiding error codes and misoperations. It can be understood that since the second ground layer 15 is located between the power supply layer 14 and the fourth signal layer 17, the second ground layer 15 can couple the return path of the transmission line of the fourth signal layer 17 to the power supply layer 14.

[0062] Since the second ground layer 15 is required to couple the return path of the transmission line of the fourth signal layer 17 to the power supply layer 14, the return path is affected not only by the impedance of the power supply layer 14, but also by the impedance between the power supply layer 14 and the second ground layer 15. A voltage drop will occur during the return of the return current, and this voltage drop is ground noise. By minimizing the thickness dimension of the second substrate 18d as much as possible, the voltage drop can be controlled to be relatively small and kept within a reasonable range. In a specific example of the printed circuit board 10 of the present invention, the thickness dimension of the second substrate 18d is set to be greater than or equal to 0.1 mm and less than or equal to 0.5 mm. In other words, let the dielectric thickness dimension parameter between the power supply layer 14 and the second ground layer 15 be , where the parameter satisfies: 0.1 mm ≤ ≤ 0.5 mm. In this way, not only can the hardness and flatness of the printed circuit board 10 be ensured, but also the impedance between the power supply layer 14 and the second ground layer 15 can be significantly reduced, making the influence of the impedance between the power supply layer 14 and the second ground layer 15 on the return path as small as possible, so that the voltage drop during the return of the return current is as small as possible to reduce ground noise.

[0063] Specifically, the instantaneous impedance experienced by the return signal in the return path between the power supply layer 14 and the second ground layer 15 is , where the parameter is the distance between the power supply layer 14 and the second ground layer 15, that is, the thickness of the second substrate 18d, the parameter is the dielectric constant of the second substrate 18d, and the parameter is the radius when the return signal continuously expands outward along the signal vias. In other words, the instantaneous impedance experienced by the return signal in the return path between the power supply layer 14 and the second ground layer 15 is proportional to the distance between the power supply layer 14 and the second ground layer 15 and inversely proportional to the radius when the return signal continuously expands outward along the signal vias. Therefore, by setting the dielectric thickness dimension between the power supply layer 14 and the second ground layer 15 to be between 0.1 mm and 0.5 mm, the instantaneous impedance of the return signal in the return path between the power supply layer 14 and the second ground layer 15 can be effectively reduced, thereby reducing ground noise.

[0064] Refer to Appendix Figure 1 and Figure 3, the first signal layer 11 has a processor mounting area 111 and a memory mounting area 112. The processor mounting area 111 and the memory mounting area 112 are adjacent to each other. A series of processor pads 1111 are provided in the processor mounting area 111, and a series of memory pads 1121 are provided in the memory mounting area 112. Opposite ends of each transmission line formed by the first signal layer 11 and the second signal layer 13 are respectively connected to the processor pads 1111 and the memory pads 1121 at different positions. Opposite ends of each transmission line formed by the second signal layer 13 and the fourth signal layer 17 are respectively connected to the processor pads 1111 and the memory pads 1121 at different positions. Wherein the processor 20 is mounted on the processor mounting area 111 of the first signal layer 11, and the memory 30 is mounted on the memory mounting area 112 of the first signal layer 11. In this way, the printed circuit board 10 provides a circuit for connecting the processor 20 and the memory 30, so that the processor 20 can execute the instructions stored in the memory 30.

[0065] In this specific example of the present invention, the memory mounting area 112 extends from a position adjacent to one side of the processor mounting area 111 in a direction perpendicular to this side of the processor mounting area 111. In this way, while ensuring that the length of the transmission line is as short as possible and all the transmission lines are as equal in length as possible, the transmission lines of the memory mounting area 112 can extend to the processor mounting area 111 from three directions. For example, the memory mounting area 112 has two sets of the memory pads 1121. One set of the memory pads 1121 is located in the upper part of the memory mounting area 112, and the other set of the memory pads 1121 is located in the lower part of the memory mounting area 112. One set of the memory pads 1121 located in the upper part of the memory mounting area 112 includes three rows of the memory pads 1121 spaced apart from each other, and these three rows of the memory pads 1121 are distributed along the length direction of the memory mounting area 112. The transmission lines of the memory mounting area 112 can extend from above, left, and below these three memory pads 1121 to the processor pads 1111 at different positions of the processor mounting area 111. Correspondingly, one set of the memory pads 1121 located in the lower part of the memory mounting area 112 includes three rows of the memory pads 1121 spaced apart from each other, and these three rows of the memory pads 1121 are distributed along the length direction of the memory mounting area 112. The transmission lines of the memory mounting area 112 can extend from above, left, and below these three memory pads 1121 to the processor pads 1111 at different positions of the processor mounting area 111. In this way, on the one hand, the lengths of the transmission lines for connecting each of the processor pads 1111 and each of the memory pads 1121 can be short and as equal in length as possible. On the other hand, it is beneficial for reasonable wiring, so that the width and line pitch can be controlled, thereby controlling the impedance to meet the requirements.

[0066] In some embodiments of the printed circuit board 10 of the present invention, the transmission lines for connecting each of the processor pads 1111 and each of the memory pads 1121 include two types: microstrip lines and stripline. Generally, the signal delays of microstrip lines and stripline with the same length are different. The formula for the delay (unit ) of the microstrip line is , and the formula for the delay (unit ) of the stripline is , where the parameter is the microstrip line delay, the parameter is the stripline delay, is the relative dielectric constant of the substrate. It can be understood that the relative dielectric constant of the substrate Limited by the specific material of the substrate, in a specific example where the relative dielectric constant of the substrate is 4, the calculation formula for the delay of the microstrip line is , and the calculation formula for the delay of the stripline is , that is, 1 (1000 ) in the microstrip line and stripline, the stripline has 34 more delay than the microstrip line. Therefore, in some embodiments of the present invention, in order to meet the signal delay requirements, the equivalent lengths of all transmission lines are designed to be equal.

[0067] The specific steps of designing the equivalent lengths of all transmission lines to be equal include: First, obtain the equivalent lengths of each transmission line respectively; Second, take the transmission line with the longest equivalent length as the reference line, and the remaining transmission lines as the target lines; Then, according to the equivalent length of the transmission line as the target line and the equivalent length of the transmission line as the reference line, obtain the length dimension that the transmission line as the target line needs to be extended; Finally, extend the transmission line as the target line according to the length dimension that needs to be extended, so that the equivalent length of the transmission line as the target line is equal to the equivalent length of the transmission line as the reference line.

[0068] Specifically, in a specific example of the printed circuit board 10 of the present invention, first, after all transmission lines are connected, obtain the microstrip line lengths and stripline lengths of each transmission line respectively. Second, obtain the equivalent total length of the transmission line. If it needs to be equivalent to a microstrip line, the equivalent length of each transmission line is , and if it needs to be equivalent to a stripline, the equivalent length of each transmission line is . Then, obtain the transmission line with the longest equivalent total length and its equivalent length , set this transmission line as the reference line, and set the other transmission lines as the target lines. That is to say, the target length of the transmission line as the target line is , and its error is allowed to be within ±5 . Then, subtract the equivalent length of the transmission line as the target line from the target length respectively to obtain the target delay length of the transmission line as the target line. Finally, wind the equal-length line and extend the other transmission lines as the target lines respectively , so that the equivalent lengths of the respective transmission lines are equal. It should be noted that if it is necessary to be equivalent to a microstrip line, winding is performed on the first signal layer 11 and / or the fourth signal layer 17, that is, when the total length of each transmission line is equivalent to a microstrip line, winding is performed on the outer layer. Correspondingly, if it is necessary to be equivalent to a stripline, winding is performed on the second signal layer 13 and / or the third signal layer 16, that is, when the total length of each transmission line is equivalent to a microstrip line, winding is performed on the inner layer.

[0069] According to another aspect of the present invention, the present invention further provides a wiring method, wherein the wiring method is used to form respective transmission lines on the printed circuit board 10 for connecting the processor 20 and the memory 30 mounted on the printed circuit board 10, and the wiring method includes the following steps:

[0070] (a) allowing the data signal routing path between the processor 20 and the memory 30 to be first from the first signal layer 11 to the second signal layer 13, and then from the second signal layer 13 to the first signal layer 11, wherein a first ground layer 12 serving as a reference layer for the first signal layer 11 and the second signal layer 13 is located between the first signal layer 11 and the second signal layer 13, and the first signal layer 11 and the second signal layer 13 both have a complete projection on the first ground layer 12; and

[0071] (b) allowing the address signal routing path between the processor 20 and the memory 30 to be first from the fourth signal layer 17 to the second signal layer 13, and then from the second signal layer 13 to the fourth signal layer 17, wherein a power supply layer 14 serving as a reference layer for the fourth signal layer 17 is located between the second signal layer 13 and the fourth signal layer 17, and the fourth signal layer 17 has a complete projection on the power supply layer 14.

[0072] Those skilled in the art should understand that the embodiments of the present invention described above and shown in the drawings are only examples and do not limit the present invention. The object of the present invention has been fully and effectively achieved. The functions and structural principles of the present invention have been shown and described in the embodiments, and without departing from the above principles, the embodiments of the present invention can have any deformation or modification.

Claims

1. A wiring method between a processor and a memory, characterized in that: The printed circuit board comprises a first signal layer located at the top layer, a first ground layer located below the first signal layer, a second signal layer located below the first ground layer, a power layer located below the second signal layer, a second ground layer located below the power layer, and a third signal layer, wherein the second ground layer and the third signal layer are on the same layer, the power layer is a reference layer for the third signal layer, the third signal layer has a complete projection on the power layer, and a fourth signal layer is located below the second ground layer and the third signal layer, and the routing method comprises the following steps: (a) The data signal routing path between the processor and the memory is first from the first signal layer to the second signal layer, and then from the second signal layer to the first signal layer, wherein the first ground layer as the reference layer for the first signal layer and the second signal layer is located between the first signal layer and the second signal layer, and the first signal layer and the second signal layer both have complete projections on the first ground layer; and (b) the address signal routing path between the processor and the memory is first from the fourth signal layer to the second signal layer, and then from the second signal layer to the fourth signal layer, wherein the power layer as the reference layer of the fourth signal layer is located between the second signal layer and the fourth signal layer, and the fourth signal layer has a complete projection on the power layer; In the above method, the equivalent lengths of the transmission lines connecting the processor pad and the memory pad of the first signal layer are equal, and the step of equalizing the equivalent lengths of the transmission lines further includes the following steps: Obtain the equivalent length of each transmission line respectively; The transmission line with the longest equivalent length is used as the reference line, and the remaining transmission lines are used as target lines; According to the equivalent length of the transmission line as the target line and the equivalent length of the transmission line as the reference line, obtaining the length dimension of the transmission line as the target line that needs to be extended; According to the length dimension that needs to be extended, the transmission line serving as the target line is extended so that the equivalent length of the transmission line serving as the target line is equal to the equivalent length of the transmission line serving as the reference line. 2 . The routing method according to claim 1 , wherein in the step (b), the second ground layer between the fourth signal layer and the power layer couples the return path of the transmission line of the fourth signal layer to the power layer.

3. The wiring method according to claim 2, wherein the dielectric thickness dimension parameter between the power layer and the second ground layer is Meet: 0.1mm≤ ≤0.5mm.

4. The routing method according to claim 1, wherein in the above method, the first signal layer has a processor mounting area and a memory mounting area, and the memory mounting area starts from a position adjacent to one side of the processor mounting area and extends in a direction perpendicular to the side of the processor mounting area.

5. The routing method according to any one of claims 1 to 4, wherein the equivalent length of the transmission line is the length of the microstrip line, and in the step of extending the equivalent length of each of the target lines, winding is performed on the outer layer according to the delay length to extend the actual length of each of the target lines.

6. The routing method according to any one of claims 1 to 4, wherein the equivalent length of the transmission line is the stripline length, and in the step of extending the equivalent length of each of the target lines, winding is performed on the inner layer according to the delay length to extend the actual length of each of the target lines.

7. A printed circuit board, characterized in that include: The first signal layer at the top layer; a first ground layer located below the first signal layer, the first ground layer being a reference layer for the first signal layer, and the first signal layer having a complete projection on the first ground layer; a second signal layer located below the first ground layer, the first ground layer being a reference layer for the second signal layer, and the second signal layer having a complete projection on the first ground layer; a power layer located below the second signal layer; A second ground layer and a third signal layer are located below the power layer, the second ground layer and the third signal layer are on the same layer, the power layer is a reference layer for the third signal layer, and the third signal layer has a complete projection on the power layer; as well as a fourth signal layer located below the second ground layer and the third signal layer, the power layer being a reference layer for the fourth signal layer, and the fourth signal layer having a complete projection on the power layer; The first signal layer has a processor mounting area and a memory mounting area adjacent to each other, and the memory mounting area extends from a position adjacent to one side of the processor mounting area to a direction perpendicular to the side of the processor mounting area; The equivalent lengths of all transmission lines used to connect the processor pads and the memory pads of the first signal layer are equal, and the step of setting all transmission lines used to connect the processor pads and the memory pads of the first signal layer to have the same equivalent lengths comprises: Obtain the equivalent length of each transmission line respectively; The transmission line with the longest equivalent length is used as the reference line, and the remaining transmission lines are used as target lines; According to the equivalent length of the transmission line as the target line and the equivalent length of the transmission line as the reference line, obtaining the length dimension of the transmission line as the target line that needs to be extended; According to the length required to be extended, the transmission line serving as the target line is extended so that the equivalent length of the transmission line serving as the target line is equal to the equivalent length of the transmission line serving as the reference line; The data signal routing path between the processor and the memory is first from the first signal layer to the second signal layer, and then from the second signal layer to the first signal layer. The address signal routing path between the processor and the memory is first from the fourth signal layer to the second signal layer, and then from the second signal layer to the fourth signal layer.

8. The printed circuit board according to claim 7, wherein the dielectric thickness dimension parameter between the power layer and the second ground layer is Meet: 0.1mm≤ ≤0.5mm.

9. An electronic device, characterized in that include: A printed circuit board as claimed in claim 7 or 8, and a processor and a memory mounted on the printed circuit board.

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