Regulator and power management integrated circuit including same

Abstract

A regulator includes: a reference voltage generation circuit generating a second reference voltage different from a first reference voltage according to a dynamic control signal; an error amplifier configured to generate an error voltage based on the second reference voltage and a regulated voltage at an output node; a power transistor including a gate terminal connected to the error amplifier and receiving an input voltage to output the regulated voltage to the output node based on the error voltage, a dynamic voltage scaling (DVS) circuit connected to the reference voltage generation circuit and the output node, the DVS circuit is used for receiving a regulation voltage from a processor and reducing the regulation voltage to the second reference voltage, and the control circuit is used for receiving a power-off signal from the processor and turning off the power transistor when the regulation voltage is reduced to the second reference voltage through the DVS circuit.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0072398 filed in the Korean Intellectual Property Office on June 5, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Various example embodiments of the inventive concepts described herein relate to a regulator and a power management integrated circuit including the regulator. Background Art

[0004] A power management integrated circuit (PMIC) manages the levels of various powers or provides power to a system, device, or an element included in the device. As an example, the PMIC turns off all supplied power or turns on or off some power according to the operation mode of the power target. In this case, the discharge time is different for each power rail to which power is supplied. Summary of the invention

[0005] Various example embodiments of the inventive concepts provide a regulator capable of preventing or reducing a voltage inversion phenomenon even if a discharge time is different for each power rail, and a power management integrated circuit including the same.

[0006] According to an embodiment, a regulator includes: a reference voltage generating circuit configured to generate a second reference voltage that varies from a first reference voltage according to a dynamic control signal; an error amplifier configured to generate an error voltage based on the second reference voltage and a regulated voltage at an output node; a power transistor including a gate terminal connected to the error amplifier and configured to receive an input voltage to output a regulated voltage to an output node based on the error voltage, a dynamic voltage scaling (DVS) circuit connected to the reference voltage generating circuit and the output node and configured to reduce the regulated voltage to a second reference voltage, and a control circuit configured to receive a power-off signal from a processor and further configured to turn off the power transistor when the regulated voltage is reduced to the second reference voltage through the DVS circuit.

[0007] According to an embodiment, a power management integrated circuit includes one or more regulators configured to regulate an input voltage and output a regulated voltage and a control circuit configured to control the one or more regulators. The control circuit is configured to operate a dynamic voltage scaling (DVS) loop, the DVS loop drops the regulated voltage to a reference voltage that varies according to a dynamic control signal when a power-off signal is provided from a processor, and turns off one or more power transistors included in the one or more regulators when the regulated voltage drops to the reference voltage.

[0008] According to an embodiment, a method of operating a power management integrated circuit includes: receiving a power-off signal from a processor, reducing a regulation voltage to a reference voltage using a dynamic voltage scaling (DVS) loop included in the power management integrated circuit, and turning off a power transistor included in the power management integrated circuit based on the regulation voltage reduced to the reference voltage.

[0009] According to the above, the power management integrated circuit includes a regulator that prevents or reduces the voltage reversal phenomenon even if the discharge time of each power rail is different. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other objects and features of the present inventive concept will become apparent by describing in detail various exemplary embodiments of the present inventive concept with reference to the accompanying drawings.

[0011] Figure 1 is a block diagram illustrating a system on chip according to example embodiments.

[0012] Figure 2 is a circuit diagram illustrating a regulator according to example embodiments.

[0013] Figure 3 is a circuit diagram illustrating a regulator according to example embodiments.

[0014] Figure 4 is a circuit diagram illustrating a DVS circuit according to an example embodiment.

[0015] Figure 5 is a circuit diagram illustrating a control circuit according to an example embodiment.

[0016] Figure 6 is a block diagram illustrating a PMIC according to example embodiments.

[0017] Figure 7 and Figure 8 is a waveform diagram illustrating a voltage waveform of a regulator according to some example embodiments.

[0018] Fig. 9 and Fig.10 is a waveform diagram illustrating a voltage waveform of a regulator according to some example embodiments.

[0019] Fig.11 is a flow chart illustrating the operation of a power management integrated circuit according to an example embodiment.

[0020] Fig.12 is a block diagram illustrating an electronic device according to an example embodiment.

[0021] Fig.13 is a block diagram illustrating an electronic device according to an example embodiment.

[0022] Fig.14 and Fig.15 It shows that according to Fig.13 A waveform diagram of the regulated operating waveform of an electronic device. DETAILED DESCRIPTION

[0023] Below, various exemplary embodiments of the inventive concept will be described in detail and clearly so that those having ordinary skill in the art can implement the inventive concept.

[0024] When the term "about" or "substantially" is used in conjunction with a numerical value in this specification, it is intended that the associated numerical value includes a manufacturing or operating tolerance (e.g., ±10%) around the numerical value. In addition, regardless of whether a numerical value is modified as "about" or "substantially", it should be understood that these values ​​should be interpreted as including a manufacturing or operating tolerance (e.g., ±10%) around the numerical value.

[0025] Figure 1 is a block diagram illustrating a system on chip (SoC) 1 according to an example embodiment.

[0026] refer to Figure 1 , the system on chip 1 may include a power management integrated circuit (PMIC) 10 a and a processor 20 .

[0027] The PMIC 10a may be configured to manage power consumption of the processor 20. The PMIC 10a may be connected to the processor 20 via one or more power rails PL1 and PL2. The PMIC 10a may provide various functions, such as voltage and current regulation, battery charging, and power sequencing, for the processor 20. As an example, the PMIC 10a may receive an input voltage VIN, may convert the received input voltage VIN into output voltages VOUT1 and VOUT2 of various levels required or used by the processor 20, and may provide the output voltages VOUT1 and VOUT2 to the processor 20.

[0028] According to example embodiments, the PMIC 10a may include one or more converters 100a and 100b, a bandgap reference (BGR) generator 200, and one or more regulators 300a and 300b.

[0029] One or more converters 100a and 100b may convert the input voltage VIN into a voltage required or used by the PMIC 10a, and may output the converted voltage. As an example, each of the converters 100a and 100b may output a voltage required or used by one or more regulators 300a and 300b based on the input voltage VIN, or may directly output a voltage required or used by the processor 20. As an example, one or more converters 100a and 100b may be a boost converter, a buck converter, or a buck-boost converter.

[0030] BGR generator 200 may generate a reference voltage VREF for voltage regulation of one or more regulators 300a and 300b and may provide the reference voltage VREF to one or more regulators 300a and 300b. Reference voltage VREF may be a BGR voltage and may be stable and independent of ambient conditions such as temperature.

[0031] One or more regulators 300a and 300b may be connected to output terminals of one or more converters 100a and 100b. One or more regulators 300a and 300b may convert voltages output from one or more converters 100a and 100b based on a reference voltage VREF, and may provide output voltages VOUT1 and VOUT2 of various levels to the processor 20. As an example, one or more regulators 300a and 300b may be low dropout (LDO) regulators.

[0032] One or more regulators 300a and 300b may receive a power-off signal Poff and a dynamic control signal DCON from the processor 20. When the processor 20 operates in a power-off sequence, the power-off signal Poff may be provided from the processor 20. When the processor 20 dynamically controls voltage using the PMIC 10a, the dynamic control signal DCON may be provided from the processor 20. The reference voltage VREF for regulation may be controlled based on the dynamic control signal DCON.

[0033] According to example embodiments, one or more regulators 300 a and 300 b may sequentially perform a driving operation of the DVS loops 301 a and 301 b and a turn-off operation of the power transistors 302 a and 302 b in response to a power-off signal Poff applied thereto.

[0034] One or more regulators 300a and 300b may control output voltages VOUT1 and VOUT2 through DVS loops 301a and 301b in response to a power-off signal Poff applied thereto. DVS loops 301a and 301b may be defined as circuit loops for reducing output voltages VOUT1 and VOUT2 from one or more regulators 300a and 300b to a reference voltage VREF adjusted according to a dynamic control signal DCON. According to example embodiments, when a power-off signal Poff is received, the reference voltage VREF may be set or changed to a specific threshold voltage. Therefore, in some example embodiments, one or more regulators 300a and 300b may drive DVS loops 301a and 301b to a threshold voltage after receiving the power-off signal Poff. The threshold voltage may be set by taking into account a power-off sequence.

[0035] In this case, according to some example embodiments, the driving operation of the DVS loops 301a and 301b may be performed according to a certain slew rate. As an example, the slew rate may be set so that the voltage drop caused by the DVS loops 301a and 301b may be performed faster than the discharge caused by the turn-off of the power transistors 302a and 302b.

[0036] In some example embodiments, when the level of the output voltages VOUT1 and VOUT2 drops to a threshold voltage through the DVS loops 301a and 301b, one or more regulators 300a and 300b may perform a shutdown operation of the power transistors 302a and 302b. One or more regulators 300a and 300b may reduce the level of the output voltages VOUT1 and VOUT2 to a specific voltage level, for example, the above-mentioned threshold voltage, through the DVS loops 301a and 301b, and then may turn off the power transistors. In this case, according to some example embodiments, the power transistors may be provided separately from the DVS loops 301a and 301b in the one or more regulators 300a and 300b for regulation. Due to the shutdown of the power transistors 302a and 302b, the output voltages VOUT1 and VOUT2 may drop from the threshold voltage to a shutdown voltage, for example, 0 volts.

[0037] In some example embodiments, during power-off regulation, for each of the regulators 300a and 300b, in the case where the discharge time of the output voltages VOUT1 and VOUT2 at a specific level is different, a voltage reversal phenomenon may occur between the power rails during power-off. According to the inventive concept, since one or more regulators 300a and 300b first reduce the level of the output voltages VOUT1 and VOUT2 to a threshold voltage through the DVS loops 301a and 301b, and then the remaining regulation can be performed by the turn-off operation of the power transistors 302a and 302b, the voltage reversal phenomenon can be prevented or reduced.

[0038] The processor 20 may control the overall operation of the system on chip 1. As an example, the processor 20 may be implemented by a general-purpose processor, a dedicated processor, or an application processor (AP). As an example, the processor 20 may be implemented by an operation processor (e.g., a central processing unit (CPU), a graphics processing unit (GPU), etc.) including a dedicated logic circuit (e.g., a field programmable gate array (FPGA), an application-specific integrated circuit (ASICs), etc.), however, it should not be limited to or thereby.

[0039] The processor 20 may execute a program stored on the system on chip 1. According to example embodiments, the processor 20 may process data stored on the system on chip 1 and data provided from the outside.

[0040] As an example, the processor 20 may send a power-off signal Poff and a dynamic control signal DCON to the PMIC 10a when operating in a power-off sequence. The processor 20 may receive a voltage required or used by the power-off sequence through the PMIC 10a.

[0041] According to some example embodiments, the regulator included in the system on chip 1 may first reduce the voltage to a threshold voltage through the DVS loops 301a and 301b, and then may perform a turn-off operation of the power transistors 302a and 302b during the power-off sequence. Therefore, in some example embodiments, the regulator may reduce the time required or used for the power-off sequence, and thus, may accurately or substantially match the power-off sequence between the components on which the power-off sequence is performed. In addition, a voltage reversal phenomenon may be prevented (or reduced or minimized) from occurring between power rails during the power-off sequence.

[0042] Figure 2 is a circuit diagram illustrating a regulator 300 c according to an example embodiment.

[0043] refer to Figure 2 The regulator 300 c may include a reference voltage generating circuit 310 , an error amplifier 320 , a power transistor P_TR, a DVS circuit 330 and a control circuit 340 .

[0044] The reference voltage generating circuit 310 can generate a second reference voltage VREF that varies from the first reference voltage according to the dynamic control signal DCON. As an example, the first reference voltage can be Figure 1 The BGR generator generates the BGR voltage BGR_REF. The dynamic control signal DCON can be Figure 1 The reference voltage generating circuit 310 may be provided by a processor and may be a control signal that dynamically changes the level of the first reference voltage and generates the second reference voltage VREF. As an example, the reference voltage generating circuit 310 may include a digital-to-analog converter (DAC), and when the first reference voltage and the dynamic control signal DCON are digital signals, the digital-to-analog converter (DAC) converts the first reference voltage and the dynamic control signal DCON into an analog level corresponding to the second reference voltage VREF.

[0045] The error amplifier 320 may include input terminals connected to the output terminal of the reference voltage generating circuit 310 and the output node no, respectively, and thus may receive the second reference voltage VREF and the regulation voltage VLDO outputted from the output node no. The output terminal of the error amplifier 320 may be connected to the gate terminal of the power transistor P_TR, and may output the error voltage Verr to the gate terminal of the power transistor P_TR based on comparing the second reference voltage VREF with the regulation voltage VLDO. The error amplifier 320 may be driven in response to the battery voltage VBAT.

[0046] The power transistor P_TR may include a gate terminal connected to the error amplifier 320, one terminal to which the input voltage VIN is applied, and another terminal connected to the output node no. The power transistor P_TR may be turned on or off in response to a gate voltage controlled by the error voltage Verr. For example, when the power transistor P_TR is turned on, the input voltage VIN may be regulated, and the regulated voltage VLDO may be output to the output node no. According to an example embodiment, when the regulator 300c operates in a power-off sequence, the power transistor P_TR may be turned off after the DVS loop operates based on the DVS circuit 330.

[0047] According to various example embodiments, the power transistor P_TR may be implemented by an NMOS as an N-type MOSFET (Metal Oxide Semiconductor Field Effect Transistor) or a PMOS as a P-type MOSFET. As an example, when the power transistor P_TR is an NMOS, an input voltage VIN may be applied to a drain terminal of the power transistor P_TR, and a source terminal of the power transistor P_TR may be connected to an output node no.

[0048] The DVS circuit 330 may be connected to the reference voltage generating circuit 310 and the output node no. The DVS circuit 330 may be configured to receive the second reference voltage VREF and the regulation voltage VLDO and reduce the regulation voltage VLDO to the second reference voltage VREF. For example, the DVS circuit 330 may operate to allow the regulation voltage VLDO to correspond to the level of the second reference voltage VREF controlled according to the dynamic control signal DCON.

[0049] According to example embodiments, when the power-off signal Poff is received, for example, when a power-off sequence starts, the second reference voltage VREF may be set to a specific threshold voltage. Therefore, in some example embodiments, the DVS circuit 330 may drop the regulation voltage VLDO to the threshold voltage during the power-off sequence.

[0050] The DVS circuit 330 may operate from the start time point of the power-off period started in response to the power-off signal Poff to a specific time point. In some example embodiments, the specific time point may be defined as a point at which the regulation voltage VLDO becomes the second reference voltage VREF. Since the second reference voltage VREF is set to a threshold voltage when the power-off signal Poff is received, the DVS circuit 330 may end its operation when the regulation voltage VLDO becomes the threshold voltage.

[0051] The DVS circuit 330 may operate at a higher discharge rate than the discharge rate after a specific time point in the power-off period. As an example, the DVS circuit 330 may have a specific slew rate, and the slew rate may be set so that the voltage drop caused by the DVS circuit 330 is performed faster than the discharge caused by the turn-off of the power transistor.

[0052] The control circuit 340 may control the overall operation of the regulator 300c. When a power-off signal Poff is received from the processor, the control circuit 340 may operate to turn off the power transistor P_TR based on dropping the regulated voltage VLDO to the second reference voltage VREF through the DVS circuit 330. For example, when the power-off signal Poff is received, the second reference voltage VREF may be set to a threshold voltage. The control circuit 340 may detect whether the regulated voltage VLDO drops to the threshold voltage while monitoring the regulated voltage VLDO.

[0053] The control circuit 340 may provide a shutdown signal TR_CON to the gate terminal of the power transistor P_TR based on a threshold voltage sensed from the voltage from the regulator 300c. The power transistor P_TR may be turned off in response to the shutdown signal TR_CON. In some example embodiments, when the power transistor P_TR is turned off, the DVS loop (which is defined as a loop that reduces the regulation voltage VLDO according to the DVS circuit 330 and the output node no) may also no longer operate. Therefore, in some example embodiments, the regulator 300c may continue the remaining discharge operation according to the turned-off power transistor P_TR until the power supply is turned off.

[0054] According to the above-described example embodiments, the regulator 300c can quickly reduce the regulation voltage VLDO to a specific voltage, such as a threshold voltage, by the DVS circuit 330 during the power-off sequence. For example, the time required or used for the power-off sequence can be reduced, and the power-off sequence between the components on which the power-off sequence is performed can be accurately or substantially matched. In addition, in the regulator 300c provided with the DVS circuit 330, the power-off sequence can be controlled only by the operation of the control circuit 340 (operating the DVS circuit 330 during the power-off sequence and turning off the power transistor P_TR when the threshold voltage is detected) without adding complex hardware elements.

[0055] Figure 3 is a circuit diagram showing a regulator 300d according to an example embodiment. Figure 3 In the same reference numerals, Figure 2 The same elements are used herein, and thus detailed description of the same elements will be omitted.

[0056] refer to Figure 3The regulator 300 d may include a reference voltage generating circuit 310 , an error amplifier 320 , a power transistor P_TR, a DVS circuit 330 , and a control circuit 340 , and may further include a buffer 335 and a discharge circuit 345 .

[0057] The buffer 335 may be connected between the output terminal of the error amplifier 320 and the gate terminal of the power transistor P_TR. The buffer 335 may buffer the error voltage Verr output based on the reference voltage generating circuit 310 and the error amplifier 320, and may output a buffer voltage Vbuf. The buffer 335 may have a high input impedance and a low output impedance, and therefore, the buffer 335 may have a load transient characteristic. As an example, the regulator 300d may include one or more buffers 335. The buffer voltage Vbuf may be applied to the gate terminal of the power transistor P_TR, and therefore, the power transistor P_TR may perform regulation in response to the buffer voltage Vbuf.

[0058] The discharge circuit 345 may be connected to the output node no and may be configured to quickly discharge the regulated voltage VLDO. According to an example embodiment, the discharge circuit 345 may include a resistor R and a transistor D_TR. The resistor R may be connected between the output node no and one terminal of the transistor. The gate voltage VG may be applied to the gate terminal of the transistor D_TR, and the other terminal of the transistor D_TR may be grounded. The transistor D_TR may discharge the regulated voltage VLDO of the output node no in response to the gate voltage VG. The discharge circuit 345 may operate continuously not only during the non-power-off period but also during the power-off period. For example, the discharge circuit 345 may operate even after the power transistor P_TR is turned off.

[0059] According to example embodiments, the regulator 300d may first drop the regulation voltage VLDO to a threshold voltage through the power transistor P_TR, the discharge circuit 345, and the DVS circuit 330 during a power-off sequence. In some example embodiments, in the event that the threshold voltage is sensed from the regulation voltage VLDO, the control circuit 340 may turn off the power transistor P_TR. Therefore, the DVS circuit 330 may be deactivated, and only the discharge circuit 345 operates. The regulator 300d may drop the regulation voltage VLDO to a turn-off voltage using the discharge circuit 345.

[0060] According to the above-described example embodiment, since the regulator 300d can more quickly reduce the regulation voltage VLDO to the threshold voltage using the DVS circuit 330 having a specific slew rate and can then turn off the power transistor P_TR, the remaining discharge operation can be performed using the discharge circuit 345. The discharge circuit 345 can participate in both the drop of the threshold voltage and the subsequent drop of the threshold voltage, and therefore, the power-off sequence can be performed faster.

[0061] Figure 4 is a circuit diagram illustrating a DVS circuit 330 according to an example embodiment.

[0062] refer to Figure 4 , the DVS circuit 330 may include a DVS amplifier 331 and a DVS transistor DVS_TR.

[0063] The DVS amplifier 331 may include two Figure 2 and Figure 3 The reference voltage generating circuit 310 and the input terminal of the output node no of the DVS amplifier 331 are connected to each other, and the second reference voltage VREF and the regulation voltage VLDO may be respectively applied to the input terminal of the DVS amplifier 331. The DVS amplifier 331 may output a comparison voltage Vcomp based on a comparison of the second reference voltage VREF and the regulation voltage VLDO. The output terminal of the DVS amplifier 331 may be connected to the gate terminal of the DVS transistor DVS_TR, and the DVS amplifier 331 may output the comparison voltage Vcomp to the gate terminal.

[0064] One terminal of the DVS transistor DVS_TR may be connected to the output node no, the regulation voltage VLDO may be applied to one terminal of the DVS transistor DVS_TR, and the other terminal of the DVS transistor DVS_TR may be grounded. A gate terminal of the DVS transistor DVS_TR may be connected to the DVS amplifier 331, and the DVS transistor DVS_TR may regulate the regulation voltage VLDO according to the comparison voltage Vcomp applied to the gate terminal.

[0065] The DVS amplifier 331 may compare the dynamically controlled second reference voltage VREF with the regulation voltage VLDO, and thus, the DVS amplifier 331 may drop the regulation voltage VLDO to the second reference voltage VREF. The DVS amplifier 331 may drop the regulation voltage VLDO to a threshold voltage during a power-off sequence according to the above-described embodiment, and then, when the power transistor P_TR is turned off, the DVS amplifier 331 may be disabled.

[0066] Figure 4 The DVS circuit 330 shown in FIG. 3 is merely an example, and the DVS circuit 330 may be configured in various ways to perform a regulation operation depending on a dynamically controlled reference voltage according to the example embodiments described above.

[0067] Figure 5 is a circuit diagram illustrating a control circuit 340 according to an example embodiment.

[0068] Reference Figure 5, the control circuit 340 may include a DML (DVS minimum level) register 341 , a DML sensor 342 , and a logic element 343 .

[0069] The DML register 341 may store a threshold voltage DML. As an example, the threshold voltage DML may be obtained from Figure 1 The processor is programmed on the DML register 341. The threshold voltage DML can be set in various ways according to the power-off sequence and can be stored.

[0070] The DML sensor 342 may sense the threshold voltage DML stored in the DML register 341 from the regulation voltage VLDO. For example, the DML sensor 342 may detect whether the regulation voltage VLDO drops to the threshold voltage DML while continuously monitoring the regulation voltage VLDO during the power-off sequence. In some example embodiments, when the threshold voltage DML is sensed, the DML sensor 342 may send a sensing signal DS to the logic element 343.

[0071] In some example embodiments, when both the power-off signal Poff and the sensing signal DS are identified, the logic element 343 may output the shutdown signal TR_CON. As an example, the logic element 343 may be implemented with an AND gate, however, the inventive concept should not be limited thereto or thereby. In some example embodiments, when the logic element 343 is implemented with an AND gate, when the power-off signal Poff corresponds to logic indicating that the power is turned off and the sensing signal DS corresponds to logic indicating that the threshold voltage DML is sensed, the logic element 343 may output the shutdown signal TR_CON through an AND operation.

[0072] Figure 6 is a block diagram illustrating a PMIC 10 b according to an example embodiment.

[0073] Reference Figure 6 The PMIC 10 b may include one or more converters 100 a and 100 b , one or more regulators 300 a and 300 b , a BGR generator 200 , a control circuit 400 , a DML register 500 , and a DVS register 600 connected to each other via a bus 700 .

[0074] One or more converters 100a and 100b may convert the input voltage VIN into a voltage required or used by the PMIC 10b, and may output the converted voltage. One or more regulators 300a and 300b may convert the voltage output from the one or more converters 100a and 100b based on a reference voltage (e.g., BGR voltage BGR_REF) generated by the BGR generator 200. In this case, the one or more regulators 300a and 300b may adjust the output voltages VOUT1 and VOUT2 according to the above-described example embodiments so that the output voltages VOUT1 and VOUT2 may correspond to a second reference voltage, which is the dynamically controlled BGR voltage BGR_REF.

[0075] The control circuit 400 may control the overall operation of the PMIC 10b. According to an example embodiment, the control circuit 400 may receive a power-off signal Poff, and may control the operation of one or more regulators 300a and 300b in response to the power-off signal Poff. For example, the control circuit 400 may control the one or more regulators 300a and 300b to sequentially perform a driving operation of the DVS loops 301a and 301b and a shut-down operation of the power transistors 302a and 302b in response to the power-off signal Poff applied thereto.

[0076] First, the control circuit 400 may control the output voltages VOUT1 and VOUT2 through the DVS loops 301a and 301b included in one or more regulators 300a and 300b. As an example, the control circuit 400 may drive the DVS loops 301a and 301b until the output voltages VOUT1 and VOUT2 drop to a threshold voltage after receiving the power-off signal Poff.

[0077] The control circuit 400 may read the threshold voltage stored in the DML register 500, may drive the DVS loops 301a and 301b, and may sense the threshold voltage from the output voltages VOUT1 and VOUT2 during the power-off sequence. The control circuit 400 may program the read threshold voltage in the DVS register 600. The DVS register 600 may store the dynamic control signal DCON or a second reference voltage as a reference voltage of the DVS loops 301a and 301b indicated by the dynamic control signal DCON, and the control circuit 400 may set the read threshold voltage to the second reference voltage upon receiving the power-off signal Poff. Therefore, in some example embodiments, the DVS loops 301a and 301b may perform adjustment on the threshold voltage.

[0078] In some example embodiments, when a threshold voltage is sensed from the output voltages VOUT1 and VOUT2, the control circuit 400 may perform a turn-off operation of the power transistors 302a and 302b on the one or more regulators 300a and 300b. For example, the control circuit 400 may turn off the one or more power transistors P_TR included in the one or more regulators 300a and 300b. Due to the turn-off operation of the power transistors 302a and 302b, the output voltages VOUT1 and VOUT2 may drop from the threshold voltage to a turn-off voltage, such as 0 volts.

[0079] Therefore, in some example embodiments, one or more regulators 300a and 300b may perform regulation according to a first discharge rate until the regulation voltage VLDO drops to a reference voltage in response to control of the control circuit 400, and may perform regulation according to a second discharge rate lower than the first discharge rate after the regulation voltage VLDO drops to the reference voltage.

[0080] According to the above-described example embodiments, the PMIC 10b may control one or more regulators 300a and 300b to sequentially reduce the voltage to the threshold voltage through the DVS loops 301a and 301b, and perform the turn-off operation of the power transistors 302a and 302b through the control circuit 400 included in the PMIC 10b during the power-off sequence. Therefore, in some example embodiments, the PMIC 10b may reduce the time required for or used for the power-off sequence, and therefore, may accurately or substantially match the power-off sequence between the components on which the power-off sequence is performed. In addition, the voltage reversal phenomenon between the power rails PL1 and PL2 during the power-off sequence may be prevented (or reduced or minimized).

[0081] Figure 7 and Figure 8 is a waveform diagram illustrating a voltage waveform of a regulator according to some example embodiments.

[0082] Figure 7 1 shows a waveform of a regulated voltage when the regulator immediately turns off the power transistor P_TR during a power-off sequence. As an example, output voltages having different levels may be regulated by a first regulator and a second regulator, and an initial voltage V1 of the first regulator may be greater than an initial voltage V2 of the second regulator. In this case, when a discharge rate of the first regulator relative to the threshold voltage DML is greater than a discharge rate of the second regulator relative to the threshold voltage DML, a voltage reversal may occur at a reversal point RP, such as Figure 7 As shown in FIG. 1 , voltage glitches and leakage current may be generated in the input / output voltage IO due to the voltage inversion.

[0083] A method of delaying the start time point of the power-off sequence of the second regulator may be considered to prevent or reduce voltage reversal, however, the delay method only delays the discharge start time and therefore may not take into account factors such as variations in the external capacitors of the regulator or deviations between on-chip systems.

[0084] Figure 8 330 shows a voltage waveform of the regulated voltage when the regulated voltage drops to the threshold voltage DML through the DVS circuit and then the power transistor P_TR is turned off during the power-off sequence. In this case, when the power-off sequence starts, the power transistor P_TR may be turned on until the regulated voltage drops to the threshold voltage DML. Therefore, in some example embodiments, the DVS circuit 330 may operate, and each of the first regulator and the second regulator may perform regulation at a predetermined conversion rate from the start time point of the power-off sequence until the regulated voltage drops to the threshold voltage DML.

[0085] Therefore, in some example embodiments, even if the discharge rate changes at least after the power transistor P_TR is turned off, the first regulator and the second regulator can perform regulation to the threshold voltage DML at a fast discharge rate through the DVS circuit 330. Preferably, by considering the power-off sequence, the threshold voltage DML can be set to a voltage close to the turn-off voltage, for example, 0 volts. Therefore, in some example embodiments, even if the first regulator and the second regulator have different discharge rates from the threshold voltage DML to the turn-off voltage, the first regulator and the second regulator can perform the power-off sequence without voltage reversal, glitches of the input / output voltage IO, and leakage current.

[0086] Fig. 9 and Fig.10 is a waveform diagram illustrating a voltage waveform of a regulator according to some example embodiments.

[0087] Fig. 9 The waveform of the regulation voltage when the regulator immediately turns off the power transistor P_TR during the power-off sequence is shown. During the power-off sequence, the voltage drop of the input / output voltage VIO of the PMIC may first start at the initial voltage V1. Then, the first logic voltage Vlogic1 for the logic circuit included in the PMIC starts to drop at V2, and the second logic voltage Vlogic2 for the logic circuit included in the PMIC starts to drop at V3. Since the discharge rate of the input / output voltage VIO is the lowest overall, even if the input / output voltage VIO starts to discharge first, the first logic voltage Vlogic1 and the second logic voltage Vlogic2 already indicate the turn-off voltage in the threshold voltage DML. Therefore, in some example embodiments, it can be observed that the voltage glitch Vglitch is detected at the threshold voltage reaching point tRP.

[0088] As described above, a method of delaying the start time point may be performed to prevent or reduce voltage reversal, and as an example, a discharge circuit (eg, Figure 3 The invention also provides the following aspects: enabling / disabling of a discharge circuit 345), controlling discharge by changing a register setting of the discharge circuit, changing a group in which a power-off sequence is performed, and changing a shutdown start time point of the group.

[0089] Fig.10 1 shows a voltage waveform of the regulated voltage when the regulated voltage drops to the threshold voltage DML by the DVS circuit 330 and then turns off the power transistor P_TR during the power-off sequence. When the power-off sequence starts, each of the voltages VIO, Vlogic1, and Vlogic2 may drop to the threshold voltage DML by the DVS circuit 330, and after the voltages VIO, Vlogic1, and Vlogic2 drop, the discharge according to the turn-off operation of the power transistor may continue. Therefore, in some example embodiments, the voltage reversal of each of the voltages VIO, Vlogic1, and Vlogic2 may be prevented or reduced, and the voltage glitch Vglitch may not be sensed.

[0090] Therefore, according to the present invention, the power-off sequence can be stably executed without executing various methods to prevent (or reduce or minimize) Fig. 9 voltage glitches.

[0091] Fig.11 is a flow chart illustrating a method of operating a power management integrated circuit according to an example embodiment.

[0092] refer to Fig.11 , the power management integrated circuit may receive a power-off signal Poff from the processor (S10). The power management integrated circuit may start a power-off sequence in response to the power-off signal Poff.

[0093] The PMIC may reduce the regulation voltage to the reference voltage based on a DVS loop included in the PMIC (S20). For example, the PMIC may first drive the DVS loop instead of turning off the power transistor P_TR immediately after receiving the power-off signal Poff through operation S10.

[0094] According to the operation of the PMIC, the power transistor P_TR included in the PMIC may be turned off based on the voltage drop from the regulation voltage VLDO to the reference voltage (S30). Turning off the power transistor P_TR may also include sensing whether the regulation voltage VLDO corresponds to the reference voltage.

[0095] The method of operating the power management integrated circuit may further include setting the reference voltage to a threshold voltage in response to the received power-off signal Poff.

[0096] The method of operating the power management integrated circuit may further include performing regulation according to a first discharge rate until the regulation voltage VLDO drops to a reference voltage, and performing regulation according to a second discharge rate lower than the first discharge rate after the regulation voltage VLDO drops to the reference voltage.

[0097] Fig.12 is a block diagram illustrating an electronic device 2 according to an exemplary embodiment.

[0098] refer to Fig.12 , the electronic device 2 may be implemented by a handheld device, such as a cellular phone, a smart phone, a tablet personal computer (PC), a personal digital assistant (PDA), an enterprise digital assistant (EDA), a digital still camera, a digital video camera, a portable multimedia player (PMP), a personal navigation device (PND), a portable navigation device (PND), a handheld game console, an e-book, etc., but the example embodiments are not limited thereto.

[0099] The electronic device 2 may include a PMIC 10 c , an application processor (AP) 30 , an input / output interface 40 , a random access memory (RAM) 50 , a communication device 60 , a display device 70 , and a read only memory (ROM) 80 .

[0100] The PMIC 10c may be implemented according to the various exemplary embodiments described above. The PMIC 10c may convert an input voltage VIN provided from a battery (not shown) included in the electronic device 2 into output voltages of various levels and may provide the output voltages to various load devices.

[0101] The PMIC 10c can monitor the workload of each load device and the system performance, and can adjust the power supply voltage and clock frequency based on the monitored results. As an example, when the workload of the load device is light, the PMIC 10c can reduce the power supply voltage and clock frequency, and thus can reduce power consumption. In the case where the workload of the load device increases, the PMIC 10c can increase the power supply voltage and clock frequency to maintain performance.

[0102] The PMIC 10c may include a converter 100, one or more regulators 300a and 300b, and a control circuit 400. The PMIC 10c may convert an input voltage VIN into a lower or higher voltage through the converter 100, and may regulate the converted voltage to a voltage level required or used by a load device through the one or more regulators 300a and 300b. In some example embodiments, when the control circuit 400 receives a power-off signal Poff, the control circuit 400 may allow the one or more regulators 300a and 300b to first reduce the regulation voltage to a threshold voltage through a DVS loop, and then, when the threshold voltage is sensed, the control circuit 400 may turn off the power transistor P_TR in response to a shutdown signal TR_CON to perform a power-off sequence.

[0103] The PMIC 10c can be connected to various load devices through multiple power rails PL1 to PL6 and can provide output voltages converted by one or more regulators 300a and 300b. In this case, a power-off sequence using a DVS loop can prevent or reduce voltage reversal between the power rails PL1 to PL6.

[0104] The AP 30 may control the overall operation of the electronic device 2. As an example, the AP 30 may provide a power-off signal Poff to the PMIC 10c during a power-off sequence.

[0105] According to an exemplary embodiment, the AP 30 may include a core 31, an internal ROM 32, an internal RAM 33, a display controller 34, and an input / output interface 35. The core 31 may process or execute a program and / or data stored in the memory. For example, the core 31 may be implemented as a multi-core processor. A boot code may be stored in the internal ROM 32. The core 31 may temporarily store a program, data, or instruction in the internal RAM 33 according to the boot code stored in the internal ROM 32. The display controller 34 may be configured to control the operation of the display device 70. The input / output interface 35 may provide an interface with respect to an IP (Intellectual Property) connected to the AP 30.

[0106] According to an example embodiment, the AP 30 may be a ModAP in which the function of a modem chip included in the communication device 60 is integrated.

[0107] The input / output interface 40 may provide an interface to transmit and receive data of the electronic device 2 .

[0108] The RAM 50 may temporarily store programs, data, or instructions. As an example, the programs and / or data stored in the memory may be temporarily stored in the RAM 50 according to the control of the CPU or the boot code stored in the ROM 80. The RAM 50 may be implemented by a dynamic RAM (DRAM) or a static RAM (SRAM).

[0109] The communication device 60 may transmit and receive signals between the electronic device 2 and other external devices according to various communication protocols. The communication device 60 may include an antenna, a transceiver and / or a modem (MODEM).

[0110] The display device 70 may display an image signal output from the display controller. As an example, the display device 70 may be implemented as a liquid crystal display (LCD), a light emitting diode (LED) display, an organic LED (OLED) display, an active matrix OLED (AMOLED) display, or a flexible display.

[0111] The ROM 80 may store permanent programs and / or data. The ROM 80 may be implemented by an erasable programmable read-only memory (EPROM) or an electrically erasable programmable read-only memory (EEPROM).

[0112] In addition, the PMIC 10 c may be connected to an operation block, a function block, or an IP block that may be included in the electronic device 2 to provide various voltage levels.

[0113] Fig.13 is a block diagram illustrating an electronic device 3 according to an exemplary embodiment.

[0114] Reference Fig.13 , the electronic device 3 may include a PMIC 10 e , an AP 30 , and a communication device 60 .

[0115] The PMIC 10e may adjust the reference voltage, and may provide a first driving voltage VDDPE required or used by the logic circuit 31 and a second driving voltage VDDCE required or used by the SRAM 32. The PMIC 10e may include the regulator according to the above-described embodiments.

[0116] The AP 30 may include a logic circuit 31 and an SRAM 32. The logic circuit 31 may be configured to allow the AP 30 to process or execute various programs and / or data. The SRAM 32 may be used as a cache memory, a register, or a buffer memory in the electronic device 3. The AP 30 may be connected to the PMIC 10e and may receive a first driving voltage VDDPE and a second driving voltage VDDCE from the PMIC 10e. The logic circuit 31 may be operated based on the first driving voltage VDDPE, and the SRAM 32 may be operated based on the second driving voltage VDDCE.

[0117] The communication device 60 may include a modem 61 and a transceiver 62. The modem 61 may process a baseband signal containing information to be transmitted, or may process a received baseband signal. The transceiver 62 may transmit / receive a radio frequency (RF) signal of a specific frequency band converted from a baseband signal to / from other electronic devices, and may process a radio frequency (RF) signal of a specific frequency band.

[0118] The communication device 60 can perform discontinuous reception (DRX) to reduce the power of the electronic device 3. According to DRX, the electronic device 3 can maintain a power efficiency mode, such as a micro-sleep or off period, within the DRX cycle. As an example, the communication device 60 can be switched to an idle state (e.g., an RRC_IDLE state) and / or an inactive state (e.g., an RRC_INACTIVE state) to reduce power consumption. In this case, the electronic device 3 switched to an idle and / or inactive state can be set to use a DRX method. As an example, the electronic device 3 switched to an idle and / or inactive state can be set to monitor signals related to paging only in a specific subframe, frame or time slot according to a DRX cycle set by a base station or the like.

[0119] In some example embodiments, when the communication device 60 operates in a DRX state to reduce power consumption, as the duration of the power-off sequence increases, it affects both the delay and current consumption of the electronic device 3. Therefore, in some example embodiments, the duration of the power-off sequence may be optimized for DRX operation.

[0120] Fig.14 and Fig.15 It shows that according to Fig.13 A waveform diagram of the regulated operating waveform of an electronic device.

[0121] Fig.14 1 shows a voltage waveform of the regulation voltage VLDO when the regulator immediately turns off the power transistor P_TR during the power-off sequence according to the DRX operation. During the power-off sequence, the first driving voltage VDDPE has a level higher than that of the second driving voltage VDDCE, and this is because a leakage current is generated when the first driving voltage VDDPE is reversed (time point t3). Meanwhile, in the case where the duration of the power-off sequence of the DRX operation is reduced, as shown in FIG. Fig.14 As shown, a voltage inversion occurs between the first driving voltage VDDPE and the second driving voltage VDDCE, and thus a leakage current is generated. To prevent or reduce the leakage current, there is a time delay between the start time point t1 of the power-off sequence associated with the first driving voltage VDDPE and the start time point t2 of the power-off sequence associated with the second driving voltage VDDCE.

[0122] Fig.15 FIG. 3 shows a voltage waveform of the regulation voltage VLDO when the regulation voltage first drops to the threshold voltage DML through the DVS circuit 330 and then the power transistor P_TR is turned off during the power-off sequence. In the case where the power transistor is turned off after the regulation voltage VLDO drops to the threshold voltage DML, the voltage reversal can be prevented or reduced without a time delay, which is to prevent or reduce Fig.14 The leakage current solution in the circuit can therefore not generate leakage current.

[0123] One or more of the elements disclosed above may include or be implemented in a processing circuit, such as hardware including logic circuits; a hardware / software combination, such as a processor that executes software; or a combination thereof. For example, the processing circuit may more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system on a chip (SoC), a programmable logic unit, a microprocessor, an application specific integrated circuit (ASIC), etc.

[0124] Although various exemplary embodiments of the inventive concept have been described, it should be understood that the inventive concept should not be limited to these various exemplary embodiments, but various changes and modifications may be made by those of ordinary skill in the art. Therefore, the inventive concept should not be limited to any single exemplary embodiment described herein, and the scope of the inventive concept should be determined according to the appended claims.

Claims

1. A regulator, include: a reference voltage generating circuit configured to generate a second reference voltage different from the first reference voltage according to a dynamic control signal; an error amplifier configured to generate an error voltage based on the second reference voltage and a regulation voltage at an output node; a power transistor including a gate terminal connected to the error amplifier and configured to receive an input voltage to output the regulated voltage to the output node based on the error voltage; a dynamic voltage scaling (DVS) circuit connected to the reference voltage generating circuit and the output node and configured to reduce the regulated voltage to the second reference voltage; and The control circuit is configured to receive a power-off signal from a processor and is further configured to turn off the power transistor when the regulated voltage drops to the second reference voltage through the DVS circuit. 2 . The regulator of claim 1 , further comprising a discharge circuit connected to the output node and configured to discharge the regulated voltage.

3. The regulator according to claim 2, in, The DVS circuit is configured to operate from a start time point of a power-off period started according to the power-off signal to a specific time point, and the specific time point is defined as a point at which the regulated voltage becomes the second reference voltage.

4. The regulator according to claim 3, in, The discharge circuit is configured to operate during the power-off period.

5. The regulator according to claim 3, in, The DVS circuit is configured to operate at a higher discharge rate during the power-off period than a discharge rate after the specific time point.

6. The regulator according to claim 1, in, The DVS circuit comprises: a DVS amplifier configured to output a comparison voltage based on a comparison of the second reference voltage and the regulation voltage; and A DVS transistor includes a gate terminal connected to the DVS amplifier and one terminal connected to the output node, and is configured to drop the regulation voltage to the second reference voltage based on the comparison voltage. 7 . The regulator of claim 1 , further comprising a buffer connected to the error amplifier and the gate terminal of the power transistor and configured to buffer the error voltage to output a buffered voltage.

8. The regulator according to claim 1, in, When the power-off signal is received, the second reference voltage is set to a threshold voltage.

9. The regulator according to claim 8, in, The control circuit is configured to sense the threshold voltage from the regulated voltage after receiving the power-off signal, and is configured to send a disconnect signal to the power transistor based on the sensed threshold voltage.

10. A power management integrated circuit, include: one or more regulators configured to regulate an input voltage and output a regulated voltage; and A control circuit is configured to control the one or more regulators, wherein the control circuit is configured to operate a dynamic voltage scaling (DVS) loop, the DVS loop drops the regulated voltage to a reference voltage that varies according to a dynamic control signal when a power-off signal is provided from a processor, and turns off one or more power transistors included in the one or more regulators when the regulated voltage drops to the reference voltage.

11. The power management integrated circuit according to claim 10, in, The one or more regulators are configured to adjust the regulated voltage based on a first discharge rate until the regulated voltage drops to the reference voltage, and are further configured to adjust the regulated voltage dropped to the reference voltage based on a second discharge rate lower than the first discharge rate after the regulated voltage drops to the reference voltage.

12. The power management integrated circuit according to claim 10, in, The control circuit is configured to set the reference voltage to a threshold voltage when the power-off signal is received.

13. The power management integrated circuit according to claim 12, further comprising: include: A first register configured to store the dynamic control signal; and The second register is configured to store the threshold voltage.

14. The power management integrated circuit according to claim 13, in, The control circuit is configured to set the dynamic control signal stored in the first register to correspond to the threshold voltage stored in the second register when the power-off signal is received.

15. The power management integrated circuit according to claim 10, in, Each of the regulators comprises: a reference voltage generating circuit configured to generate the reference voltage in response to the dynamic control signal; an error amplifier configured to generate an error voltage based on the reference voltage and the regulation voltage at an output node; a power transistor including a gate terminal connected to the error amplifier and configured to receive an input voltage to output the regulated voltage to the output node based on the error voltage; and A dynamic voltage scaling (DVS) circuit is connected to the reference voltage generating circuit and the output node and is configured to reduce the regulated voltage to the reference voltage.

16. The power management integrated circuit according to claim 15, in, The DVS loop is defined as a loop configured to reduce the regulated voltage based on the DVS circuit and the output node.

17. A method of operating a power management integrated circuit, include: receiving a power-off signal from a processor; using a dynamic voltage scaling (DVS) loop included in the power management integrated circuit to reduce the regulated voltage to a reference voltage; and A power transistor included in the power management integrated circuit is turned off based on the regulated voltage dropping to the reference voltage.

18. The method of claim 17, further comprising sensing whether the regulated voltage corresponds to the reference voltage.

19. The method of claim 17, further comprising setting the reference voltage to a threshold voltage based on the received power-off signal.

20. The method according to claim 17, further comprising: include: adjusting the regulated voltage based on a first discharge rate until the regulated voltage drops to the reference voltage; and After the regulated voltage drops to the reference voltage, the regulated voltage dropped to the reference voltage is adjusted based on a second discharge rate lower than the first discharge rate.

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