Method and system for embedded ECC protection

Abstract

The invention relates to a method and system for embedded ECC protection, and specifically proposes a memory system having interconnects configured to receive commands from the system to read data from and / or write data to a memory device. The memory system also has a bridge configured to receive the command from the interconnect to manage ECC data, and performing address translation between a system address and a physical memory device address by calculating a first ECC memory address for a first ECC data block after and adjacent to a first data block having a first data address, a second ECC memory address is calculated after and adjacent to the first ECC block, and a second data address is calculated after and adjacent to the second ECC block.

Description

[0001] Information about divisional applications

[0002] This case is a divisional application. The parent case of the divisional application is an invention patent application with application date of December 10, 2019, application number 201980068709.6, and invention name “Method and system for embedded ECC protection”. Technical Field

[0003] The present application relates to the field of memory. Background Art

[0004] In a computing system, data stored in a memory, such as a dynamic random access memory (DRAM) or a double data rate (DDR) synchronous dynamic random access memory (SDRAM), can be affected by errors in the controller, physical interface (PHY), or circuit board during a write or read operation, or by errors in the memory array itself when the data is stored in the memory array. In addition, external memory is often made by a third party and / or may not be rated for functional safety applications or not reliable enough for the application. Erroneous data or instructions from the memory can cause the system to operate incorrectly. Incorrect operation of the system is undesirable, especially in systems or applications where functional safety or reliability is critical.

[0005] There are generally three types of memory errors: permanent, temporary, and systematic. Permanent errors are usually the result of physical damage or degradation of the memory or associated circuitry, or can be shorts in the silicon or wires. Temporary errors can be attributed to particle strikes and typically result in a bit flipping state (e.g., in a flip-flop). Systematic errors are errors in the logic, for example, the system is working correctly as designed, but there is an error in the hardware or software. Summary of the invention

[0006] Examples described herein include an integrated circuit including an interconnect configured to receive a command from a system to read data from and / or write data to a physical address of a memory device. The integrated circuit further includes a bridge configured to receive the command from the interconnect and perform address translation between system addresses and the physical addresses by calculating a first error correction code (ECC) memory address for a first ECC data block following and adjacent to a first data block having a first data address, calculating a second ECC memory address following and adjacent to the first ECC block, and calculating a second data address following and adjacent to the second ECC block.

[0007] Another exemplary integrated circuit described herein includes an interconnect configured to receive a command from a system for reading and / or writing a portion of data. The integrated circuit further includes a bridge configured to receive the command from the interconnect and to check and calculate ECC data for a data burst including the portion of data.

[0008] Another exemplary integrated circuit described herein includes an interconnect configured to receive a command from a system for reading and / or writing a portion of data. The integrated circuit further includes a bridge configured to receive the command from the interconnect and to check and calculate ECC data, the bridge further configured to buffer the ECC data of a complete data burst including the portion of data.

[0009] Examples described herein also include a memory system having a memory device, a processor, and an interconnect configured to receive a command from the processor to read data from and / or write data to a physical address of the memory device. The memory device further includes a bridge configured to receive the command from the interconnect and perform address translation between system addresses and the physical addresses by calculating a first ECC memory address for a first ECC data block after and adjacent to a first data block having a first data address, calculating a second ECC memory address after and adjacent to the first ECC block, and calculating a second data address after and adjacent to the second ECC block.

[0010] Another exemplary memory device described herein includes a memory system having a memory device, a processor, and an interconnect configured to receive a command from the processor for reading a portion of data and / or writing a portion of data to the memory device; and a bridge configured to receive the command from the interconnect and to check and calculate ECC data, the bridge further configured to cache the ECC data of a complete data burst including the portion of data.

[0011] Examples described herein also include a method of writing data to or reading data from an external memory. The method includes: receiving a command from a system to read and / or write a portion of data; and buffering ECC data of a complete data burst including the portion of data.

[0012] Also described herein are exemplary methods of writing data to or reading data from an external memory. The method includes receiving a command from a system to read and / or write a portion of data and checking ECC data for a complete data burst including the portion of data.

[0013] An exemplary method of translating a system memory address into a physical memory address is also described herein. The method includes providing a first ECC block associated with a first data block and providing a second ECC block associated with a second data block. The method further includes calculating a first ECC memory address for the first ECC data block that is subsequent to and adjacent to the first data block having a first data address, calculating a second ECC memory address that is subsequent to and adjacent to the first ECC block, and calculating a second data address for the second data block that is subsequent to and adjacent to the second ECC block. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] To describe various examples in detail, reference will now be made to the accompanying drawings, in which:

[0015] Figure 1 A block diagram of an exemplary memory system is illustrated.

[0016] Figure 2 A block diagram of an exemplary ECC bridge is illustrated.

[0017] Figure 3 A block diagram illustrating an exemplary read-modify-write block.

[0018] Figure 4 A block diagram of an exemplary embedded ECC block is illustrated.

[0019] Figure 5 An exemplary addressing mode is illustrated.

[0020] Figure 6 Graphical instructions Figure 5 An exemplary portion of an exemplary addressing mode.

[0021] Figure 7 A block diagram illustrating an exemplary state machine (SM) block.

[0022] Figure 8 An exemplary device including the exemplary memory system described herein is illustrated. DETAILED DESCRIPTION

[0023] The expression “based on” means “based at least in part on.” Thus, if X is based on Y, then X may vary with Y and any number of additional factors.

[0024] The examples described herein calculate single error correction double error detection (SECDED) ECC across every word of a burst. The size of the burst depends on the requirements of the memory device and is typically a power of 2 (e.g., 16, 32, 64, 128, 256). The ECC syndromes are stored intermixed with normal data ("embedded") so that a burst of data or ECC data does not extend beyond a page boundary. Typically, storage and retrieval consists of two different commands: one for data and the other for ECC syndromes. Address calculations for data and ECC syndromes can be done automatically so the host system still experiences a flat, continuous memory map. Address calculations can use a rolling system that ensures that a permanent failure on a single address will not be masked by losing the entire data / ECC chunk.

[0025] Some embodiments also calculate and check the ECC across the entire burst, regardless of how much data is written or read, to further ensure that there are no bursts or aliasing issues that provide mismatched ECC syndromes. The exemplary systems described herein automatically perform read-modify-write (RMW) operations when writing less than a full ECC amount of data while maintaining full data coherence. The exemplary systems described herein also implement an ECC cache, where writes and reads are stored and merged in order to reduce RMW operations that would otherwise be incurred when receiving a sub-burst write, as well as multiple reads that would be required when requesting a sub-burst read.

[0026] Figure 1 A memory system 100 is shown according to the examples described herein. The memory system 100 includes an interconnect 101 that provides an interface for a master device 107 to read from and write to memory. For example, the master device 107 may include a processor. The interconnect 101 performs any necessary transformations and sends calls from the master device 107 to the ECC bridge 102. The ECC bridge 102 acts as an interface between the computing system and the memory devices. For example, the ECC bridge 102 may handle error correction code (ECC) checking, address translation between system addresses and physical addresses, and voltage translation between the computing system domain and the memory device domain (starting with the memory controller 102). The memory domain includes: a memory controller 103, a physical layer (PHY) 104, a circuit board trace 105, and the memory device 106 itself. For example, the memory controller 103, the physical layer (PHY) 104, the circuit board trace 105, and the memory device 106 may be SDRAM and may be external or internal RAM.

[0027] Figure 2A block diagram of an ECC bridge 102 is shown. The ECC bridge 102 interfaces with an interconnect 101 operating on a computing system voltage using a computing system voltage domain 201. The ECC bridge 102 also includes a memory voltage domain 203 for interfacing with a memory device 106 operating on a memory voltage (e.g., a DDR voltage). The ECC bridge 102 also includes a voltage converter 202 for performing voltage conversion between the computing system voltage domain 201 and the memory voltage domain 203.

[0028] The memory voltage domain 203 includes a command arbiter 204 that receives voltage converted read or write commands (and accompanying data) from the voltage converter 202 and queues the received commands. The read modify write (RMW) block 205 handles read modify write operations, such as a read command for an incomplete ECC amount write command. The ECC amount is the data size per ECC syndrome (e.g., 8 bytes of data). The embedded ECC block 206 performs three main functions: adding / calculating ECC, caching ECC data, and translating system addresses into physical addresses in the memory device.

[0029] Figure 3 2. The RMW block 205 is shown in more detail in FIG. 2. The commands and data from the command arbitrator 204 are received by the arbitration scheduler 301. The arbitration scheduler 301 acts as an entry point to the RMW block 205, routing incoming commands and performing additional necessary tasks. The arbitration scheduler 301 may forward any command that does not require additional processing by the RMW block 205 (as described below) and / or does not have an address conflict (coherent) with any command in the RMW backlog holding queue 302 (which may be a first-in-first-out (FIFO) queue) to the embedded ECC block 206. For example, the arbitration scheduler 301 may forward a write command to the embedded ECC block 206 if any of the following conditions are met: (1) all write data byte enables are set for the ECC amount; (2) the system address is not in an ECC protected area, or (3) the data is not coherent with any command in the RMW backlog holding queue 302. If the data is not relevant to any command in the RMW backlog holding queue 302, the arbitration scheduler 301 may forward the read command to the embedded ECC block 206. The command forwarded by the arbitration scheduler 301 to the embedded ECC block 206 may be forwarded through the multi-threaded FIFO queue 304.

[0030] For commands to write a partial amount of ECC data, arbitration scheduler 301 issues a read command for a full data burst and places the write command in RMW backlog holding queue 302. When read data is returned from state machine (SM) 207, it is placed in data merge block 303 where it is merged with the partial amount of write data placed in RMW backlog holding queue 302. Data merge block 303 routes the merged data to arbitration scheduler 301, which then issues a write command for the merged data burst to be routed to embedded ECC 206.

[0031] The arbitration scheduler 301 also handles commands that are no longer coherent due to a change in the environment in the RMW backlog holding queue 302. In this case, the data may need to be merged as described above, or the command may simply be passed to the embedded ECC 206. As described above, the RMW backlog holding queue 302 holds commands and data that are awaiting coherent resolution or awaiting return data due to a partial write.

[0032] Figure 4 4. The embedded ECC block 206 is shown in more detail in FIG. 4. The commands and data sent to the embedded ECC block 206 are received by the command arbitration and generation block 401 and the ECC encoding block 405. The ECC encoding block 405 calculates the ECC for the amount of data to be written in the write command. The ECC encoding block 405 may also optionally encode the address of the data into each ECC. The encoded address may be the address of the ECC amount, burst, or block, and may be a system or virtual address, or may be a physical address in the memory device. More than one of these addresses may be encoded into each ECC syndrome.

[0033] For inbound commands, command arbitration and generation block 401 generates command sequences based on ECC region and ownership information. For example, certain cache entries may be "owned" by a specific CPU and used only by that CPU. A small set of ECC cache lines in ECC cache buffer 402 may be reserved for all other system initiators.

[0034] When a read command is received by the command arbitration and generation block 401, the command arbitration and generation block 401 determines whether the ECC of the associated data is already in the ECC cache buffer 402. If the ECC is in the ECC cache buffer 402, the command arbitration and generation block 401 will route the read command to the SM 207 and use the cached ECC. If the ECC of the associated data is not in the ECC cache buffer 402, but the ECC cache buffer 402 has room to cache the ECC block, the command arbitration and generation block 401 will route the read command to the SM 207 for both the data and the ECC block. When the SM 207 returns the ECC block, the ECC block will be stored in the ECC cache buffer 402 (optionally via the multi-threaded FIFO queue 404). If the ECC of the associated data is not in the ECC cache buffer 402 and there is no room for additional ECC blocks, the ECC cache buffer 402 will remove the oldest read ECC data before sending the read command to the SM 207 for both the data and the ECC block. If the removed ECC data is "dirty," meaning that the cached ECC data is different than the ECC data stored in physical memory, then the ECC block may be written to external memory.

[0035] When a write command is received by the command arbitration and generation block 401, the command arbitration and generation block 401 determines whether the ECC of the associated data is already in the ECC cache buffer 402. If the ECC is in the ECC cache buffer 402, then the ECC will be merged into the cached ECC in the ECC cache buffer 402 and will be marked as "dirty". If the ECC of the associated data is not in the ECC cache buffer 402, but the ECC cache buffer 402 has space to cache the ECC block, then the oldest owned entry in the ECC cache buffer 402 will be allocated and the ECC will be stored in that space and marked as "dirty". The command arbitration and generation block 401 issues the write command to the SM 207 for the data block.

[0036] If the ECC of the associated data is not in the ECC cache buffer 402 and the ECC cache buffer does not own any space, then the command arbitration and generation block 401 issues a write command to the SM 207 for the data block. If the ECC of the associated data is not in the ECC cache buffer 402 and all owned entries are dirty, then the oldest entry in the ECC cache buffer 402 will be removed and, if dirty, written to external memory. That space will be reallocated and the ECC of the write command will be written to that reallocated space in the ECC cache buffer 402.

[0037] Commands sent to the SM 207 by the command arbitration and generation block 401 may be sent through the multi-threaded FIFO queue 403 .

[0038] exist Figure 4 In the exemplary embedded ECC block 206 of FIG. 4 , the ECC cache buffer 402 holds previously read and written ECC blocks for future use. The ECC cache buffer 402 has a "dirty" flag for each byte of ECC data that indicates whether the cached ECC byte is different from the ECC byte stored in the physical memory. In the example described herein, each entry in the ECC cache buffer holds ECC syndrome data for eight data bursts. In this case, the ECC cache buffer holds 64 bytes of ECC syndrome data for eight consecutive data blocks (512 bytes).

[0039] As described above, the embedded ECC block 206 also performs address translation between system addresses and physical memory addresses. The command arbitration and generation block 401 performs this address translation and inserts the translated addresses into the read and write commands issued to the SM 207. In the example described herein, the system addresses are transformed so that two 64-byte ECC blocks are placed between two 512-byte data blocks (each with eight 64-byte memory bursts). Figure 5 An example of this address translation is shown in Figure 5 As can be seen in FIG. 1 , ECC blocks 52 and 53 are arranged consecutively between 512-byte data blocks 51 and 54 .

[0040] This address translation provides protection against failures in command or addressing by staggering all address bits across data and ECC syndrome storage. This staggered pattern provides efficient use of memory space, reserving 8 / 9 of the space for normal data use, while only occupying 1 / 9 for ECC syndrome, with little, if any, wasted memory space. Furthermore, since every 8 data bursts (e.g., 512 bytes) share a single block for ECC, address bit errors may never hit the aligned ECC block, thereby protecting memory addresses as well as data. Specifically, by using a power of 2 for the burst count (e.g., eight in this example) and a power of 3 for the burst count plus the ECC syndrome (e.g., in this example, burst count (8) + 1 = 9), any address bit failure will prevent data and ECC alignment, resulting in an error. Furthermore, the two 64-byte ECC blocks are arranged consecutively so that the burst alignment will not cross any 128-byte page boundary. For example, this arrangement can support 128-byte bursts, allowing 128 bytes to start on a 128-byte memory aligned boundary. Different numbers and sizes of ECC blocks and data bursts / blocks may be used, depending on the burst alignment configuration of the memory device, and so that the number of data blocks plus ECC blocks has a prime bias.

[0041] Figure 6More detailed map explanation Figure 5 The relationship between data blocks 51 and 54 and ECC blocks 52 and 53 is shown in FIG. Data block 51 has eight 64-byte bursts d0 to d7. Data block 54 has eight 64-byte bursts d8 to dF. 64-byte ECC block 52 contains ECC data e0 for data block 51 and 64-byte ECC block 53 contains ECC data e1 for data block 54. Figure 5 and 6 , the first burst of blocks 51 and 54 will always be on a 128-byte boundary throughout the memory. Therefore, in this particular example, all read commands sent to the memory device should be 128-bit aligned, and all two-burst operations are always aligned by two bursts (128 bytes in this case).

[0042] The present system encompasses other alignment examples. For example, 256-byte alignment can be used with a 64-burst memory device. In this case, four 64-byte ECC blocks will be placed between the 16 data blocks. This ensures that all master device requests that are 256-byte aligned are also 256-byte aligned with the memory device.

[0043] Figure 7 1 shows a block diagram of the state machine (SM) 207. The arbiter 701 is responsible for arbitrating commands to the memory controller 103 to ensure that resources are available. The commands sent by the arbiter 701 to the memory controller 103 may be sent via the multi-threaded FIFO queue 704. When the read return FIFO 703 receives a read command from a memory device (e.g., Figure 1 When the data and ECC are received from the memory device 106 of the embedded ECC, the read return FIFO maintains the ownership of the data and that data, and returns the ECC data to the embedded ECC 206. The read return FIFO 703 sends the data to the ECC correction and detection (ECC COR / DET) block 702, which uses the ECC data received from the embedded ECC block 206 to single-error correct and / or double-error detect the ECC protection area of ​​the memory in the case of a SECDED device, and returns the corrected read data to the RMW block 205 for merging. The ECC correction and detection block 702 performs this ECC check on the entire burst of data received from the memory device. Since eight ECC blocks are checked per burst, and since the ECC syndrome also contains the memory address, the probability of hitting an error on the ECC syndrome is small in the event of an address bit error. The read return FIFO 703 can return the read ECC data directly to the embedded ECC 206.

[0044] The examples of ECC caches described herein (e.g., examples of ECC cache buffers 402) provide efficient merging and caching of transactions to avoid less than ideal bursts on the memory device interface. Certain embodiments check and calculate ECC across the entire burst, regardless of the requested data, to provide further protection for commands and addresses. Checking ECC across the entire data burst access (e.g., the entire 64-byte data burst for DDR memory) prevents command or addressing failures. Some examples may also encode the address of the transaction into the ECC syndrome by a novel scheme of extending the address across the burst, thereby further protecting the transaction without additional bits. Some examples use additional diagnostic measures such as parity checks to further protect functions (e.g., address translation, generating ECC, etc.) in order to achieve higher error detection rates. Some examples can be further extended by adding obfuscation or encryption to protect data and enhance error detection.

[0045] The solution described in this specification is superior to existing solutions because the solution described in this specification provides more efficient use of address space (potentially eliminating wasted memory), provides better protection against address failures (rows, columns, banks, and ranks) by using a novel address translation scheme, provides more efficient use of the memory interface by minimizing RMW and sub-burst accesses, provides protection for the entire memory controller by generating two independent commands before they enter the memory command queue, and encoding addresses into ECC syndromes provides additional protection.

[0046] The embedded ECC protection techniques described herein may be implemented in any type of electronic system or device, and are particularly useful for systems and devices in applications where functional safety is critical, such as automotive (e.g., ADAS or advanced driver assistance system systems) or industrial applications. Examples of such devices may include various internal and / or external components that contribute to the functionality of the device, which components may include hardware elements (including circuitry), software elements (including computer code stored on a tangible computer-readable medium), or a combination of both hardware and software elements. A device may include input / output (I / O) ports, input structures, one or more processors, memory, a power supply, etc.

[0047] Figure 8 One such exemplary device 80 is shown having an exemplary processor 81 and memory device 100 according to the examples described herein.

[0048] The processor 81 can control the general operation of the device 80. For example, the processor 81 can provide processing power to execute an operating system, programs, user and application interfaces, and any other functions of the device. The processor 81 can include one or more microprocessors, such as one or more general-purpose microprocessors, special-purpose microprocessors (ASICs), or a combination of such processing components. The processor 81 can include one or more processors based on an x86 or RISC architecture, as well as a special-purpose graphics processor (GPU), an image signal processor, a digital signal processor, a video processor, an audio processor, and / or related chipsets. The processor 81 can include several processing cores of the same or different types and can be implemented as a system on a chip (SOC) device.

[0049] Instructions or data to be processed by processor 81 may be stored in a computer-readable medium such as memory device 100. Memory device 100 may include a memory device (eg, DRAM, SDRAM, or internal memory), and an ECC bridge that implements the embedded ECC functionality described above.

[0050] Although ECC functionality and address translation are described herein as occurring in the ECC bridge 102, this functionality may alternatively be implemented in whole or in part in another component (eg, the memory controller 103).

[0051] Modifications are possible in the described embodiments, and other embodiments are possible within the scope of the claims.

Claims

1. An integrated circuit, comprising: An error correction code (ECC) circuit configured to be coupled to a memory and comprising an arbitration circuit configured to: receiving a memory command directed to the memory, wherein the memory command is associated with reading or writing a first data unit; as well as Based on the memory command, determining a first data address associated with the first data unit and a first ECC address associated with the first ECC data, wherein: The first ECC data is associated with the first data unit and the second data unit; and The first data address and the first ECC address are such that, in the address space of the memory: The first data unit is followed by the second data unit, and the second data unit is followed by the first ECC data; The first ECC data is adjacent to the second ECC data, and the second ECC data is associated with the third data unit; and The second ECC data is followed by the third data unit. 2 . The integrated circuit of claim 1 , wherein the first data address is adjacent to a second data address in the address space of the memory.

3. The integrated circuit of claim 2, wherein: The second data address is associated with a fourth data unit; and In the address space of the memory, the fourth data unit is preceded by third ECC data associated with the fourth data unit.

4. The integrated circuit of claim 1, wherein: The first data unit is a first data burst; The second data unit is a second data burst; and The first ECC data is associated with a plurality of data bursts including the first data burst and the second data burst.

5. The integrated circuit of claim 4, wherein: The size of the first data unit is 64 bytes; and The size of the multiple data bursts is 512 bytes.

6. The integrated circuit of claim 1, wherein: The ECC circuit further includes an ECC buffer coupled to the arbitration circuit and configured to store the ECC data associated with the first data unit; and The arbitration circuit is further configured to, when the memory command is associated with the read of the first data unit, determine whether to request the ECC data from the memory based on whether the ECC data is cached in the ECC buffer.

7. The integrated circuit of claim 6, wherein the ECC circuit further comprises an ECC encoder circuit coupled to the arbitration circuit and configured, when the memory command is associated with the write of the first data unit: generating the ECC data; and The ECC data is caused to be stored in the ECC buffer.

8. The integrated circuit of claim 7, wherein the ECC encoder circuit is configured to encode at least one of: the first data address or the first ECC address in the ECC data.

9. The integrated circuit of claim 1 , further comprising: a read-modify-write (RMW) circuit coupled to the ECC circuit, the RMW circuit comprising: scheduler circuit; and a data merging circuit coupled to the scheduler circuit, wherein the scheduler circuit is configured to: determining whether the first data unit is smaller than an ECC amount; and When the first data unit is smaller than the ECC amount and the memory command is associated with the writing of the first data unit: requesting a fourth data unit from the memory; and causing the data merging circuit to merge the fourth data unit and the first data unit to generate a merged data unit; and The merged data unit is provided to the ECC circuit.

10. The integrated circuit of claim 1, further comprising: a memory controller coupled to the ECC circuit; as well as The memory is coupled to the memory controller.

11. The integrated circuit of claim 1 , further comprising: A set of processors; as well as An interconnect is coupled between the ECC circuit and the set of processors.

12. A method comprising: receiving a memory command associated with the first data unit and directed to a memory; Determining a first data address of the first data unit in an address space of the memory; Determine a first ECC address of the first ECC data in the address space of the memory, the first ECC data being associated with the first data unit and the second data unit such that: In the address space of the memory, the first data unit is followed by the second data unit, and the second data unit is followed by the first ECC data; In the address space of the memory, the first ECC data is adjacent to the second ECC data, wherein the second ECC data is associated with a third data unit; as well as In the address space of the memory, the second ECC data is followed by the third data unit; as well as The memory is accessed using at least one of the first data address and the first ECC address.

13. The method of claim 12, wherein the first data address is determined such that the first data address is adjacent to a second data address in the address space of the memory.

14. The method of claim 13, wherein the second data address is associated with a fourth data unit, the fourth data unit not being associated with the first ECC data.

15. The method of claim 12, wherein: The first data unit is a first data burst; The second data unit is a second data burst; and The first ECC data is associated with a plurality of data bursts including the first data burst and the second data burst.

16. The method of claim 15, wherein: The size of the first data unit is 64 bytes; and The size of the multiple data bursts is 512 bytes.

17. The method of claim 12, further comprising: determining whether the first ECC data exists in the ECC buffer; as well as Whether to access the memory using the first ECC address is determined based on whether the first ECC data exists in the ECC buffer.

18. The method of claim 12, further comprising: generating the first ECC data; as well as Before storing the first ECC data in the memory, the first ECC data is stored in an ECC buffer.

19. The method of claim 18, wherein the generating the first ECC data comprises encoding at least one of: the first data address or the first ECC address in the ECC data.

20. The method of claim 12, further comprising: determining whether the first data unit is smaller than an ECC amount; as well as When the first data unit is smaller than the ECC amount and the memory command is associated with writing of the first data unit: requesting a fourth data unit from the memory; as well as merging the fourth data unit and the first data unit to generate a merged data unit; as well as The merged data unit is written to the memory based on the first data address.

21. An apparatus comprising: a memory configured to store data according to an address space; as well as A circuit coupled to the memory and configured to: receiving a first write command associated with a first set of data; generating a first set of error correction code (ECC) data for the first set of data; receiving a second write command associated with a second set of data; generating a second set of ECC data for the second set of data; causing the first set of data to be stored in the memory; causing the second set of data to be stored in the memory to be adjacent to the first set of data in the address space; causing the first set of ECC data to be stored in the memory to be adjacent to and prior to the first set of data in the address space; as well as The second set of ECC data is caused to be stored in the memory to be adjacent to and after the second set of data in the address space.

22. The device of claim 21, wherein the circuit is configured to: receiving a third write command associated with a third set of data; generating a third group of ECC data for the third group of data; causing the third set of ECC data to be stored in the memory to be adjacent to the second set of ECC data in the address space; and The third set of data is caused to be stored in the memory to be adjacent to and after the third set of ECC data in the address space.

23. The apparatus of claim 21, wherein: The first write command is a read-modify-write command that specifies a third set of data; and The circuit includes a read-modify-write circuit configured to, based on the read-modify-write command: reading a fourth set of data from the memory; as well as The third set of data is combined with the fourth set of data to generate the first set of data.

24. The device of claim 21, wherein the memory is a random access memory.

25. The apparatus of claim 21, wherein the first set of ECC data is single error correction double error detection (SECDED) data.

26. The device of claim 21, wherein the first set of ECC data encodes at least one of: an address of the first set of data or an address of the first set of ECC data.

27. The apparatus of claim 21, wherein: The size of the first set of data is 512 bytes; and The size of the first group of ECC data is 512 bytes.

28. An apparatus comprising: a memory configured to store data according to an address space; a processor configured to provide a first write command to write a first set of data and a second write command to write a second set of data; as well as a memory control circuit coupled between the memory and the processor and configured to: receiving the first write command and the second write command; and causing the first group of data, a first group of error correction code (ECC) data associated with the first group of data, The second set of data and a second set of ECC data associated with the second set of data are stored in the memory such that: The first set of data is adjacent to the second set of data in the address space; The first set of ECC data is adjacent to and precedes the first set of data in the address space; and The second group of ECC data is adjacent to and subsequent to the second group of data in the address space.

29. The device of claim 28, wherein the memory control circuit comprises an ECC calculation circuit configured to generate the first set of ECC data and the second set of ECC data.

30. The apparatus of claim 28, wherein: The processor is configured to provide a third write command to write a third set of data; and The memory control circuit is configured to cause the third set of data and a third set of ECC data associated with the third set of data to be stored in the memory such that: The third group of ECC data is adjacent to the second group of ECC data in the address space; as well as The third group of data is adjacent to the third group of ECC data and is located after the third group of ECC data in the address space.

31. The device of claim 28, wherein the memory is a random access memory.

32. The apparatus of claim 28, wherein the first set of ECC data is single error correction double error detection (SECDED) data.

33. The device of claim 28, wherein the first set of ECC data encodes at least one of: an address of the first set of data or an address of the first set of ECC data.

34. The apparatus of claim 28, wherein: The size of the first set of data is 512 bytes; and The size of the first group of ECC data is 512 bytes.

35. A method comprising: Receive the first set of data; generating a first set of error correction code (ECC) data based on the first set of data; Receive a second set of data; generating a second set of ECC data based on the second set of data; The first set of data, the first set of ECC data, the second set of data, and the second set of ECC data are stored in a memory such that: The first set of data is adjacent to the second set of data in the address space; The first group of ECC data is adjacent to the first group of data and is located before the first group of data in the address space; as well as The second group of ECC data is adjacent to the second group of data and is located after the second group of data in the address space.

36. The method of claim 35, wherein receiving the first set of data comprises: receiving a read-modify-write command specifying a third set of data; as well as Based on the read-modify-write command: reading a fourth set of data from the memory; as well as The third set of data is combined with the fourth set of data to generate the first set of data.

37. The method of claim 35, wherein the memory is a random access memory.

38. The method of claim 35, wherein the first set of ECC data is single error correction double error detection SECDED data.

39. The method of claim 35, wherein the first set of ECC data encodes at least one of: an address of the first set of data or an address of the first set of ECC data.

40. The method of claim 35, wherein: The size of the first set of data is 512 bytes; and The size of the first group of ECC data is 64 bytes.

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