Method for improving FFT refresh rate based on dual-port RAM in FPGA and computer device

Abstract

The invention relates to the field of FFT refresh rates, in particular to a method for increasing the FFT refresh rate based on a dual-port RAM in an FPGA and a computer device. According to the scheme, the method comprises the following steps: instantiating a dual-port RAM, connecting a write data end with a write clock signal, a write address signal and a write data signal, and connecting a read data end with a read clock signal, a read address signal and a read data signal; the FPGA is sequentially written into the dual-port RAM from a data writing port of the dual-port RAM, and a writing address signal of the RAM is circularly and progressively increased from 0 to 1023; after the data is fully written, a data reading port of the dual-port RAM reads out the first frame data cached in the RAM from the address 0 to 1023 in a circulating and progressive increasing manner; and the initial address of the read data of the new frame of FFT data is the end address of the read data of the previous frame, and the initial address of the read data of the new frame is fallback forwards 205, and the initial address is cyclically and progressively increased to the previous address of the initial address of the read operation of the current frame. The method is suitable for improving the FFT refresh rate.

Description

Technical Field

[0001] The invention relates to the field of FFT refresh rate, and in particular to a method for improving FFT refresh rate based on a dual-port RAM in an FPGA and a computer device. Background Art

[0002] In a spectrum analyzer, the spectrum of a signal is obtained by calculating the FFT (Fast Fourier Transform) of the collected signal. In order to capture smaller pulse signals, this is usually achieved by increasing the FFT refresh rate to increase the number of calculations, which is equivalent to shortening the calculation interval.

[0003] A common way to increase the FFT refresh rate is to delay and overlap the input data and then perform multi-channel FFT calculations. This method can greatly increase the overlap rate of the input data, thereby greatly increasing the FFT refresh rate, and the spectrum analyzer can capture smaller signals.

[0004] Because multi-channel FFT calculation is adopted by overlapping FFT calculation paths, the calculation resources of FPGA (Field Programmable Gate Array) are also greatly increased. Summary of the invention

[0005] The purpose of the present invention is to overcome the shortcomings of the prior art and provide a method and a computer device for improving the FFT refresh rate based on a dual-port RAM (Random Access Memory) in an FPGA, thereby improving the FFT refresh rate without increasing the FPGA computing resources.

[0006] The present invention adopts the following technical solutions to achieve the above-mentioned purpose. In a first aspect, the present invention provides a method for improving the FFT refresh rate based on a dual-port RAM in an FPGA, comprising: S1, instantiate a dual-port RAM, connect the write data end to the write clock signal, write address signal and write data signal respectively, and connect the read data end to the read clock signal, read address signal and read data signal respectively; S2, FPGA writes the input data from the data write port of the dual-port RAM to the dual-port RAM in sequence under the beat of the write clock signal. The write address signal of the RAM increases cyclically from 0 to 1023. The written data is simultaneously written to the write port in the dual-port RAM for cyclic overwriting and updating. S3, initially, the dual-port RAM is empty, and then the write port of the dual-port RAM continuously writes data. After the dual-port RAM is filled with data at addresses 0-1023 for the first time, the read data port of the dual-port RAM reads the first frame of data cached in the RAM in a cyclic increment from address 0 to 1023; S4, the input data rate is lower than the read data rate. When the data read end finishes reading 1024 data, the write data port has not yet completed the update of the 1024 depth data of the dual-port RAM. If the read data port finishes reading 1024 data, the new read address restarts the cycle from 0 as in step S3, then the sequence of the new frame of FFT data will be reversed. If the starting address of the new frame of FFT data read data is the end address of the read data of the previous frame and moves back 205, and then starts the cycle to the previous address of the start address of the current frame read operation, then the data read out of the dual-port RAM is FFT calculated under the read clock.

[0007] In a second aspect, the present invention provides a computer device, including a memory, wherein the memory stores program instructions, and when the program instructions are run, the above-mentioned method for improving FFT refresh rate based on dual-port RAM in FPGA is executed.

[0008] The beneficial effects of the present invention are: The present invention adopts the dual-port RAM inside the FPGA and improves the refresh rate of the FFT by increasing the FFT calculation clock frequency, thereby achieving the improvement of the FFT refresh rate without increasing the FPGA calculation resources. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 It is a schematic diagram of an FPGA dual-port RAM provided by an embodiment of the present invention; Figure 2 This is a schematic diagram of a cyclic writing of a dual-port RAM data writing end provided by an embodiment of the present invention; Figure 3 1 is a schematic diagram of a dual-port RAM data start read operation provided by an embodiment of the present invention; Figure 4 The diagram is a schematic diagram of arbitration of dual-port RAM data read operations provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0010] To make the purpose, technical solution and advantages of the embodiments of the present invention more clear, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention.

[0011] The present invention provides a method for improving the FFT refresh rate based on a dual-port RAM in an FPGA, which specifically includes: In the first step, the FPGA project calls the ipcore of the dual-port RAM to generate a dual-port RAM with a storage depth of 1024; The second step is, Figure 1 As shown, a dual-port RAM is instantiated, the write data end is connected to wr_clk (write clock signal), wr_addr (write address signal), wr_data (write data signal), and the read data end is connected to rd_clk (read clock signal), rd_addr (read address signal), rd_data (read data signal); The third step is Figure 2 As shown, the FPGA program writes the input data from the data write port of the dual-port RAM to the dual-port RAM in sequence under the beat of the wr_clk clock. The wr_addr write address of the RAM increases cyclically from 0 to 1023 (that is, addr0 increases to addr1023), and the write data is also continuously updated cyclically in the write port of the dual-port RAM. The fourth step is Figure 3 As shown in the figure, at the beginning of the program, the dual-port RAM is empty and has no data. At this time, the write port of the dual-port RAM is continuously writing data. After the dual-port RAM is filled with data at addresses 0-1023 for the first time, the read data port of the dual-port RAM reads the first frame of data cached in the RAM in a cyclic increment from address 0 to 1023.

[0012] Step 5: Figure 4 As shown, because the input data rate is lower than the read data rate, when the read data port finishes reading 1024 data, the write data port has not yet completed the update of the 1024-depth data of the dual-port RAM. If the read data port finishes reading 1024 data at this time, the new read address will restart the cycle from 0 as in step 3, and the order of the new frame of FFT data will be reversed. Therefore, after the read data port finishes reading 1024 data, the start address of the new frame of FFT data should be 205 back from the end address of the read data of the previous frame, and then start the cycle to increment to the previous address of the start address of the current frame read operation.

[0013] In the sixth step, the data read out from the dual-port RAM is subjected to FFT calculation under the rd_clk clock, thereby improving the FFT refresh rate.

[0014] The following example is taken as follows: the FFT calculation length is 1024, the wr_clk is 250MHz, and the rd_clk is 312.5MHz. The same applies to other FFT lengths and read / write clock frequencies.

[0015] Input data FFT refresh rate: F = 250MHz / 1024 = 244140.625 frames; Input update time of 1024 data: T1 = 1024 / 250MHz = 4096ns; Output data FFT refresh rate: F = 312.5MHz / 1024 = 305175.78125 frames; Output read 1024 data time: T2 = 1024 / 312.5MHz = 3276.8ns; When the output reads 1024 data, the number of input update data is: T2*250MHz= 819.2; The number of overlapping points that a new frame of read data needs to overlap with the previous frame of data is: P = 1024-819= 205.

[0016] The above is only a preferred embodiment of the present invention. It should be understood that the present invention is not limited to the form disclosed herein, and should not be regarded as excluding other embodiments, but can be used in various other combinations, modifications and environments, and can be modified within the scope of the concept described herein through the above teachings or the technology or knowledge of the relevant field. The changes and modifications made by those skilled in the art shall not deviate from the spirit and scope of the present invention, and shall be within the scope of protection of the claims attached to the present invention.

Claims

1. A method for improving FFT refresh rate based on dual-port RAM in FPGA, characterized in that: include: S1, instantiate a dual-port RAM, connect the write data end with the write clock signal, the write address signal and the write data signal, and connect the read data end with the read clock signal, the read address signal and the read data signal; S2, FPGA writes the input data from the data write port of the dual-port RAM to the dual-port RAM in sequence under the beat of the write clock signal. The write address of the RAM increases cyclically from 0 to 1023. The written data is simultaneously written to the write port in the dual-port RAM for cyclic overwriting and updating. S3, initially, the dual-port RAM is empty, and then data is continuously written to the write port of the dual-port RAM. After the dual-port RAM is filled with data from addresses 0 to 1023 for the first time, the read data port of the dual-port RAM reads the first frame of data cached in the RAM in a cyclic increment from address 0 to 1023; S4, the input data rate is lower than the read data rate. When the data read end finishes reading 1024 data, the write data port has not yet completed the update of the 1024 depth data of the dual-port RAM. If the read data port finishes reading 1024 data, the new read address restarts the cycle from 0 as in step S3, then the sequence of the new frame of FFT data will be reversed. If the starting address of the new frame of FFT data read data is the end address of the read data of the previous frame and moves back 205, and then starts the cycle to the previous address of the start address of the current frame read operation, then the data read out of the dual-port RAM is FFT calculated under the read clock.

2. A computer device comprising a memory, wherein the memory stores program instructions, characterized in that: When the program instructions are executed, the method for improving the FFT refresh rate based on the dual-port RAM in the FPGA as claimed in claim 1 is executed.

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