Layout legalization check and fill cell insertion method and apparatus, device, medium

Abstract

The application provides a layout legalization checking and filler cell insertion method and device, equipment and medium, which are applied to the technical field of integrated circuit design automation, simulate filler cell insertion in the legalization stage of integrated circuit design, detect potential violation problems in advance before actual insertion of the filler cell, eliminate the violation through cell movement, realize mutual coordination between the legalization stage and the filler cell insertion stage, ensure that the physical circuit design does not violate ion implantation layer constraints after the filler cell insertion stage, thereby significantly improving the compliance of the overall design, and effectively shortening the design cycle while meeting the requirements of complex processes.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuit design automation, in particular to a layout legalization checking and fill cell insertion method and device considering ion implant layer constraints in integrated circuit design, equipment and medium. BACKGROUND

[0002] In the physical implementation of integrated circuits, ion implant layer technology plays a crucial role. By dividing different areas on the layout and implanting different doses of ions, the threshold voltage of transistors in each area is set. In particular, in integrated circuit design at 28 nanometers and below, ion implant layer technology is widely used in multi-threshold voltage design to balance power consumption and timing.

[0003] However, as the feature size of integrated circuits continues to shrink, the design rules for implant layers become more stringent. In the legalization stage and fill cell insertion stage, it is necessary to check whether the design meets the minimum width, spacing and other process rules within and between rows.

[0004] Currently, some existing solutions only consider in-row constraint rules, such as references [1-2]. Some consider inter-row constraint rules, but the consideration is not comprehensive, lacking consideration of inter-row minimum spacing constraints, and mostly relying on heuristic algorithms, such as references [3-5]. Some consider more comprehensive rules, but are based on simple examples and do not consider macro blocks and other issues on industrial examples, resulting in final designs that cannot meet high performance and high reliability requirements, such as reference [6].

[0005] In addition, existing solutions often only consider constraints during legalization and do not consider the requirements of fill cell insertion.

[0006] Therefore, existing practices cannot fully comply with in-row and inter-row constraint rules, resulting in a failure to meet the needs of process nodes shrinking to 28nm and below.

[0007] Therefore, a new integrated circuit design method is needed.

[0008] References:

[0009] [1] Kahng AB, Lee H. Minimum implant area-aware gate sizing and placement [C] / / Proceedings of the 24th Edition of the Great Lakes Symposium on VLSI. 2014: 57-62.

[0010] [2]Tseng K H,Chang Y W,Liu C C C.Minimum-implant-area-aware detailedplacement with spacing constraints[C] / / Proceedings of the 53rd Annual DesignAutomation Conference.2016:1-6.

[0011] [3]Han K,Kahng AB,Lee H.Scalabledetailed placement legalization forcomplex sub-14nm constraints[C] / / 2015IEEE / ACM International Conference onComputer-Aided Design(ICCAD).IEEE,2015:867-873.

[0012] [4]Mak W K,Kuo W S,Zhang S H,et al.Minimum implant area-awareplacement and threshold voltage refinement[J].IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,2017,36(7):1103-1112.

[0013] [5]Chen G,Zeng Z,Zhu B,et al.Mixed-cell-height Placement withMinimum-Implant-Area and Drain-to-Drain Abutment Constraints[C] / / 2023 60thACM / IEEE Design Automation Conference(DAC).IEEE,2023:1-6.

[0014] [6]Zou P, Chen G, Lin Z, et al. Toward Optimal Filler Cell Insertion with Complex Implant Layer Constraints[C] / / 2023 60th ACM / IEEE Design Automation Conference (DAC). IEEE, 2023:1-6. Summary of the Invention

[0015] In view of this, the embodiments of this specification provide a layout legalization check and filling unit insertion method and device, equipment, and medium. By considering the optimal insertion strategy of the filling unit in advance in the legalization stage, combined with the lookup table generated according to the constraint form of the process node in the preprocessing stage, violations in the design can be quickly and accurately identified and repaired, which not only speeds up the speed of violation detection and repair, but also ensures that the design meets the strict process requirements of the ion implantation layer, thereby achieving comprehensive legalization of the layout design.

[0016] The embodiments of this specification provide the following technical solutions:

[0017] The embodiments of this specification provide a method for checking the legality of an integrated circuit layout, including:

[0018] Generate a corresponding lookup table from the circuit design layout through dynamic programming based on the process nodes and ion implantation layer constraints; wherein the ion implantation layer constraints include at least: a minimum width constraint within a row, a minimum spacing constraint within a row, a minimum width constraint between rows, and a minimum spacing constraint between rows; and the lookup table includes: an inference mode lookup table and a violation mode lookup table;

[0019] Perform the following traversal on each unit to be laid out and its placement position to obtain the legalized layout result:

[0020] Try to place the current unit to be placed at the currently specified placement position, then generate a current processing window based on the preset optimal size of the recognition window with the current unit to be placed as the center, and give an ion implantation layer in the current processing window. Then, perform pre-filling reasoning of the ion implantation layer on the blank sites in the current processing window according to the inference pattern lookup table until no further reasoning can be done. Finally, determine whether there is a violation in the current processing window according to the violation pattern lookup table, and determine the corresponding unit to be placed and placement position for the next round of traversal based on the violation situation and the placement situation of other units that have been placed.

[0021] The cells to be laid out include logic cells and filling cells to be laid out.

[0022] This specification also provides a method for inserting a filler cell in an integrated circuit layout, comprising:

[0023] Based on any one of the integrated circuit layout legalization checking methods, a filling position corresponding to the filling unit is obtained;

[0024] Performing a filling process at the filling position;

[0025] The illegal pattern lookup table is used to perform a legality check on the filled filling unit.

[0026] The embodiment of this specification also provides an integrated circuit layout legalization checking device, the integrated circuit layout legalization checking device comprising: a lookup table generation module and a layout generation module;

[0027] The lookup table generation module is configured to generate a corresponding lookup table from the circuit design layout through dynamic programming based on the process nodes and the ion implantation layer constraints; wherein the ion implantation layer constraints include at least: a minimum width constraint within a row, a minimum spacing constraint within a row, a minimum width constraint between rows, and a minimum spacing constraint between rows; and the lookup table includes: an inference mode lookup table and a violation mode lookup table;

[0028] The layout generation module is used to perform the following traversal on each unit to be laid out and placement position to obtain a legalized layout result:

[0029] Try to place the current unit to be placed at the currently specified placement position, then generate a current processing window based on the preset optimal size of the recognition window with the current unit to be placed as the center, and give an ion implantation layer in the current processing window. Then, perform pre-filling reasoning of the ion implantation layer on the blank sites in the current processing window according to the inference pattern lookup table until no further reasoning can be done. Finally, determine whether there is a violation in the current processing window according to the violation pattern lookup table, and determine the corresponding unit to be placed and placement position for the next round of traversal based on the violation situation and the placement situation of other units that have been placed.

[0030] The cells to be laid out include logic cells and filling cells to be laid out.

[0031] An embodiment of this specification further provides an electronic device, including:

[0032] At least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to execute: any one of the integrated circuit layout legalization checking methods or the integrated circuit layout filling unit insertion methods.

[0033] An embodiment of this specification also provides a computer storage medium, which stores computer-executable instructions. When the computer-executable instructions are executed by a processor, they perform: any one of the integrated circuit layout legalization checking methods or the integrated circuit layout filling unit insertion method.

[0034] Compared with the prior art, the at least one technical solution adopted in the embodiments of this specification can achieve the following beneficial effects:

[0035] This application simulates the insertion of filling cells in the legalization stage of integrated circuit design, detects potential violations in advance before the actual insertion of the filling cells, and eliminates violations by moving the cells, thereby achieving mutual coordination between the legalization stage and the filling cell insertion stage, ensuring that after the filling cell insertion stage, the physical circuit design does not violate the ion implantation layer constraints, thereby significantly improving the compliance of the overall design, allowing the layout design to meet complex process requirements while effectively shortening the design cycle. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0037] Figure 1 This is a schematic diagram of the effect of inserting a filling unit in this application;

[0038] Figure 2 It is a schematic diagram of the reasoning model of the lookup table content in this application;

[0039] Figure 3 This is a schematic diagram of the violation pattern of the lookup table content in this application;

[0040] Figure 4 It is a flow chart of the integrated circuit layout legalization checking method in this application. DETAILED DESCRIPTION

[0041] The embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0042] The following describes the embodiments of the present application through specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The present application can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that, in the absence of conflict, the features in the following embodiments and embodiments can be combined with each other. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without making creative work are within the scope of protection of this application.

[0043] It should be noted that various aspects of the embodiments within the scope of the appended claims are described below. It should be apparent that the aspects described herein can be embodied in a wide variety of forms, and any specific structure and / or function described herein is merely illustrative. Based on this application, it should be understood by those skilled in the art that an aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number and aspect described herein can be used to implement an apparatus and / or practice a method. In addition, other structures and / or functionalities other than one or more of the aspects described herein can be used to implement this apparatus and / or practice this method.

[0044] It should also be noted that the illustrations provided in the following embodiments are only schematic illustrations of the basic concept of the present application. The illustrations only show components related to the present application and are not drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component can be changed at will, and the component layout type may also be more complicated.

[0045] Additionally, in the following description, specific details are provided to provide a thorough understanding of the examples, however, one skilled in the art will appreciate that the examples can be practiced without these specific details.

[0046] In the physical implementation of integrated circuits, the design of the ion implantation layer plays a crucial role in determining the precise setting of the transistor's threshold voltage, directly impacting its switching speed, power consumption, and performance. With technological advancements, feature sizes continue to decrease, especially at process nodes of 28nm and below. The design rules for the implantation layer have become increasingly stringent, placing higher demands on violation detection during the legalization and cell insertion stages. Designs must be checked for compliance with a range of process constraints, including minimum widths and spacing within and between rows.

[0047] However, existing mainstream legalization violation detection methods have some significant shortcomings. Some methods only consider intra-row constraints and ignore the importance of inter-row constraints. This leads to the need for extensive adjustments in subsequent design stages, which not only increases design cycle time and costs but also prevents designs from meeting the complex requirements of new process nodes.

[0048] Although other methods take into account inter-row constraints, their coverage is not comprehensive, especially the lack of consideration of the minimum spacing constraints between rows. They also rely on heuristic algorithms. As process nodes shrink and design scale increases, they are difficult to adapt to the increase in design scale and the complexity of constraints. They cannot guarantee to find the optimal solution or an effective solution in complex situations, thus affecting the overall performance and reliability of the design.

[0049] Some approaches, while theoretically comprehensive, rely solely on simple examples and fail to fully consider issues like macroblocks in industrial applications, resulting in designs that fail to meet high-performance and high-reliability requirements. Furthermore, existing approaches often focus solely on legalization constraints while ignoring the requirements during the padding insertion phase. This leads to the need for redesign and verification when padding cell issues are discovered later, increasing the difficulty and risk of corrections and prolonging the overall design cycle.

[0050] In view of this, the inventors discovered through research and improvement exploration that the existing legalization violation detection method does not fully consider the complexity of integrated circuit design, especially the neglect of inter-row constraints and fill cell insertion requirements, resulting in the final design being unable to meet the requirements of high performance and high reliability.

[0051] Based on this, the embodiment of this specification proposes a method for checking the legalization of integrated circuit layout: the overall idea is: through the lookup table generated in the preprocessing stage, the need for filling unit insertion is considered simultaneously in the legalization stage (such as Figure 1 As shown in the figure, the potential placement position of each unit is checked for compliance, and a lookup table is used to effectively identify violations and adjust positions. Through an iterative process, it is ensured that all units meet the process constraints, which significantly improves the compliance of the overall design. This allows the layout design to meet complex process requirements while effectively shortening the design cycle and reducing costs.

[0052] The following describes the technical solutions provided by various embodiments of the present application in conjunction with the accompanying drawings.

[0053] like Figure 4 As shown, the embodiment of this specification provides an integrated circuit layout legalization checking method, comprising the following steps:

[0054] Based on the process nodes and ion implantation layer constraints, a corresponding lookup table is generated from the circuit design layout through dynamic programming; wherein the ion implantation layer constraints include at least: minimum width constraint within a row, minimum spacing constraint within a row, minimum width constraint between rows, and minimum spacing constraint between rows; the lookup table includes: an inference mode lookup table and a violation mode lookup table.

[0055] Specifically, in the pre-processing stage of integrated circuit design, according to the legalized circuit design layout and the ion implantation layer constraints corresponding to the process node, a lookup table is generated, including the inference mode lookup table (see Figure 2 ) and the violation pattern lookup table (see Figure 3 ), generates the optimal size of the recognition window, ensuring that when checking whether the cell placement is compliant, the window will not be too small to miss important design rules, nor too large to introduce unnecessary complexity.

[0056] Proper window size helps ensure that the ion implantation layer information within the window is sufficient for comprehensive compliance checking, including minimum width and spacing constraints within and between rows.

[0057] In combination with the above embodiment, the following traversal is performed on each unit to be laid out and the placement position to obtain a legalized layout result:

[0058] Try to place the current unit to be placed at the currently specified placement position, then generate a current processing window based on the preset optimal size of the recognition window with the current unit to be placed as the center, and give an ion implantation layer in the current processing window. Then, perform pre-filling reasoning of the ion implantation layer on the blank sites in the current processing window according to the inference pattern lookup table until no further reasoning can be done. Finally, determine whether there is a violation in the current processing window according to the violation pattern lookup table, and determine the position of the unit to be placed corresponding to the next round of traversal based on the violation situation and the placement situation of other units that have been placed.

[0059] The cells to be laid out include logic cells and filling cells to be laid out.

[0060] Specifically, when the legalization engine attempts to place a unit in a certain position, it cuts out a local area from the layout according to the optimal size of the recognition window to form the current processing window. Within the current processing window, the ion implantation layer information of all relevant units is collected, including the unit type, ion implantation dose, implantation depth, etc. The ion implantation layer information of the current processing window is passed as input data to the violation identifier.

[0061] Based on the ion implantation layer information provided by the legalization engine, the violation identifier fills in the blank sites in the current processing window according to the inference pattern lookup table generated by the preprocessing until no further inference can be made. After completing the filling in inference, the violation identifier checks whether there are any violations in the current processing window according to the violation pattern lookup table, such as whether the current placement is compliant, or what violations exist, and feeds back the results of the compliance analysis to the legalization engine.

[0062] The legalization engine determines whether the current position is legal based on the feedback from the ion implantation layer violation identifier. If it is legal, the legalization engine will continue to process the next unit. If it is illegal, the legalization engine will search for the next possible placement position of the current unit and iterate the legalization process until all units are legally placed and the entire layout design meets the constraints of all ion implantation layers.

[0063] After the pre-placement attempts of all cells are completed and the entire layout meets all process constraints in the simulation check, the legalization engine will generate a preliminary legalized layout design.

[0064] It should be noted that the legalization stage provides a layout framework that meets the process requirements for the subsequent filling cell insertion stage. During the filling cell insertion stage, necessary adjustments and confirmations are made to the pre-placed cells to ensure that the final layout design not only meets the constraints of the ion implantation layer, but also optimizes the layout of the filling cells, significantly improving the compliance of the overall design and effectively shortening the design cycle while ensuring that the design meets strict requirements.

[0065] In some embodiments, when generating a lookup table, the assignment of each unit site is first determined based on the pattern size, and then it is determined based on the assignment of the unit site whether the unit site is assigned a pattern of a specified type. If so, the unit site is recorded in a first pattern set, wherein the unit sites in the first pattern set do not require reasoning and only need to determine whether the pattern is violated;

[0066] The allocation of each unit site is determined by the following formula: ImplantType*2+1, where ImplantType represents the number of implant types of the process node; multiplying by 2 indicates allocation as a logic unit or fill unit; adding 1 indicates allocation as a macroblock or other non-placeable area.

[0067] Specifically, according to the provided ion implantation layer constraints, the mode size can be determined. In order to comprehensively consider all possible process constraints and design options, there are ImplantType*2+1 assignment possibilities for each cell site, where ImplantType represents the number of implant types for the process node, multiplied by 2 to represent that each cell site can be a logical cell or a fill cell, increasing the flexibility of the design and allowing optimization while meeting process constraints; plus 1 to represent the case of considering macro blocks or other non-placable areas in addition to logical cells and fill cells, ensuring that these special cases are included in the design.

[0068] Reasonable assignment can optimize the efficiency of the algorithm, so as to ensure that the violation detection and layout adjustment are carried out quickly and accurately during legalization, and the need for later correction is reduced.

[0069] In some embodiments, the mode set corresponding to each cell site is determined according to the number of assignments of each cell site and the mode size, so that in the dynamic programming, the mode corresponding to the cell site is divided into the corresponding mode set according to the assignment of the cell site;

[0070] Wherein, the total number of mode sets is represented by the formula: N=M+1, where N>=1, and M represents the corresponding mode size;

[0071] The first mode set is used to represent that each cell site is assigned a specific type of mode; the second mode set is used to represent that only one cell site is not assigned a mode; and the Nth mode set is used to represent that N-1 cell sites are not assigned a mode.

[0072] Specifically, the process parameters determine the size of the mode, and each mode size and the number of assignments of each cell site determine the mode set of the cell site.

[0073] For example, under a certain process node, two mode sizes of 2 rows*5 columns and 3 rows*3 columns are corresponding, and under each mode size, the mode set is determined according to the number of assignments of each cell site. 2 rows*5 columns will have a first mode set to an eleventh mode set, and 3 rows*3 columns will have another first mode set to a tenth mode set, as shown in Figure 2 The mode has four cell sites not assigned, so the mode is divided into the fifth mode set. By processing each mode set specifically, unnecessary calculation can be reduced, and the accuracy and efficiency of violation detection are improved. Moreover, by generating a comprehensive lookup table, fast and accurate compliance evaluation of cell placement is supported in the legalization stage, and the automatic flow of the entire integrated circuit design is optimized.

[0074] In some embodiments, dynamic programming is used to start from the first mode set and sequentially detect each mode set until the Nth mode set.

[0075] For the first pattern set, determining whether a pattern in the first pattern set violates a rule, and if so, adding the pattern to the lookup table and updating the lookup table;

[0076] For the second pattern set, according to the process node and the ion implantation layer constraints, an unassigned unit site is assigned through dynamic programming, converted into a pattern in the first pattern set, and the lookup table is updated according to the converted situation;

[0077] For the Nth pattern set, dynamic programming will allocate one of the unassigned unit sites to obtain the pattern in the N-1th pattern set, and update the lookup table according to the conversion result in the N-1th pattern set.

[0078] Specifically, in the dynamic programming algorithm, the first pattern set P1 to which each unit site is assigned is first detected. Since each site in this set is assigned a specific type (corresponding to each site being occupied), this type of pattern does not require reasoning, and it can be directly determined whether the pattern is in violation.

[0079] Then, when a second pattern set P2 is detected in which one unit site is not assigned, the unassigned unit site can be assigned in the pattern p of the set to be converted into a pattern in the set P1.

[0080] Afterwards, for the third pattern set P3 with two unassigned unit sites, a pattern in the set P2 can also be obtained by transforming one of the unassigned unit sites, and the subsequent process is the same as the above.

[0081] During implementation, for example, if a pattern has four unassigned unit sites, the pattern is divided into the fifth pattern set. Subsequently, an allocation attempt is made for one of the unassigned unit sites. If a unit allocation is determined for one of the unassigned sites, the pattern is converted into a pattern in the fourth pattern set, and the lookup table is updated according to the conversion result in the fourth pattern set to support subsequent design decisions and compliance checks.

[0082] It should be noted that the generated violation patterns and inference patterns will eventually be organized uniformly according to pattern size.

[0083] In some embodiments, when converting a pattern in the Nth pattern set into a pattern in the N-1th pattern set, the situation after the unassigned unit sites are assigned is determined:

[0084] If the allocation method of any unassigned unit site leads to a violation mode, the current mode is considered to be a violation mode and is added to the violation mode lookup table;

[0085] If there is only one allocation method for the unassigned sites that can transform the current pattern into a non-violating pattern in the N-1th pattern set, then establish an inference pattern from the current pattern to the non-violating pattern, and add the current pattern to the inference pattern lookup table;

[0086] If there are two or more cases where the unassigned sites can be converted into non-violating patterns in the N-1th pattern set after assignment, the current pattern is not added to the lookup table.

[0087] Specifically, taking the conversion of a pattern in the second pattern set into a pattern in the first pattern set as an example, in implementation, when a pattern set P2 with an unassigned unit site is detected, the unassigned unit site can be allocated in the pattern p of the set to convert it into a pattern in the set P1. There are three possibilities for this process:

[0088] (1) If the corresponding transformed pattern is a violation pattern in set P1 regardless of how the site is assigned, then the pattern p is also a violation pattern and is added to the lookup table;

[0089] (2) If there is only one transformation that can transform pattern p into a non-violating pattern in set P1, then a reasoning pattern from pattern p to the non-violating pattern can be established and added to the lookup table;

[0090] (3) If there are two or more transformations that can transform pattern p into a non-violating pattern in set P1, then it is not added to the lookup table.

[0091] In some embodiments, performing pre-filling reasoning of the ion implantation layer on blank sites within the current processing window according to the reasoning pattern lookup table until no further reasoning is possible includes:

[0092] According to the inference pattern lookup table, determining whether there is a blank site in the current processing window that must be assigned a specific ion implantation type;

[0093] If there is, the blank site is marked; otherwise, the filling reasoning ends and the violation detection mode is entered.

[0094] Specifically, during the legalization process, the legalization engine presents a cell and a placement location, querying whether the placement of the cell at that location is legal. First, centered on the current cell, the legalization engine generates a local window of the ion implantation layer based on the current placement. Then, based on the ion implantation layer in this local window, the violation identifier combines the inference patterns in the lookup table to determine whether any empty sites must be assigned a specific ion implantation type. If no new fills are found, the remaining empty sites are uncertain, and the violation pattern can be used to identify any violations in the current window.

[0095] In combination with the above embodiment, the violation situation is fed back to the legalization engine, and the legalization engine determines the cells and placement positions to be provided in the next round based on the violation situation and the placement of other cells. The process is repeated until all cells are traversed, and the legalization considering the ion implantation layer constraints is completed.

[0096] This application considers the insertion of filler units in advance during the legalization stage (e.g. Figure 1 As shown in Figure 2, the algorithm combines logic cells and filler cells to determine if there are any violations in the layout. Specifically, it determines whether there are any legal filler cell insertion schemes during the legalization phase. Combined with the legalization engine, this algorithm can quickly detect violations corresponding to the example injection layer constraints and provide feedback to the legalization engine for remediation.

[0097] Based on the same inventive concept, the present application provides a method for inserting a fill cell in an integrated circuit layout, comprising:

[0098] Based on any one of the integrated circuit layout legalization checking methods, a filling position corresponding to the filling unit is obtained;

[0099] Performing a filling process at the filling position;

[0100] The illegal pattern lookup table is used to perform a legality check on the filled filling unit.

[0101] Based on the same inventive concept, the present application also provides an integrated circuit layout legalization checking device, the integrated circuit layout legalization checking device comprising: a lookup table generation module and a layout generation module;

[0102] The lookup table generation module is configured to generate a corresponding lookup table from the circuit design layout through dynamic programming based on the process nodes and the ion implantation layer constraints; wherein the ion implantation layer constraints include at least: a minimum width constraint within a row, a minimum spacing constraint within a row, a minimum width constraint between rows, and a minimum spacing constraint between rows; and the lookup table includes: an inference mode lookup table and a violation mode lookup table;

[0103] The layout generation module is used to perform the following traversal on each unit to be laid out and placement position to obtain a legalized layout result:

[0104] placing the current to-be-laid-out unit at the current specified placement position, then generating a current processing window according to a preset recognition window optimal size with the current to-be-laid-out unit as a center, and giving an ion implantation layer in the current processing window, then performing the pre-filling inference of the ion implantation layer on the blank site in the current processing window according to the inference mode lookup table until no further inference can be performed, and finally judging whether the current processing window has a violation according to the violation mode lookup table, and determining the corresponding to-be-laid-out unit and placement position for the next round of iteration according to the violation and the placement situation of other units that have been placed.

[0105] The to-be-laid-out unit includes a logic unit to be laid out and a padding unit.

[0106] Based on the same inventive concept, the present application also provides an electronic device based on the integrated circuit layout layout legalization checking method or the electronic device based on the integrated circuit layout layout padding unit insertion method, and the electronic device includes a processor, a memory and a computer program.

[0107] The memory is used to store the computer program, and the memory can also be a flash memory. The computer program is, for example, an application program, a functional module or the like for implementing the above method.

[0108] The processor is used to execute the computer program stored in the memory to implement each step of the device in the above method. For details, refer to the related description in the above method embodiment.

[0109] Optionally, the memory can be independent or integrated with the processor.

[0110] When the memory is a device independent of the processor, the device can further include:

[0111] A bus is used to connect the memory and the processor.

[0112] Based on the same inventive concept, the present application also provides a computer storage medium, which stores computer executable instructions. When the computer executable instructions are executed by a processor, the integrated circuit layout layout legalization checking method or the integrated circuit layout layout padding unit insertion method as described in any embodiment of the present application is executed.

[0113] It should be noted that the computer storage medium can include but is not limited to a portable disc, a hard disk, a random access memory, a read-only memory, an erasable programmable read-only memory, an optical storage device, a magnetic storage device or any suitable combination of the above.

[0114] In possible implementation manners, the present application can also provide a program product in the form of data processing, which comprises program codes for causing a terminal device to execute several steps in the method of any one of the preceding embodiments when the program product is run on the terminal device.

[0115] The program code for executing the present application can be written in any combination of one or more programming languages, and can be executed entirely on the user device, partially on the user device, as a stand-alone software package, partially on the user device and partially on a remote device, or entirely on a remote device.

[0116] The present application provides an ion implantation layer violation detection algorithm under advanced integrated circuit process nodes (28nm process and below), to consider the insertion of fill cells in the legalization stage of layout, detect corresponding violations in advance, so that the violations can be eliminated by cell movement. By mutual coordination with the fill cell insertion stage, the algorithm can ensure that the physical circuit design after the fill cell insertion stage does not violate the ion implantation layer constraint.

[0117] In the specification, the same or similar parts among various embodiments can be referred to each other, and each embodiment focuses on the difference from other embodiments. Especially, for the embodiments described later, the description is relatively simple, and the relevant parts can be referred to the part of the foregoing embodiments.

[0118] The above merely describes the specific embodiments of the present application, but the protection scope of the present application is not limited to this. Any person skilled in the art can easily think of changes or replacements within the technical range disclosed by the present application, which should be covered in the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A method for checking the legality of an integrated circuit layout, characterized in that: include: Generate a corresponding lookup table from the circuit design layout through dynamic programming based on the process nodes and ion implantation layer constraints; wherein the ion implantation layer constraints include at least: a minimum width constraint within a row, a minimum spacing constraint within a row, a minimum width constraint between rows, and a minimum spacing constraint between rows; and the lookup table includes: an inference mode lookup table and a violation mode lookup table; When generating the lookup table, the allocation of each unit site is first determined according to the pattern size, and then it is determined whether each unit site is assigned a specified type according to the allocation of the unit sites. If so, the pattern is recorded in the first pattern set, wherein the patterns in the first pattern set do not need to be inferred and only need to determine whether the pattern is in violation; Wherein, the pattern size is determined by process parameters; The allocation of each unit site is determined by the following formula: ImplantType*2+1, ImplantType indicates the number of implant types of the process node; multiplying by 2 indicates allocation to logic cells or fill cells; adding 1 indicates allocation to macro blocks or other non-placeable areas; Perform the following traversal on each unit to be laid out and its placement position to obtain the legalized layout result: Try to place the current unit to be placed at the currently specified placement position, then generate a current processing window based on the preset optimal size of the recognition window with the current unit to be placed as the center, and give an ion implantation layer in the current processing window. Then, perform pre-filling reasoning of the ion implantation layer on the blank sites in the current processing window according to the inference pattern lookup table until no further reasoning can be done. Finally, determine whether there is a violation in the current processing window according to the violation pattern lookup table, and determine the corresponding unit to be placed and placement position for the next round of traversal based on the violation situation and the placement situation of other units that have been placed. The cells to be laid out include logic cells and filling cells to be laid out; The pre-filling reasoning of the ion implantation layer is performed on the blank sites in the current processing window according to the reasoning pattern lookup table until no further reasoning is possible, comprising: According to the inference pattern lookup table, determining whether there is a blank site in the current processing window that must be assigned a specific ion implantation type; If there is, the blank site is marked; otherwise, the filling reasoning ends and the violation detection mode is entered.

2. The integrated circuit layout legalization checking method according to claim 1, characterized in that: Determining a pattern set corresponding to the pattern according to the number of allocations and pattern size of each unit site, so as to divide the patterns corresponding to the unit sites into corresponding pattern sets according to the allocation of the unit sites through dynamic programming; The total number of pattern sets is expressed as: N=M+1, where N>=1 and M represents the corresponding pattern size. The first pattern set is used to characterize that each unit site is assigned a specific type of pattern; the second pattern set is used to characterize patterns with only one unit site unassigned; and the Nth pattern set is used to characterize patterns with N-1 unit sites unassigned.

3. The integrated circuit layout legalization checking method according to claim 2, characterized in that: Using dynamic programming, starting from the first pattern set, each pattern set is tested in turn until the Nth pattern set; For the first pattern set, determining whether a pattern in the first pattern set violates a rule, and if so, adding the pattern to the lookup table and updating the lookup table; For the second pattern set, according to the process node and the ion implantation layer constraints, an unassigned unit site is assigned through dynamic programming, converted into a pattern in the first pattern set, and the lookup table is updated according to the converted situation; For the Nth pattern set, dynamic programming will allocate one of the unassigned unit sites to obtain the pattern in the N-1th pattern set, and update the lookup table according to the conversion result in the N-1th pattern set.

4. The integrated circuit layout legalization checking method according to claim 3, characterized in that: When converting the pattern in the Nth pattern set into the pattern in the N-1th pattern set, the situation after the unassigned unit sites are assigned is judged: If the allocation method of any unassigned unit site leads to a violation mode, the current mode is considered to be a violation mode and is added to the violation mode lookup table; If there is only one allocation method for the unassigned sites that can transform the current pattern into a non-violating pattern in the N-1th pattern set, then establish an inference pattern from the current pattern to the non-violating pattern, and add the current pattern to the inference pattern lookup table; If there are two or more cases where the unassigned sites can be converted into non-violating patterns in the N-1th pattern set after assignment, the current pattern is not added to the lookup table.

5. A method for inserting a filling cell in an integrated circuit layout, characterized in that: include: Based on the integrated circuit layout legalization checking method according to any one of claims 1 to 4, obtaining a filling position corresponding to the filling unit; Performing a filling process at the filling position; The illegal pattern lookup table is used to perform a legality check on the filled filling unit.

6. An integrated circuit layout legalization checking device, characterized in that: The integrated circuit layout legalization checking device includes: a lookup table generation module and a layout generation module; The lookup table generation module is configured to generate a corresponding lookup table from the circuit design layout through dynamic programming based on the process nodes and the ion implantation layer constraints; wherein the ion implantation layer constraints include at least: a minimum width constraint within a row, a minimum spacing constraint within a row, a minimum width constraint between rows, and a minimum spacing constraint between rows; and the lookup table includes: an inference mode lookup table and a violation mode lookup table; When generating the lookup table, the allocation of each unit site is first determined according to the pattern size, and then it is determined whether each unit site is assigned a specified type according to the allocation of the unit sites. If so, the pattern is recorded in the first pattern set, wherein the patterns in the first pattern set do not need to be inferred and only need to determine whether the pattern is in violation; Wherein, the pattern size is determined by process parameters; The allocation of each unit site is determined by the following formula: ImplantType*2+1, ImplantType indicates the number of implant types of the process node; multiplying by 2 indicates allocation to logic cells or fill cells; adding 1 indicates allocation to macro blocks or other non-placeable areas; The layout generation module is used to perform the following traversal on each unit to be laid out and placement position to obtain a legalized layout result: Try to place the current unit to be placed at the currently specified placement position, then generate a current processing window based on the preset optimal size of the recognition window with the current unit to be placed as the center, and give an ion implantation layer in the current processing window. Then, perform pre-filling reasoning of the ion implantation layer on the blank sites in the current processing window according to the inference pattern lookup table until no further reasoning can be done. Finally, determine whether there is a violation in the current processing window according to the violation pattern lookup table, and determine the corresponding unit to be placed and placement position for the next round of traversal based on the violation situation and the placement situation of other units that have been placed. The cells to be laid out include logic cells and filling cells to be laid out; The pre-filling reasoning of the ion implantation layer is performed on the blank sites in the current processing window according to the reasoning pattern lookup table until no further reasoning is possible, comprising: According to the inference pattern lookup table, determining whether there is a blank site in the current processing window that must be assigned a specific ion implantation type; If there is, the blank site is marked; otherwise, the filling reasoning ends and the violation detection mode is entered.

7. An electronic device, characterized in that: include: at least one processor; And, a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to execute: the integrated circuit layout legalization checking method according to any one of claims 1 to 4, or the integrated circuit layout filling unit insertion method according to claim 5.

8. A computer storage medium, characterized in that The computer storage medium stores computer executable instructions, and when the computer executable instructions are executed by the processor, they perform: the integrated circuit layout legalization checking method according to any one of claims 1 to 4, or the integrated circuit layout filling unit insertion method according to claim 5.

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