Flash memory controller, flash memory device and corresponding method

Abstract

The invention relates to a flash memory controller, a flash memory device and a corresponding method. The method includes: using an error correction code circuit to perform an error correction code operation on data accessed from a storage block of a flash memory chip of the flash memory device to generate an error correction code result; when it is judged that the error correction code result indicates that the error correction code fails, a fetching task corresponding to the storage block is temporarily stored in the fixed buffer; and controlling a voltage generator of the flash memory device to control at least one address decoder of the flash memory device to re-access the flash memory device according to at least one threshold voltage level of the voltage generator through the specific communication interface until the temporarily stored access task has been temporarily stored for a specific preset time The storage block of the flash memory chip is provided.

Description

Technical Field

[0001] The present invention relates to a flash memory access mechanism, and more particularly to a flash memory controller, a flash memory device and a corresponding method. Background Art

[0002] Generally speaking, if a storage block or page of a conventional NAND flash memory has not been read / written for a long period of time, then the fail bit count (FBC) when reading the data of the storage block or page will increase significantly, so the bit error rate of reading the data of the storage block or page will be quite high. In another case, assuming that a storage block has not been accessed after reading it, and the bit error of the error correction code when accessing the storage block gradually increases, it means that the threshold voltage distribution of the storage block has shifted. Summary of the invention

[0003] Therefore, one of the objectives of the present invention is to provide a flash memory controller, a flash memory device and a corresponding method to solve the above-mentioned problem.

[0004] According to an embodiment of the present invention, a flash memory device is disclosed. The flash memory device is used in a storage device and is coupled to a flash memory controller of the storage device through a specific communication interface, and the flash memory device includes an input / output control circuit, a command register, an address register, a storage cell array, at least one address decoder, a voltage generator, a control circuit and an error correction code circuit. The input / output control circuit is coupled to the flash memory controller through the specific communication interface. The command register is coupled to the input / output control circuit and is used to cache a command information issued from the flash memory controller and transmitted through the input / output control circuit. The address register is coupled to the input / output control circuit and is used to buffer an address information sent by the flash memory controller and transmitted through the input / output control circuit. The storage cell array has a plurality of flash memory chips, each flash memory chip has a plurality of flash memory planes, each flash memory plane has a plurality of storage blocks, and each storage block has a plurality of storage pages. At least one address decoder is coupled to the storage cell array and the data register. The voltage generator is coupled to the at least one address decoder and the storage cell array, and is used to generate and output at least one critical voltage level to the at least one address decoder. The control circuit is coupled to the address register, the command register, the voltage generator and the storage cell array, and is used to control the voltage generator to control the at least one address decoder to access a storage block of a flash memory chip of the storage cell array according to the at least one critical voltage level. The error correction code circuit is coupled between the storage cell array and the input / output control circuit, and is used to perform an error correction code operation on a data of the storage block of the accessed flash memory chip, and generate an error correction code result to the control circuit. When the control circuit determines that the error correction code result indicates an error correction code failure, the control circuit temporarily stores an access task corresponding to the storage block in a specific buffer in the storage cell array, and the control circuit does not control the voltage generator to control the at least one address decoder to access the storage block of the flash memory chip again according to the at least one critical voltage level until the temporarily stored access task has been temporarily stored for a specific preset time.

[0005] According to an embodiment of the present invention, a flash memory controller is disclosed. The flash memory controller is used in a storage device and is coupled to a flash memory device of the storage device through a specific communication interface, and the flash memory controller includes an input / output circuit and a processing circuit, and the processing circuit includes a processor, an error correction code circuit and a specific buffer. The input / output circuit is coupled to the flash memory device through the specific communication interface. The processor is used to control the input / output circuit to send a command information to the flash memory device through the specific communication interface, and control the input / output circuit to send an address information to the flash memory device through the specific communication interface. The error correction code circuit is coupled to the processor to perform an error correction code operation on a data accessed from a storage block of a flash memory chip of the flash memory device to generate an error correction code result to the processor. The specific buffer is coupled to the processor. When the processor determines that the ECC result indicates an ECC failure, the processor temporarily stores an access task corresponding to the storage block in the specific buffer, and only after the temporarily stored access task has been temporarily stored for a specific preset time, the processor controls the control circuit of the flash memory device through the specific communication interface to control the voltage generator of the flash memory device to control at least one address decoder of the flash memory device to access the storage block of the flash memory chip again according to at least one critical voltage level of the voltage generator of the flash memory device.

[0006] According to an embodiment of the present invention, a method for use in a flash memory device is disclosed. The flash memory device is used in a storage device and is coupled to a flash memory controller of the storage device through a specific communication interface, and the method includes: providing an input / output control circuit, coupled to the flash memory controller through the specific communication interface; providing a command register, coupled to the input / output control circuit, using the command register to cache a command information issued from the flash memory controller and transmitted through the input / output control circuit; providing an address register, coupled to the input / output control circuit, using the address register to cache an address information sent from the flash memory controller and transmitted through the input / output control circuit; providing a storage cell array having a plurality of flash memory chips, each flash memory chip having a plurality of flash memory planes, each flash memory plane having a plurality of storage blocks, and each storage block having a plurality of storage pages; providing at least one address decoder, coupling the storage cell array and the data register; providing a voltage generator, coupled to the at least one ground The invention relates to an address decoder and a storage cell array, using the voltage generator to generate and output at least one critical voltage level to the at least one address decoder; providing a control circuit to control the voltage generator to control the at least one address decoder to access a storage block of a flash memory chip of the storage cell array according to the at least one critical voltage level; providing an error correction code circuit, coupled between the storage cell array and the input / output control circuit, using the error correction code circuit to perform an error correction code operation on a data of the storage block of the accessed flash memory chip to generate an error correction code result to the control circuit; when it is determined that the error correction code result indicates an error correction code failure, temporarily storing an access task corresponding to the storage block in a specific buffer in the storage cell array; and controlling the voltage generator to control the at least one address decoder to access the storage block of the flash memory again according to the at least one critical voltage level until the temporarily stored access task has been temporarily stored for a specific preset time.

[0007] According to an embodiment of the present invention, a method for a flash memory controller is disclosed. The flash memory controller is used in a storage device and is coupled to a flash memory device of the storage device through a specific communication interface, and the method includes: providing an input / output circuit, coupled to the flash memory device through the specific communication interface; controlling the input / output circuit to send a command information to the flash memory device through the specific communication interface; controlling the input / output circuit to send an address information to the flash memory device through the specific communication interface; providing an error correction code circuit for correcting the error information stored in a storage block of a flash memory chip of the flash memory device. The invention discloses a flash memory device for performing an error correction code operation on a data to generate an error correction code result; providing a specific buffer; when it is determined that the error correction code result indicates an error correction code failure, temporarily storing an access task corresponding to the storage block in the specific buffer; and controlling a voltage generator of the flash memory device to control at least one address decoder of the flash memory device to access the storage block of the flash memory chip again according to at least one critical voltage level of the voltage generator only after the temporarily stored access task has been temporarily stored for a specific preset time. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a schematic diagram of an example of a storage device including a flash memory controller and a flash memory device according to an embodiment of the present invention.

[0009] Figure 2 According to an embodiment of the present invention Figure 1 Schematic diagram of the storage cell array in .

[0010] Figure 3 According to an embodiment of the present invention Figure 1 The operation flow chart of the storage device is shown.

[0011] Figure 4 According to an embodiment of the present invention Figure 1 A schematic diagram showing a statistical trend of the number of failed bits when a flash memory device reads a storage block / page and then accesses the same storage block / page again with the same unadjusted threshold voltage value after waiting for different time periods.

[0012] Figure 5 According to an embodiment of the present invention Figure 1 The schematic diagram shows an example of a control circuit of a flash memory device controlling the voltage generator to output different threshold voltage levels.

[0013] Figure 6 is a schematic diagram of an example of a storage device according to another embodiment of the present invention.

[0014] Figure 7 According to an embodiment of the present invention Figure 7 The operation flow chart of the storage device is shown.

[0015]

Explanation of symbols

[0016] 100,600: Storage device

[0017] 105,605: Flash memory controller

[0018] 110,610: Flash memory device

[0019] 1051,6052:Processor

[0020] 1052: Input / output circuit

[0021] 1101: Input / output control circuit

[0022] 1102: Logic control circuit

[0023] 1103: Control circuit

[0024] 1104: Voltage generator

[0025] 1105: Address register

[0026] 1106: Command register

[0027] 1107: Storage cell array

[0028] 1108: Column address decoder

[0029] 1109: row address decoder

[0030] 1110,6054: Error Correction Code Circuit

[0031] 1112,6053:Buffer

[0032] 1111A~1111D: Storage block

[0033] 1113A, 1113B: Flash memory chip

[0034] 6051: Processing circuit DETAILED DESCRIPTION

[0035] Please refer to Figure 1 and Figure 2 , Figure 1 is a schematic diagram of an example of a storage device 100 including a flash memory controller 105 and a flash memory device 110 according to an embodiment of the present invention. Figure 2 According to an embodiment of the present invention Figure 1 Schematic diagram of a storage unit array 1107 in FIG. The storage device 100 is, for example, a solid state drive (SSD).

[0036] The flash memory controller 105 includes at least a processor 1051 and an input / output circuit 1052. The processor 1051 is coupled to the input / output circuit 1052 and is used to control the input / output circuit 1052 to send access (e.g., read, write / program, or erase) command signals / sequences to the flash memory device 110 through a specific communication interface to control and access the flash memory device 110.

[0037] The flash memory device 110 is, for example, a NAND type flash memory device including a plurality of chips / die. The flash memory device 110 includes an input / output control circuit 1101, a logic control circuit 1102, a control circuit 1103, a voltage generator 1104, such as a high voltage generator (but not limited to), an address register 1105, a command register 1106, a memory cell array 1107, a row address decoder 1108, a column address decoder 1109, and an error correction code (ECC) circuit 1110. The input / output control circuit 1101 is coupled to the flash memory controller 105 through the specific communication interface. The command register 1106 is coupled to the input / output control circuit 1101 for buffering a command information issued from the flash memory controller 105 and transmitted through the input / output control circuit 1101. The address register 1105 is coupled to the input / output control circuit 1101, and is used to buffer an address information sent by the flash memory controller 105 and transmitted through the input / output control circuit 1101. At least one address decoder, such as 1108 and / or 1109, is coupled to the storage cell array 1107. The voltage generator 1104 is coupled to the at least one address decoder, such as 1108, and the storage cell array 1107, and is used to generate and output at least one threshold voltage level to the at least one address decoder, such as 1108. The control circuit 1103 is coupled to the address register 1105, the command register 1106, the voltage generator 1104, and the storage cell array 1107, and is used to control the voltage generator 1104 to control the at least one address decoder, such as 1108, to access a storage block of a flash memory chip of the storage cell array 1107 according to the at least one threshold voltage level. The ECC circuit 1110 is coupled between the storage cell array 1107 and the input / output control circuit 1101, and is used to perform an ECC operation on a data of the storage block of the accessed flash memory chip, and generate an ECC result to the control circuit 1103. When the control circuit 1103 determines that the ECC result indicates an ECC failure, the control circuit 1103 temporarily stores an access task corresponding to the storage block in a specific buffer in the storage cell array 1107, and the control circuit 1103 controls the voltage generator 1104 to control the at least one address decoder, such as 1108, to access the storage block of the flash memory chip again according to the at least one threshold voltage level until the temporarily stored access task has been temporarily stored for a specific preset time.

[0038] In addition, before the temporarily stored access task has not been temporarily stored for the specific preset time, the control circuit 1103 controls the voltage generator 1104 to output and maintain the at least one critical voltage level to control the at least one address decoder, such as 1108, so that the flash memory chip accesses another storage block of the flash memory chip according to the at least one critical voltage level, and the access to the other storage block corresponds to another access command. In addition, after accessing each storage block, the control circuit 1103 checks whether the temporarily stored access task in the specific buffer has been temporarily stored for the specific preset time. In addition, when the error correction code fails to access the storage block of the flash memory chip again according to the at least one critical voltage level, the control circuit 1103 controls the voltage generator 1104 to adjust the at least one critical voltage level to control the at least one address decoder, such as 1108, so that the flash memory chip accesses the storage block of the flash memory chip according to the adjusted at least one critical voltage level. In addition, the specific preset time is adjustable and is between 100 milliseconds and 3 minutes. In addition, the specific buffer may also be disposed inside the flash memory device 110 (eg, inside the control circuit 1103 ) instead of being located in the storage cell array 1107 .

[0039] In practice, the flash memory controller 105 is coupled to the flash memory device 110 through the specific communication interface, and controls or accesses the flash memory device 110 by sending one or more commands to the flash memory device 110. The specific communication interface includes, for example, at least one signal port / pin, such as data pins DQ0-DQ7 or other data pins ( Figure 1 The data pins DQ0-DQ7 are coupled to the input / output control circuit 1101, and the logic control pins are coupled to the logic control circuit 1102.

[0040] The entire storage unit array 1107 is, for example, a flash memory module and has two or more flash memory chips / die (LUN), each flash memory chip / die includes two or more flash memory planes (hereinafter referred to as planes), each flash memory plane includes multiple storage blocks, each storage block includes multiple storage pages, and each storage page includes multiple storage sectors. For example, Figure 2As shown, the storage unit array 1107 includes two flash memory chips / bare crystals 1113A and 1113B, each flash memory chip / bare crystal 1113A or 1113B, for example, includes two planes, each plane includes multiple storage blocks, for example, multiple storage blocks 1111A form a first plane, multiple storage blocks 1111B form a second plane, multiple storage blocks 1111C form a third plane, and multiple storage blocks 1111D form a fourth plane, wherein the first and second planes are located in the flash memory chip / bare crystal 1113A, and the third and fourth planes are located in the flash memory chip / bare crystal 1113B; the flash memory chip / bare crystal 1113A or 1113B, for example, can correspond to the same flash memory channel or to different flash memory channels. In addition, the storage unit array 1107 can configure its storage space to form a storage space of a specific buffer 1112, so that the buffer 1112 is used as a specific queue (to be described in subsequent paragraphs).

[0041] In practice, when the flash memory controller 105 sends command data of a command signal, the flash memory controller 105 controls the signal of the pin ALE to be a low voltage level and controls the signal of the pin CLE to be a high voltage level, so that the flash memory device 110 can know that the data received through the pins DQ0~DQ7 is the command data, and then the received command data can be stored in the command register 1106 through the input / output control circuit 1101; the command register 1106 can temporarily store multiple command data. Similarly, when the flash memory controller 105 sends an address data, the flash memory controller 105 controls the signal of the pin ALE to be a high voltage level and controls the signal of the pin CLE to be a low voltage level, so that the flash memory device 110 can know that the data received by the pins DQ0-DQ7 is the address data, and then the received address data can be stored in the address register 1105 through the input / output control circuit 1101; the address register 1105 can temporarily store multiple address data. For simplicity, the pin RE and / or other pins ( Figure 1 The related operations are not described in detail.

[0042] In addition, the control circuit 1103 can control the voltage generator 1104 to output different voltage levels to the column address decoder 1108 and the row address decoder 1109, so that the column address decoder 1108 and the row address decoder 1109 can control the storage cell array 1107 to perform an access operation, such as a read operation, a programming operation or an erase operation, according to the different voltage levels, one or more received addresses buffered in the address register 1105 and one or more received commands buffered in the command register 1106. In other words, the flash memory controller 105 can send at least one access / control command to the flash memory device 110 to control the flash memory device 110 to perform at least one access / control task (e.g., a read task, a program task, or an erase task) to access at least one storage area of ​​at least one flash memory chip included in the flash memory device 110 (or the storage cell array 1107), such as at least one storage plane, at least one storage block, at least one storage page, and / or at least one storage sector. For a read task, in this embodiment (but not limited to), the data read from the storage cell array 1107 may have partial bit errors, so the data will first be checked and / or corrected by the error correction code operation performed by the error correction code circuit 1110 to generate an error-corrected data to the input / output control circuit 1101, and then output to the flash memory controller 105. For a write task (or programming task), the data from the input / output control circuit 1101 will be processed by the error correction code circuit 1110 to generate an error correction code to be attached to the data to form a data to be written, and then the data to be written will be written into at least one storage block, at least one storage page or at least one storage sector included in the storage cell array 1107). In this embodiment, the error correction code result of the error correction code operation performed by the error correction code circuit 1110 will also be transmitted to the control circuit 1103, and the control circuit 1103 can decide whether to control the voltage generator 1104 to maintain the originally preset output voltage level or adjust the output voltage level according to the error correction code result to reduce the error rate of data access (such as data reading), and the one or more voltage levels are the critical voltage values ​​of the flash memory voltage distribution.

[0043] Please refer to Figure 3 , Figure 3 According to an embodiment of the present invention Figure 1 The operation flow chart of the storage device 100 is shown. The detailed steps are described as follows:

[0044] Step S305: The control circuit 1103 of the flash memory device 110 determines whether any storage area (e.g., a storage block or page) of a flash memory chip of the storage cell array 1107 has an error correction code failure (hereinafter referred to as ECC failure) when an access task (e.g., a read task) is performed. If any ECC failure occurs, step S310 is performed. Otherwise, if no ECC failure occurs, step S315 is performed.

[0045] Step S310: The control circuit 1103 of the flash memory device 110 marks, pushes and temporarily stores the access task (e.g., read task) corresponding to the storage area (e.g., a storage block or page) in the buffer 1112 of the storage cell array 1107. The buffer 1112 is now used as a specific retry queue, such as a specific read retry queue (readretry queue), which is a first-in-first-out queue.

[0046] Step S315: Regardless of whether an ECC failure occurs, the control circuit 1103 of the flash memory device 110 controls the flash memory chip of the storage cell array 1107 to serve and process other access tasks (corresponding to other commands sent by the flash memory controller 105). Other access tasks are, for example, used to access / read other storage areas (other blocks or other pages) in the same flash memory chip;

[0047] Step S320: The control circuit 1103 of the flash memory device 110 determines whether a first task temporarily stored in the specific read retry queue has been temporarily stored for a specific preset time; if it has reached or exceeded the specific preset time, step S325 is performed; otherwise, if it has not reached the specific preset time, step S305 is performed to continue to determine whether an ECC failure occurs when other tasks are accessed;

[0048] Step S325: When the specific preset time has been reached, the control circuit 1103 of the flash memory device 110 will preliminarily determine that the access error rate at this time will be lower, and thus control the voltage generator 1104 to immediately and sequentially read at least one storage area (at least one block or page) corresponding to at least one task in the specific read retry queue without adjusting any threshold voltage value, for example, reading the block or page corresponding to the first read task in the specific read retry queue;

[0049] Step S330: The control circuit 1103 of the flash memory device 110 determines whether an ECC failure error still occurs when accessing (e.g., reading) without adjusting any threshold voltage value. If an ECC failure still occurs, step S335 is performed. Otherwise, if at least one task in the specific read retry queue does not have an ECC failure when reading without adjusting any threshold voltage value, step S305 is performed to continue to determine whether an ECC failure occurs when other tasks are accessed; and

[0050] Step S335: The control circuit 1103 of the flash memory device 110 controls the voltage generator 1104 to adjust the one or more threshold voltage values ​​outputted therefrom, so that the storage cell array 1107 can re-read the storage block or page with ECC failure based on the adjusted threshold voltage value.

[0051] As mentioned above, Figure 1 The flash memory controller 105 controls and accesses the flash memory device 110 to perform a work task (or an access task). For example, in a read task corresponding to a read command sent by the flash memory controller 105, the flash memory device 110 reads out at least one storage block (e.g., a storage block or a super block formed by multiple storage blocks) or at least one storage page (e.g., a single storage page or a super page formed by multiple storage pages) stored in at least one flash memory chip of the storage cell array 1107. For example, for reading data of a storage block / page, the data of the storage block / page is data protected by an error correction code. The error correction code circuit 1110 of the flash memory device 110 performs an error correction code operation on the data of the storage block / page. The error correction code operation can be more accurate. When there are some errors in the data of the storage block / page, and when there are too many errors in the data of the storage block / page, an ECC failure error will occur. At this time, after receiving the error result of ECC failure, the control circuit 1103 of the flash memory device 110 will determine that the error rate of reading and retrying immediately or subsequently is very high, so it will control the flash memory device 110 not to immediately (or subsequently) perform a read retry, and push the read task to and temporarily store it in the specific retry task queue, mark the time point (or time stamp) of the next processing on the entry of the read task, and wait until the error rate of ECC failure is reduced (for example, a specific preset time) before continuing to read and retry the data of the storage block / page.

[0052] Please refer to Figure 4 , Figure 4 According to an embodiment of the present invention Figure 1A schematic diagram showing the statistical trend of the fail bit count (FBC) of the flash memory device 110 when accessing the same storage block / page again with the same unadjusted threshold voltage value after reading a storage block / page and waiting for different time periods. Figure 4 As shown, for example (but not limited to), if the same storage block / page is accessed or read directly without waiting (i.e., the waiting time is zero seconds), the number of failed bits will be quite high, and the statistical trend of the number of failed bits will first decrease as the waiting time becomes longer, for example, when the waiting time is from zero seconds to 100 milliseconds, the statistical trend of the number of failed bits will decrease, and when the waiting time is within 100 milliseconds to 3 minutes, the statistical trend of the number of failed bits will be at a lower state, and when the waiting time begins to exceed 3 minutes, the statistical trend of the number of failed bits will begin to increase. Therefore, the specific preset time of the case can be set at 100 milliseconds, but this is not a limitation of the case, and it can also be set to a time within 100 milliseconds to 3 minutes, or it can also be dynamically determined by the user or by the flash memory controller 105.

[0053] In addition, as described in step S315, whether the read task has been completed or not, a flash memory chip including the storage block can be used to receive and serve at least one control command / task or at least one access command / task of other flash memories to improve the overall data processing efficiency. In addition, as described in step S320, after, for example, completing at least one other control command / task (or other access command / task), the control circuit 1103 of the flash memory device 110 will immediately check to confirm whether the difference between the time point marked on the first (or first) task in the specific read retry queue and the current time point has reached a predetermined time period (for example, 100 milliseconds, but not limited to). When it has reached, for example, 100 milliseconds, it means that the statistical trend of the number of failed bits in accessing the same storage block / page will be in a lower state, that is, the error rate of ECC failure at this time is lower. Therefore, when the time difference reaches the predetermined time period, the control circuit 1103 will stop serving other commands and instead control the voltage generator 1104 so that it does not adjust any critical voltage value to immediately re-read at least one storage area (at least one block or page) corresponding to the first (or first) task, as shown in step S325. Next, if an ECC failure occurs again during an immediate re-read operation without adjusting any critical voltage value, this indicates that the critical voltage distribution has changed. Therefore, as shown in step S335, the control circuit 1103 of the flash memory device 110 controls the voltage generator 1104 to adjust one or more critical voltage values ​​it outputs so that the storage cell array 1107 can re-read the storage block or page where the ECC failure occurred based on the adjusted critical voltage value.

[0054] Specifically, the invention of this case can be applied, for example, when multiple pages of a storage block are intensively read and written, but there is a sudden need to read and write a page of another storage block that has not been accessed for a long time. At this time, if an ECC error occurs when accessing the page of the other storage block, the page of the other storage block can be accessed again after waiting for a period of time, for example, from 100 milliseconds to 3 minutes, thereby reducing the ECC failure errors caused by sudden access.

[0055] Figure 5 According to an embodiment of the present invention Figure 1 The control circuit 1103 of the flash memory device 110 is shown as an example schematic diagram of controlling the voltage generator 1104 to output different threshold voltage levels. Figure 5As shown, a preset unadjusted critical voltage level Vth1 can be used, for example (but not limited to), to distinguish two different states of a voltage state distribution D1. When ECC failure occurs after waiting for a sufficient cooling time, it indicates that the voltage state distribution D1 may have shifted and become a voltage state distribution D1'. At this time, the control circuit 1103 can, for example, control the voltage generator 1104 to adjust the critical voltage level Vth1 to the critical voltage level Vth1' so as to correctly distinguish the two different states of the voltage state distribution D1', thereby reducing the error rate of data reading.

[0056] In addition, in other embodiments, Figure 3 Some of the process steps shown may be performed by a flash memory controller, such as error correction code operations and / or control and adjustment of different threshold voltage levels may also be performed by the flash memory controller. Figure 6 and Figure 7 , Figure 6 is a schematic diagram of an example of a storage device 600 according to another embodiment of the present invention. Figure 7 According to an embodiment of the present invention Figure 7 The operation flow chart of the storage device 600 is shown in FIG. The storage device 600 includes a flash memory controller 605 and a flash memory device 610, wherein the flash memory controller 605 includes at least a processing circuit 6051 and an input / output circuit 1052, the processing circuit 6051 is coupled to the input / output circuit 1052 and is used to control the input / output circuit 1052 to send an access (e.g., read, write / program or erase) command signal / sequence to the flash memory device 610 through a specific communication interface to control and access the flash memory device 610. The processing circuit 6051 includes a processor 6052, a specific buffer 6053 and an error correction code circuit 6054, wherein the specific buffer 6053 also serves as a specific retry task queue, and the operation of the error correction code circuit 6054 is similar to Figure 1 operation of the error correction code circuit 1110.

[0057] The flash memory device 610 is, for example, a NAND type flash memory device including a plurality of chips / die. The flash memory device 610 includes an input / output control circuit 1101, a logic control circuit 1102, a control circuit 1103, a voltage generator 1104, such as a high voltage generator (but not limited to), an address register 1105, a command register 1106, a memory cell array 1107, a row address decoder 1108, and a column address decoder 1109. The flash memory device 610 does not include an error correction code circuit in this embodiment, and other circuit components with the same number have the same operation and function.

[0058] The flash memory controller 605 is coupled to the flash memory device 610 through the specific communication interface, and controls or accesses the flash memory device 610 by sending one or more commands to the flash memory device 610. The processor 6052 can control the input / output circuit 1052 to send a command information to the flash memory device 610 through the specific communication interface, and control the input / output circuit 1052 to send an address information to the flash memory device 610 through the specific communication interface. The error correction code circuit 6054 is coupled to the processor 6052 to perform an error correction code operation on a data accessed from a storage block of a flash memory chip of the flash memory device 610 to generate an error correction code result to the processor 6052. The specific buffer 6053 is coupled to the processor 6052 and serves as a specific task retry queue. When the processor 6052 determines that the error correction code result indicates an error correction code failure, the processor 6052 temporarily stores an access task corresponding to the storage block in the specific buffer 6053, and until the stored access task has been temporarily stored for a specific preset time, the processor 6052 controls the control circuit 1103 of the flash memory device 610 through the specific communication interface to control the voltage generator 1104 of the flash memory device 610 to control at least one address decoder of the flash memory device 610, such as 1108, to access the storage block of the flash memory chip again according to at least one critical voltage level of the voltage generator 1104 of the flash memory device 610. In addition, before the temporarily stored access task has not been temporarily stored for the specific preset time, the processor 6052 of the flash memory controller 605 controls the control circuit 1103 of the flash memory device 610 to control the voltage generator 1104 of the flash memory device 610 to output and maintain the at least one critical voltage level to control the at least one address decoder 1108 of the flash memory device 610, so that the flash memory chip of the flash memory device 610 accesses another storage block of the flash memory chip according to the at least one critical voltage level, and accessing the another storage block corresponds to another access command. In addition, after accessing each storage block, the processor 6052 checks whether the temporarily stored access task in the specific buffer 6053 of the flash memory controller 605 has been temporarily stored for the specific preset time.In addition, when an error correction code fails when accessing the storage block of the flash memory chip again according to the at least one critical voltage level, the processor 6052 controls the control circuit 1103 of the flash memory device 610 to control the voltage generator 1104 of the flash memory device 610 to adjust the at least one critical voltage level to control the at least one address decoder such as 1108, so that the flash memory chip accesses the storage block of the flash memory chip according to the adjusted at least one critical voltage level. In addition, the specific preset time is also adjustable and is between 100 milliseconds and 3 minutes.

[0059] Specifically, the flash memory controller 605 (or the processor 6052 of the processing circuit 6051) can send at least one access / control command to the flash memory device 610 to control the flash memory device 610 to perform at least one access / control task (e.g., a read task, a programming task, or an erase task) to access at least one storage area of ​​at least one flash memory chip included in the flash memory device 610 (or the storage cell array 1107), such as at least one storage plane, at least one storage block, at least one storage page, and / or at least one storage sector. For a read task, in this embodiment (but not limited to), the data read from the storage cell array 1107 may have some bit errors, so the data will be checked and / or corrected by the error correction code operation performed by the error correction code circuit 6054 of the flash memory controller 605 after passing through the input / output control circuit 1101, the specific communication interface, and the input / output circuit 1052 to generate an error-corrected data to the processor 6052. For a write task (or programming task), a piece of data from the processor 6052 will be processed by the error correction code operation performed by the error correction code circuit 6054 to generate an error correction code attached to the data to form a piece of data to be written, and then the piece of data to be written will be written to at least one storage block, at least one storage page, or at least one storage sector included in the storage cell array 1107 after passing through the input / output circuit 1052, the specific communication interface, and the input / output control circuit 1101. In the present embodiment, the error correction code result of the error correction code operation performed by the error correction code circuit 6054 is also transmitted to the processor 6052, and the processor 6052 can decide whether to control the control circuit 1103 of the flash memory device 610 to control the voltage generator 1104 to maintain the originally preset output voltage level or adjust the output voltage level to reduce the error rate of data access (such as data reading). The one or more voltage levels are the critical voltage values ​​of the flash memory voltage distribution.

[0060] Please refer to Figure 7, Figure 7 The detailed steps are described as follows:

[0061] Step S705: When receiving the ECC result of the ECC operation performed by the ECC circuit 6054 of the flash memory controller 605, the processor 6052 of the flash memory controller 605 determines whether any storage area (e.g., a storage block or page) of a flash memory chip of the storage cell array 1107 has an ECC failure when an access task (e.g., a read task) is performed. If any ECC failure occurs, step S710 is performed. Otherwise, if no ECC failure occurs, step S715 is performed.

[0062] Step S710: The processor 6052 of the flash memory controller 605 marks, pushes and temporarily stores the access task (e.g., read task) corresponding to the storage area (e.g., a storage block or page) in the buffer 6053 of the flash memory controller 605. The buffer 6053 is used as a specific retry queue, such as a specific read retry queue, which is a first-in-first-out queue.

[0063] Step S715: Regardless of whether an ECC failure occurs, the processor 6052 of the flash memory controller 605 controls the control circuit 1103 of the flash memory device 610 to control the flash memory chip of the storage cell array 1107 to serve and process other access tasks (corresponding to other commands sent by the flash memory controller 605). Other access tasks are, for example, to access / read other storage areas (other blocks or other pages) in the same flash memory chip.

[0064] Step S720: The processor 6052 of the flash memory controller 605 determines whether a first task temporarily stored in the specific read retry queue has reached a specific preset time; if it has reached or exceeded the specific preset time, step S725 is performed; otherwise, if it has not reached the specific preset time, step S705 is performed to continue to determine whether an ECC failure occurs when other tasks are accessed;

[0065] Step S725: When the specific preset time has been reached, the processor 6052 of the flash memory controller 605 will preliminarily determine that the access error rate at this time will be lower, so the processor 6052 of the flash memory controller 605 will control the control circuit 1103 of the flash memory device 610 to control the voltage generator 1104 to immediately and sequentially read at least one storage area (at least one block or page) corresponding to at least one task in the specific read retry queue without adjusting any threshold voltage value, for example, reading the block or page corresponding to the first read task in the specific read retry queue;

[0066] Step S730: The processor 6052 of the flash memory controller 605 determines whether an ECC failure error still occurs when accessing (e.g., reading) without adjusting any threshold voltage value. If an ECC failure still occurs, step S735 is performed. Otherwise, if at least one task in the specific read retry queue does not have an ECC failure when reading without adjusting any threshold voltage value, step S705 is performed to continue to determine whether an ECC failure occurs when other tasks are accessed; and

[0067] Step S735: The processor 6052 of the flash memory controller 605 controls the control circuit 1103 of the flash memory device 610 to control the voltage generator 1104 to adjust one or more threshold voltage values ​​outputted therefrom, so that the storage cell array 1107 can re-read the storage block or page with ECC failure based on the adjusted threshold voltage values.

[0068] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made according to the scope of the patent application of the present invention should fall within the scope of the present invention.

Claims

1. A flash memory device, used in a storage device, coupled to a flash memory controller of the storage device via a specific communication interface, and the flash memory device comprises: an input / output control circuit coupled to the flash memory controller through the specific communication interface; a command register coupled to the input / output control circuit for buffering command information issued from the flash memory controller and transmitted through the input / output control circuit; an address register, coupled to the input / output control circuit, for buffering address information sent by the flash memory controller and transmitted through the input / output control circuit; A storage unit array has a plurality of flash memory chips, each of which has a plurality of flash memory planes, each of which has a plurality of storage blocks, and each of which has a plurality of storage pages; at least one address decoder coupled to the storage cell array; a voltage generator, coupled to the at least one address decoder and the storage cell array, for generating and outputting at least one critical voltage level to the at least one address decoder; a control circuit coupled to the address register, the command register, the voltage generator and the storage cell array, for controlling the voltage generator to control the at least one address decoder to access a storage block of a flash memory chip of the storage cell array according to the at least one threshold voltage level; as well as An error correction code circuit is coupled between the storage cell array and the input / output control circuit, and is used to perform an error correction code operation on a data of the storage block of the accessed flash memory chip, and generate an error correction code result to the control circuit; When the control circuit determines that the error correction code result indicates an error correction code failure, the control circuit temporarily stores an access task corresponding to the storage block in a specific buffer in the storage unit array, and the control circuit controls the voltage generator to control the at least one address decoder to access the storage block of the flash memory chip again according to the at least one critical voltage level until the temporarily stored access task has been temporarily stored for a specific preset time.

2. The flash memory device according to claim 1, wherein: Before the temporarily stored access task reaches the specific preset time, the control circuit controls the voltage generator output to maintain the at least one critical voltage level to control the at least one address decoder, so that the flash memory chip accesses another storage block of the flash memory chip according to the at least one critical voltage level, and accessing the another storage block corresponds to another access command.

3. The flash memory device according to claim 1, wherein: After accessing each storage block is completed, the control circuit checks whether the access task temporarily stored in the specific buffer has been temporarily stored for the specific preset time.

4. The flash memory device according to claim 1, wherein: When an error correction code fails when accessing the storage block of the flash memory chip again according to the at least one critical voltage level, the control circuit controls the voltage generator to adjust the at least one critical voltage level to control the at least one address decoder, so that the flash memory chip accesses the storage block of the flash memory chip according to the adjusted at least one critical voltage level.

5. The flash memory device according to claim 1, wherein: The specific preset time is adjustable and is between 100 milliseconds and 3 minutes.

6. A flash memory controller, used in a storage device, a flash memory device coupled to the storage device through a specific communication interface, and the flash memory controller comprises: an input / output circuit coupled to the flash memory device through the specific communication interface; A processing circuit, coupled to the input / output circuit, comprises: a processor, used to control the input / output circuit to send a command message to the flash memory device through the specific communication interface, and control the input / output circuit to send an address message to the flash memory device through the specific communication interface; an ECC circuit coupled to the processor for performing an ECC operation on data accessed from a storage block of a flash memory chip of the flash memory device to generate an ECC result to the processor; as well as a specific buffer coupled to the processor; When the processor determines that the error correction code result indicates an error correction code failure, the processor temporarily stores an access task corresponding to the storage block in the specific buffer, and only after the temporarily stored access task has been temporarily stored for a specific preset time, the processor controls the control circuit of the flash memory device through the specific communication interface to control the voltage generator of the flash memory device to control at least one address decoder of the flash memory device to access the storage block of the flash memory chip again according to at least one critical voltage level of the voltage generator of the flash memory device.

7. The flash memory controller according to claim 6, wherein: Before the temporarily stored access task reaches the specific preset time, the processor of the flash memory controller controls the control circuit of the flash memory device to control the voltage generator output of the flash memory device to maintain the at least one critical voltage level to control the at least one address decoder of the flash memory device, so that the flash memory chip of the flash memory device accesses another storage block of the flash memory chip according to the at least one critical voltage level, and accessing the another storage block corresponds to another access command.

8. The flash memory controller according to claim 6, wherein: After accessing each storage block is completed, the processor checks whether the access task temporarily stored in the specific buffer of the flash memory controller has been temporarily stored for the specific preset time.

9. The flash memory controller according to claim 6, wherein: When an error correction code failure occurs when accessing the storage block of the flash memory chip again according to the at least one critical voltage level, the processor controls the control circuit of the flash memory device to control the voltage generator of the flash memory device to adjust the at least one critical voltage level to control the at least one address decoder, so that the flash memory chip accesses the storage block of the flash memory chip according to the adjusted at least one critical voltage level.

10. The flash memory controller according to claim 6, wherein: The specific preset time is adjustable and is between 100 milliseconds and 3 minutes.

11. A method for using a flash memory device, the flash memory device being used in a storage device and coupled to a flash memory controller of the storage device through a specific communication interface, and the method comprising: Providing an input / output control circuit coupled to the flash memory controller through the specific communication interface; A command register is provided, coupled to the input / output control circuit, and the command register is used to cache a command information issued from the flash memory controller and transmitted through the input / output control circuit; Providing an address register, coupled to the input / output control circuit, using the address register to cache address information sent by the flash memory controller and transmitted through the input / output control circuit; A storage unit array having a plurality of flash memory chips is provided, each flash memory chip having a plurality of flash memory planes, each flash memory plane having a plurality of storage blocks, and each storage block having a plurality of storage pages; Providing at least one address decoder coupled to the storage cell array; Providing a voltage generator, coupled to the at least one address decoder and the storage cell array, using the voltage generator to generate and output at least one critical voltage level to the at least one address decoder; Providing a control circuit to control the voltage generator to control the at least one address decoder to access a storage block of a flash memory chip of the storage cell array according to the at least one critical voltage level; Providing an error correction code circuit, coupled between the storage cell array and the input / output control circuit, using the error correction code circuit to perform an error correction code operation on a data of the storage block of the accessed flash memory chip to generate an error correction code result to the control circuit; When the error correction code result indicates an error correction code failure, temporarily storing an access task corresponding to the storage block in a specific buffer in the storage unit array; as well as The voltage generator is controlled to control the at least one address decoder to access the storage block of the flash memory again according to the at least one threshold voltage level until the temporarily stored access task has been temporarily stored for a specific preset time.

12. The method according to claim 11, characterized in that include: Before the temporarily stored access task reaches the specific preset time, the voltage generator output is controlled to maintain the at least one critical voltage level to control the at least one address decoder, so that the flash memory chip accesses another storage block of the flash memory chip according to the at least one critical voltage level, wherein accessing the another storage block corresponds to another access command.

13. The method according to claim 11, characterized in that include: After accessing each storage block is completed, checking whether the access task temporarily stored in the specific buffer has been temporarily stored for the specific preset time.

14. The method according to claim 11, characterized in that include: When an error correction code fails when accessing the storage block of the flash memory again according to the at least one critical voltage level, the voltage generator is controlled to adjust the at least one critical voltage level to control the at least one address decoder, so that the flash memory chip accesses the storage block of the flash memory chip according to the adjusted at least one critical voltage level.

15. The method according to claim 11, characterized in that The specific preset time is adjustable and is between 100 milliseconds and 3 minutes.

16. A method for use in a flash memory controller, the flash memory controller being used in a storage device and coupled to a flash memory device of the storage device through a specific communication interface, and the method comprising: Providing an input / output circuit coupled to the flash memory device through the specific communication interface; Controlling the input / output circuit to send a command message to the flash memory device through the specific communication interface; Controlling the input / output circuit to send an address information to the flash memory device through the specific communication interface; Providing an ECC circuit for performing an ECC operation on data accessed from a storage block of a flash memory chip of the flash memory device to generate an ECC result; Providing a specific buffer; When the error correction code result indicates an error correction code failure, temporarily storing an access task corresponding to the storage block in the specific buffer; as well as After the temporarily stored access task has been temporarily stored for a specific preset time, the specific communication interface is used to control a voltage generator of the flash memory device to control at least one address decoder of the flash memory device to access the storage block of the flash memory chip again according to at least one critical voltage level of the voltage generator.

17. The method according to claim 16, characterized in that include: Before the temporarily stored access task reaches the specific preset time, the voltage generator of the flash memory device is controlled through the communication interface to output and maintain the at least one critical voltage level to control the at least one address decoder of the flash memory device, so that the flash memory chip of the flash memory device accesses another storage block of the flash memory chip according to the at least one critical voltage level, and accessing the another storage block corresponds to another access command.

18. The method according to claim 16, characterized in that include: After accessing each storage block is completed, checking whether the access task temporarily stored in the specific buffer of the flash memory controller has been temporarily stored for the specific preset time.

19. The method according to claim 16, characterized in that include: When an error correction code failure occurs when accessing the storage block of the flash memory chip again according to the at least one critical voltage level, the voltage generator of the flash memory device is controlled through the communication interface to adjust the at least one critical voltage level to control the at least one address decoder of the flash memory device, so that the flash memory chip accesses the storage block of the flash memory chip according to the adjusted at least one critical voltage level.

20. The method of claim 16, wherein: The specific preset time is adjustable and is between 100 milliseconds and 3 minutes.

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