A write circuit and method for a configurable SRAM within an FPGA
By introducing multiple pull-down control modules and bit line feedback into the SRAM write circuit within the FPGA, the reliability and cost issues of SRAM writing in the prior art are solved, and efficient write operations are achieved under different process deviations and low voltages.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHANGHAI ANLOGIC INFOTECH CO LTD
- Filing Date
- 2023-11-06
- Publication Date
- 2026-07-03
AI Technical Summary
Existing technologies for improving the write reliability of SRAM within FPGAs suffer from increased design costs, larger area, and increased complexity, especially with high write failure rates under process variations and low voltage conditions.
Multiple pull-down control modules and SRAM bit line feedback are used to enhance the SRAM write drive capability. The write circuit design is optimized by combining the configuration control module, data controller, address decoder, configuration memory cell array, pull-down control module and buffer module.
While reducing design costs and area, it improves the write reliability of SRAM, especially the write success rate under different process deviations and low voltage conditions.
Smart Images
Figure CN117334235B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of integrated circuit technology, and more specifically to a writing technology for configurable SRAM within an FPGA. Background Technology
[0002] This section is intended to provide background or context for the embodiments of this application as set forth in the claims. The description herein is not intended to imply that it is prior art that has been disclosed, simply because it is included in this section.
[0003] As the feature size of integrated circuits continues to shrink in advanced manufacturing processes, the deviations, especially local variations, in metal-oxide-semiconductor field-effect transistors (MOS) become increasingly large, significantly impacting the reliability of static random access memory (SRAM). The read / write process of SRAM involves a competition between the driving capabilities of N-type (NMOS) and P-type (PMOS) transistors. When the driving capabilities of NMOS and PMOS transistors differ significantly due to process variations, SRAM read / write failures may occur. This paper primarily describes methods to improve SRAM write reliability.
[0004] The mainstream technologies for Field-Programmable Gate Arrays (FPGAs) include antifuse-based, SRAM-based, and flash-based technologies. Compared to antifuse and flash-based FPGAs, SRAM-based FPGAs offer significant performance advantages and design flexibility, making them highly attractive for flight control and avionics applications. Currently, the vast majority of products from Xilinx and Altera, the largest FPGA manufacturers in terms of market share, are SRAM-based, and aerospace agencies in Europe and the United States also use SRAM-based FPGAs as core electronic components.
[0005] SRAM is an important component for implementing functions in SRAM-based FPGAs. Users need to download the logic functions to be implemented into the programmable SRAM of the FPGA in the form of a code stream. If the writing to the programmable SRAM fails, it may cause the user to be unable to achieve the expected function and the chip to fail.
[0006] There are three main methods to enhance SRAM write reliability: using SRAM with smaller process tolerances, increasing the word line (address line) voltage, and enhancing the capability of the driver transistors. Using components with smaller process tolerances significantly improves SRAM reliability, but the downside is a larger area or static leakage current. Increasing the SRAM word line voltage requires designing an additional voltage regulator, which is complex and costly. Enhancing the capability of the driver transistors is a common design approach; pull-down transistors composed of NMOS transistors play a major role in the SRAM write process. However, with changes in on-chip conditions (process corner, voltage, and temperature, i.e., PVT), increasing the size of the NMOS transistors under boundary conditions can also lead to SRAM write failures.
[0007] Currently, FPGA manufacturers Xilinx and Altera have also enhanced the write reliability of SRAM in their advanced process products to cope with increasingly larger process variations and lower operating voltages. Their main approach is to increase the SRAM wordline voltage during the write process. However, this approach presents several problems: increased design costs, the need for a separate voltage regulator, the investment of human resources in developing analog circuits, increased design complexity, increased chip area, and higher overall design costs. Summary of the Invention
[0008] The purpose of this invention is to provide a write circuit for configurable SRAM within an FPGA, which improves the write reliability of SRAM with a relatively low increase in design cost.
[0009] In this invention, a write circuit for a configurable SRAM within an FPGA is provided, comprising a configuration control module, a data controller, multiple address decoders, a configuration memory cell array, a pull-down control module, and a buffer module, wherein:
[0010] The configuration control module is connected to the data controller;
[0011] The data controller is connected to the configuration storage unit array via multiple pairs of bit lines and negative bit lines, and each pair of bit lines and negative bit lines is connected to a column of storage units in the configuration storage unit array;
[0012] The data controller is connected to the buffer module through the multiple pairs of bit lines and negative bit lines, write enable signal line and data pull-down enable signal line, and is connected to the pull-down control module through the multiple pairs of bit lines and negative bit lines and the data pull-down enable signal line. The pull-down control module is used to receive the "0" signal on the bit line or negative bit line, and under the control of the data pull-down enable signal, open the N-type drive transistor switch of the bit line or negative bit line corresponding to the pull-down "0" signal, and close the N-type drive transistor switch of the other bit line or negative bit line.
[0013] The configuration control module is connected to each of the plurality of address decoders via an address enable signal line, and each row of storage cells in the configuration storage cell array corresponds one-to-one with the plurality of address decoders and is connected accordingly via word lines.
[0014] In a preferred embodiment, the pull-down control module is positioned centrally within the configuration storage unit array.
[0015] In a preferred embodiment, the pull-down control module is located at a boundary position in the configuration memory cell array away from the bit line origin.
[0016] In a preferred embodiment, one row of the storage unit corresponds to one or more of the pull-down control modules.
[0017] In a preferred embodiment, the area and power consumption of the pull-down control module are smaller than those of the data controller.
[0018] In a preferred embodiment, the system includes a configuration control module, a data controller, multiple address decoders, a configuration memory array, a pull-down control module, and a buffer module, wherein:
[0019] The configuration control module sends a data frame and then sends a write enable signal.
[0020] The data is transmitted to a bit line of a column of memory cells in the configured memory cell array via the data controller. Depending on the data value, the bit line or negative bit line is pulled down to "0" by the data controller.
[0021] After the "0" signal is established, the data controller sends a data pull-down enable signal to the buffer module.
[0022] Based on the "0" signal on the bit line or negative bit line, the pull-down control module, under the control of the data pull-down enable signal, turns on the N-type drive transistor switch of the bit line or negative bit line corresponding to the pull-down "0" signal, and turns off the N-type drive transistor switch of the other bit line or negative bit line.
[0023] The address enable signal sent by the configuration control module enables the word line and starts the plurality of address decoders.
[0024] Under the control of the write enable signal and the address enable signal, the value of the storage cell is rewritten to the data value, thus completing the write operation of the static random access memory.
[0025] In a preferred embodiment, the data value includes "0";
[0026] When the configuration control module sends data "0", the bit line is pulled down to "0" by the data controller. The data pull-down enable signal needs to wait for the "0" on the bit line to be completely established before it is turned on.
[0027] The pull-down control module, based on the "0" signal on the bit line and under the control of the data pull-down enable signal, turns on the N-type drive transistor switch of the pull-down bit line and turns off the N-type drive transistor switch of the negative bit line.
[0028] In a preferred embodiment, the data value includes "1";
[0029] When the configuration control module sends data "1", the negative bit line is pulled down to "0" by the data controller. The data pull-down enable signal needs to wait for the "0" on the negative bit line to be fully established before it is turned on.
[0030] The pull-down control module, based on the "0" signal on the negative bit line and under the control of the data pull-down enable signal, turns on the N-type drive transistor switch of the pull-down negative bit line and turns off the N-type drive transistor switch of the bit line.
[0031] In a preferred embodiment, the write enable signal is issued after all data in a frame has been sent; the data pull-down enable signal needs to wait for N cycles to end until the "0" signal is fully established before it is activated, where N depends on the establishment time of the "0" signal.
[0032] In a preferred embodiment, when the pull-down control module receives a "0" signal on the bit line or negative bit line, and opens the N-type drive transistor switch of the bit line or negative bit line corresponding to the pull-down "0" signal under the control of the data pull-down enable signal, and closes the N-type drive transistor switch of the other bit line or negative bit line, the drive on the write path includes the data controller and the pull-down control module.
[0033] The main differences and effects of the embodiments of the present invention compared with the prior art are as follows:
[0034] This disclosure employs a combination of multiple pull-down control modules and utilizes SRAM bitline (i.e., SRAM data line) feedback to improve the drive capability of SRAM writes, thereby improving the write reliability of SRAM, especially the write reliability of SRAM under different process deviations and lower voltages.
[0035] Furthermore, this implementation method features a small circuit area and flexible implementation, allowing for the insertion of multiple modules to accommodate different bitline loads. This design approach can significantly reduce design costs and area, thereby enhancing product competitiveness.
[0036] It should be understood that, within the scope of this invention, the above-described technical features of this invention and the technical features specifically described below (such as in the embodiments) can be combined with each other to form new or preferred technical solutions. Due to space limitations, they will not be described in detail here. Attached Figure Description
[0037] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0038] Figure 1 This is a schematic diagram of the writing circuit framework structure according to one embodiment of this application;
[0039] Figure 2 This is a schematic diagram of the enhanced writing of "0" implementation process according to one embodiment of this application;
[0040] Figure 3 This is a schematic diagram of the implementation process of enhancing the writing of "1" according to one embodiment of this application.
[0041] The labels in each of the attached figures are as follows:
[0042] 101 - Configure the control module;
[0043] 102 - Data Controller;
[0044] 103 - Address Decoder;
[0045] 104 - Configure the storage unit array;
[0046] 105 - Drop-down control module;
[0047] 106-Buffer;
[0048] 201-206 - Enhanced steps for writing "0";
[0049] 301~306 - Enhanced steps for writing "1". Detailed Implementation
[0050] In the following description, many technical details are presented to help the reader better understand this application. However, those skilled in the art will understand that the technical solutions claimed in this application can be implemented even without these technical details and various variations and modifications based on the following embodiments.
[0051] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.
[0052] In this invention, a write circuit for a configurable SRAM within an FPGA is provided, the structure of which is as follows: Figure 1 As shown, the circuit includes a configuration control module 101, a data controller (DSR) 102, multiple address decoders (addr_dec) 103, a configuration memory cell array (sram_cell) 104, a pull-down control module (pull_down) 105, and a buffer module (RPT) 106, wherein:
[0053] The configuration control module 101 is responsible for configuring the conversion between storage unit address / data and other circuit interfaces;
[0054] The data controller 102 is responsible for shifting the frame data to be written in units of words and transferring the data to the bitline and the negative bitline.
[0055] Address decoder 103 performs address decoding on the memory cell array and controls the opening and closing of word lines.
[0056] The configuration storage unit array 104 stores FPGA configuration data in frames.
[0057] The pull-down control module 105 determines which pull-down drive transistor to turn on by identifying the values of the bit line and the negative bit line.
[0058] The data line buffer module 106 is used to insert a buffer into the SRAM array to increase the driving capability of the data line, so that the data can be completely transmitted to the boundary of the storage array.
[0059] Configure control module 101 to connect to data controller 102;
[0060] The data controller 102 is connected to the configuration storage cell array 104 via multiple pairs of bit lines and negative bit lines, and each pair of bit lines and negative bit lines is connected to a column of storage cells in the configuration storage cell array 104.
[0061] The data controller 102 is connected to the buffer module 106 via multiple pairs of bit lines and negative bit lines, write enable signal line (data_en) and data pull-down enable signal line (data_en_pd), and is also connected to the pull-down control module 105 via multiple pairs of bit lines and negative bit lines and data pull-down enable signal line. The pull-down control module 105 is used to receive the "0" signal on the bit line or negative bit line, and under the control of the data pull-down enable signal, it opens the N-type drive transistor switch of the bit line or negative bit line corresponding to the pull-down "0" signal, and closes the N-type drive transistor switch of the other bit line or negative bit line.
[0062] The configuration control module 101 is connected to each of the multiple address decoders 103 through the address enable signal line (address_en). Each row of memory cells in the configuration memory cell array 104 corresponds one-to-one with the multiple address decoders 103 and is connected accordingly through word lines.
[0063] In one embodiment, the pull-down control module 105 is positioned centrally within the configuration memory cell array 104, which yields better results. In another embodiment, the pull-down control module 105 can also be positioned at a boundary location in the configuration memory cell array 104, away from the bit line start point. The position of the drive circuit can be adjusted according to the layout and reliability requirements, increasing design flexibility.
[0064] In one embodiment, a row of storage cells corresponds to one or more pull-down control modules 105. Different manufacturing processes result in different line resistances, allowing the number of drive circuits to be adjusted according to varying load resistances.
[0065] In one embodiment, the area and power consumption of the pull-down control module 105 are smaller than those of the data controller 102. Compared with traditional methods, this method can reduce circuit area and power consumption, which helps to reduce product costs.
[0066] In one embodiment, the system includes a configuration control module 101, a data controller 102, multiple address decoders 103, a configuration memory array 104, a pull-down control module 105, and a buffer module 106, wherein:
[0067] The configuration control module 101 sends a frame of data, and then sends a write enable signal; the write enable signal is sent after all the data frames have been sent.
[0068] Data is transmitted to the bit line of a column of memory cells in the connected configuration memory cell array 104 via the data controller 102. Depending on the data value, the bit line or negative bit line is pulled down to "0" by the data controller 102.
[0069] After the "0" signal is established, the data controller 102 sends a data pull-down enable signal to the buffer module 106. The data pull-down enable signal needs to wait for N cycles to end until the "0" signal is fully established before it is enabled. N depends on the establishment time of the "0" signal.
[0070] According to the "0" signal on the bit line or negative bit line, the pull-down control module 105, under the control of the data pull-down enable signal, turns on the N-type drive transistor switch of the bit line or negative bit line corresponding to the pull-down "0" signal, and turns off the N-type drive transistor switch of the other bit line or negative bit line.
[0071] By configuring the address enable signal sent by the control module 101, the word line is enabled, and multiple address decoders 103 are started.
[0072] Under the control of the write enable signal and the address enable signal, the value of the memory cell is rewritten as a data value, completing the write operation of the static random access memory.
[0073] Figure 2 and Figure 3 The diagram illustrates the process of enhancing the SRAM write path driving capability through feedback from bit lines and inverted bit lines. Specifically, the SRAM write process is mainly accomplished by pull-down transistors in the drive circuit. During the writing of a "0", the bit line is pulled down to 0. For the configuration memory cell 104, which is far from the data controller 102, the bit line length of the write path is relatively long, and the resistance is relatively high, increasing the difficulty of writing the value "0". The function of the pull-down control module 105 is to increase the driving capability on the bit line path after confirming the writing of "0" data. At this time, the drive transistor controlling the inverted bit line pull-down in the pull-down control module 105 is turned off. Similarly, during the writing of a "1", the inverted bit line is pulled down to 0. For the configuration memory cell 104, which is far from the data controller 102, the inverted bit line length of the write path is relatively long, and the resistance is relatively high, increasing the difficulty of writing the value "1". The function of the pull-down control module 105 is to increase the driving capability on the inverted bit line path after confirming the writing of "1" data. At this time, the drive transistor controlling the bit line pull-down in the pull-down control module 105 is turned off.
[0074] The specific steps are as follows, in one embodiment, such as Figure 2 As shown, the data values include "0";
[0075] Step 201: Send data "0" through the configuration control module 101, and then send a write enable signal.
[0076] In step 202, the data "0" is transmitted to the bit line through the data controller 102, and the bit line is pulled down to "0" by the data controller 102; at this time, only the data controller 102 is turned on in the write path.
[0077] Step 203: The data pull-down enable signal needs to wait for N cycles to end until the "0" signal on the bit line is fully established before it is turned on. N depends on the establishment time of the "0" signal.
[0078] In step 204, the pull-down control module 105, based on the "0" signal on the bit line and under the control of the data pull-down enable signal, turns on the N-type drive transistor switch of the pull-down bit line and turns off the N-type drive transistor switch of the negative bit line. At this time, the write path is driven by the data controller 102 and the pull-down control module 105. The activation of the pull-down control module 105 enhances the driving capability of the write "0" path.
[0079] Step 205: By sending the address enable signal through the configuration control module 101, the word line is enabled, and the plurality of address decoders 103 are started.
[0080] Step 206: Under the control of the write enable signal and the address enable signal, the value of the memory cell is rewritten to "0", thus completing the write operation of the static random access memory.
[0081] In one embodiment, such as Figure 3 As shown, the data values include "1";
[0082] Step 301: Send data "1" through configuration control module 101, and then send write enable signal.
[0083] In step 302, the data "1" is transmitted to the bit line through the data controller 102, and the negative bit line is pulled down to "0" by the data controller 102; at this time, only the data controller 102 is turned on in the write path.
[0084] Step 303: The data pull-down enable signal needs to wait for N cycles to end until the "0" signal on the negative bit line is fully established before it is turned on. N depends on the establishment time of the "0" signal.
[0085] In step 304, the pull-down control module 105, based on the "0" signal on the negative bit line and under the control of the data pull-down enable signal, turns on the N-type drive transistor switch of the pull-down negative bit line and turns off the N-type drive transistor switch of the bit line. At this time, the write path is driven by the data controller 102 and the pull-down control module 105. The activation of the pull-down control module 105 enhances the driving capability of the write "1" path.
[0086] Step 305: By sending the address enable signal through the configuration control module 101, the word line is enabled, and the plurality of address decoders 103 are started.
[0087] Step 306: Under the control of the write enable signal and the address enable signal, the value of the memory cell is rewritten to "1", thus completing the write operation of the static random access memory.
[0088] It should be noted that in the claims and specification of this patent, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one" does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.
[0089] All documents mentioned in this invention are incorporated herein by reference as if each document were individually incorporated by reference. Furthermore, it should be understood that after reading the foregoing teachings of this invention, those skilled in the art can make various alterations or modifications to this invention, and these equivalent forms also fall within the scope defined by the appended claims.
Claims
1. A write circuit for configurable SRAM within an FPGA, characterized in that, It includes a configuration control module, a data controller, multiple address decoders, a configuration memory array, a pull-down control module, and a buffer module, wherein: The configuration control module is connected to the data controller; The data controller is connected to the configuration storage unit array via multiple pairs of bit lines and negative bit lines, and each pair of bit lines and negative bit lines is connected to a column of storage units in the configuration storage unit array; The data controller is connected to the buffer module through the multiple pairs of bit lines and negative bit lines, write enable signal line and data pull-down enable signal line, and is connected to the pull-down control module through the multiple pairs of bit lines and negative bit lines and the data pull-down enable signal line. The pull-down control module is used to receive the "0" signal on the bit line or negative bit line, and under the control of the data pull-down enable signal, open the N-type drive transistor switch of the bit line or negative bit line corresponding to the pull-down "0" signal, and close the N-type drive transistor switch of the other bit line or negative bit line. The configuration control module is connected to each of the plurality of address decoders via an address enable signal line, and each row of storage cells in the configuration storage cell array corresponds one-to-one with the plurality of address decoders and is connected accordingly via word lines.
2. The write circuit for configurable SRAM within an FPGA according to claim 1, characterized in that, The pull-down control module is located in the center of the configuration storage unit array.
3. The write circuit for configurable SRAM within an FPGA according to claim 1, characterized in that, The pull-down control module is located at a boundary position in the configuration memory cell array that is far from the start of the bit line.
4. The write circuit for configurable SRAM within an FPGA according to claim 1, characterized in that, Each row of storage units corresponds to one or more of the pull-down control modules.
5. The write circuit for configurable SRAM within an FPGA according to claim 1, characterized in that, The area and power consumption of the pull-down control module are smaller than those of the data controller.
6. A writing method, applied to the writing circuit of configurable SRAM within an FPGA according to any one of claims 1 to 5, characterized in that, It includes a configuration control module, a data controller, multiple address decoders, a configuration memory array, a pull-down control module, and a buffer module, wherein: The configuration control module sends a data frame and then sends a write enable signal. The data is transmitted to the bit line of a column of memory cells in the configuration memory cell array via the data controller. Depending on the data value, the bit line or negative bit line is pulled down to "0" by the data controller. After the "0" signal is established, the data controller sends a data pull-down enable signal to the buffer module. Based on the "0" signal on the bit line or negative bit line, the pull-down control module, under the control of the data pull-down enable signal, turns on the N-type drive transistor switch of the bit line or negative bit line corresponding to the pull-down "0" signal, and turns off the N-type drive transistor switch of the other bit line or negative bit line. The address enable signal sent by the configuration control module enables the word line and starts the plurality of address decoders. Under the control of the write enable signal and the address enable signal, the value of the storage cell is rewritten to the data value, thus completing the write operation of the static random access memory.
7. The writing method according to claim 6, characterized in that, The data values include "0"; When the configuration control module sends data "0", the bit line is pulled down to "0" by the data controller. The data pull-down enable signal needs to wait for the "0" on the bit line to be completely established before it is turned on. The pull-down control module, based on the "0" signal on the bit line and under the control of the data pull-down enable signal, turns on the N-type drive transistor switch of the pull-down bit line and turns off the N-type drive transistor switch of the negative bit line.
8. The writing method according to claim 6, characterized in that, The data value includes "1"; When the configuration control module sends data "1", the negative bit line is pulled down to "0" by the data controller. The data pull-down enable signal needs to wait for the "0" on the negative bit line to be fully established before it is enabled. The pull-down control module, based on the "0" signal on the negative bit line and under the control of the data pull-down enable signal, turns on the N-type drive transistor switch of the pull-down negative bit line and turns off the N-type drive transistor switch of the bit line.
9. The writing method according to claim 6, characterized in that, The write enable signal is issued after all data in a frame has been sent. The data pull-down enable signal needs to wait for N cycles to complete until the "0" signal is fully established before it is turned on. N depends on the establishment time of the "0" signal.
10. The writing method according to claim 6, characterized in that, When the pull-down control module receives a "0" signal on the bit line or negative bit line, and opens the N-type drive transistor switch of the bit line or negative bit line corresponding to the pull-down "0" signal under the control of the data pull-down enable signal, and closes the N-type drive transistor switch of the other bit line or negative bit line, the drive on the write path includes the data controller and the pull-down control module.