Schottky integrated super junction device and manufacturing method thereof

Abstract

The invention provides a Schottky integrated super junction device which comprises a substrate, an N-type epitaxial layer is formed on the substrate, P-type columns are formed on the epitaxial layer, and areas between the P-type columns are alternately arranged super junction MOSFET forming areas. A Schottky diode formed by Schottky contact and a substrate is integrated in the super junction MOSFET in parallel, the super junction MOSFET is of a split-gate structure, and a blank space is reserved between the split-gate structures to serve as a Schottky contact area. A well region is formed on the epitaxial layer between the trench gate structure and the P-type column, and a well contact region and a source region are formed on the well region; a Schottky metal layer; the anode of the Schottky diode is located on the Schottky metal layer of the Schottky contact area, and the cathode of the Schottky diode shares the drain electrode of the super junction MOSFET located on the back face of the substrate. According to the invention, the Schottky structure can be formed without additional injection, and adverse effects of an irradiation process on the device can be avoided.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a Schottky integrated super junction device and a manufacturing method thereof. Background Art

[0002] In the prior art super junction device, a built-in electric field exists in the PN junction, and the device is in a reverse current conduction state during recovery.

[0003] For example, see Figure 1 , which shows a Schottky integrated super junction device, comprising:

[0004] A substrate, an N-type epitaxial layer 4 is formed on the substrate, a P-type column 1 is formed on the epitaxial layer 4, and the area between the P-type columns 1 and the P-type columns 1 is an alternately arranged super junction MOSFET formation area;

[0005] A super junction MOSFET is provided in which a Schottky diode formed by a Schottky contact and a substrate is integrated in parallel in the super junction MOSFET, wherein:

[0006] The super junction MOSFET is a gate structure;

[0007] A well region 2 is formed on the epitaxial layer 102 between the trench gate structure and the P-type pillar 101, and a well contact region 7 and a source region 3 are formed on the well region 2;

[0008] Schottky metal layer; the anode of the Schottky diode is located on the Schottky metal layer in the Schottky contact area, and the cathode of the Schottky diode shares the drain electrode of the super junction MOSFET located on the back side of the substrate.

[0009] The existing super junction devices have the following problems:

[0010] (1) The tail current is large;

[0011] (2) It takes a certain amount of time for the PN capacitor to release the charge Qrr, and the switching frequency is limited.

[0012] The solution of the existing technology is to reduce the carrier lifetime through electron irradiation, but the disadvantage is that the stress in the contact hole has a great impact on the leakage after electron irradiation, resulting in Vt (threshold voltage) / BV (breakdown voltage) instability.

[0013] In order to solve the above problems, it is necessary to propose a new type of Schottky integrated super junction device and a manufacturing method thereof. Summary of the invention

[0014] In view of the shortcomings of the prior art mentioned above, the purpose of the present invention is to provide a Schottky integrated super junction device and a method for manufacturing the same, so as to solve the problem in the prior art that the super junction device reduces the carrier lifetime through electron irradiation, but causes the stress in the contact hole to have a great influence on the leakage after electron irradiation, resulting in Vt (threshold voltage) / BV (breakdown voltage) instability.

[0015] To achieve the above objectives and other related objectives, the present invention provides a Schottky integrated super junction device, comprising:

[0016] A substrate, an N-type epitaxial layer is formed on the substrate, a P-type column is formed on the epitaxial layer, and the area between the P-type columns is an alternately arranged super junction MOSFET formation area;

[0017] A super junction MOSFET, in which a Schottky diode formed by a Schottky contact and a substrate is integrated in parallel, wherein:

[0018] The super junction MOSFET is a split gate structure, and a blank space is reserved between the split gate structures as a Schottky contact area;

[0019] A well region is formed on the epitaxial layer between the trench gate structure and the P-type column, and a well contact region and a source region are formed on the well region;

[0020] A Schottky metal layer; an anode of the Schottky diode is located on the Schottky metal layer in the Schottky contact region, and a cathode of the Schottky diode shares a drain electrode of the super junction MOSFET located on the back side of the substrate.

[0021] Preferably, the split-gate structure includes: two first gate trenches formed in the super junction MOSFET formation area, with a blank space reserved between the two first gate trenches as the Schottky contact area; a first gate dielectric layer formed in the first gate trenches and a first gate conductive material layer filling the remaining first gate trenches.

[0022] Preferably, the Schottky metal layer also forms a source and a gate at the same time, and the Schottky metal layer on the P-type column, the well contact area and the source area, and the Schottky diode composed of the N-type epitaxial layer and the Schottky metal layer serve as a source, and the Schottky metal layer on the first gate conductive material layer serves as a gate.

[0023] Preferably, the split-gate structure includes: a second gate trench formed in the super junction MOSFET formation area and a third gate trench outside the P-type column, a second gate dielectric layer formed on the second gate trench, and a side wall formed by etching the second gate conductive material layer is formed on the side wall of the gate trench; a blank space is reserved on the epitaxial layer between the side walls formed by etching the second gate conductive material layer as the Schottky contact area; a third gate dielectric layer in the third gate trench and a third gate conductive material layer filling the remaining third gate trench.

[0024] Preferably, the Schottky metal layer also forms a source, a gate and the Schottky diode at the same time, the Schottky metal layer on the P-type column, the well contact area and the source area serves as a source, and the Schottky metal layer on the third gate conductive material layer serves as a gate.

[0025] Preferably, the first to third gate conductive material layers are made of polysilicon.

[0026] Preferably, the first to third gate dielectric layers are oxide layers.

[0027] Preferably, for the manufacture of devices above 200V, the resistance of the epitaxial layer is greater than 0.4Ω, and a Schottky structure can be formed without additional injection.

[0028] The present invention also provides a method for manufacturing the Schottky integrated super junction device, comprising:

[0029] Step 1: providing a substrate, forming an N-type epitaxial layer on the substrate, forming a P-type column on the epitaxial layer, and the area between the P-type columns is an alternately arranged super junction MOSFET formation area;

[0030] Step 2: forming a super junction MOSFET, in which a Schottky diode formed by a Schottky contact and a substrate is integrated in parallel in the super junction MOSFET, wherein:

[0031] The super junction MOSFET is a split gate structure, and a blank space is reserved between the split gate structures as a Schottky contact area;

[0032] A well region is formed on the epitaxial layer between the trench gate structure and the P-type column, and a well contact region and a source region are formed on the well region;

[0033] Step 3: forming a Schottky metal layer by deposition and patterning;

[0034] The anode of the Schottky diode is located on the Schottky metal layer of the Schottky contact region, and the cathode of the Schottky diode shares the drain electrode of the super junction MOSFET located on the back side of the substrate.

[0035] Preferably, the split-gate structure in step two includes: two first gate trenches formed in the super junction MOSFET formation area, with a blank space reserved between the two first gate trenches as the Schottky contact area; a first gate dielectric layer formed in the first gate trenches and a first gate conductive material layer filling the remaining first gate trenches.

[0036] Preferably, the method for forming the split-gate structure in step two includes: using photolithography and etching methods to simultaneously form two first gate trenches in the super junction MOSFET formation area; sequentially depositing the first gate dielectric layer and the first gate conductive material layer in the first gate trenches; grinding the first gate conductive material layer onto the epitaxial layer; forming a well region by ion implantation, and forming a well contact region and a source region on the well region.

[0037] Preferably, the Schottky metal layer after patterning in step three also forms a source and a gate at the same time, and the Schottky metal layer on the P-type column, the well contact area and the source area, and the Schottky diode composed of the N-type epitaxial layer and the Schottky metal layer jointly form a source contact hole, and the Schottky metal layer on the first gate conductive material layer serves as a gate.

[0038] Preferably, the split-gate structure in step two includes: a second gate trench formed in the super junction MOSFET formation area and a third gate trench outside the P-type column, a second gate dielectric layer formed on the second gate trench, and a side wall formed by etching the second gate conductive material layer is formed on the side wall of the gate trench; a blank space is reserved on the epitaxial layer between the side walls formed by etching the second gate conductive material layer as the Schottky contact area; a third gate dielectric layer in the third gate trench and a third gate conductive material layer filling the remaining third gate trench.

[0039] Preferably, the method for forming the split-gate structure in step two includes: forming a well region by ion implantation, and forming a well contact region and a source region on the well region; forming the second and third gate trenches simultaneously by photolithography and etching methods; forming the second and third gate dielectric layers in the second and third gate trenches by deposition and grinding methods; forming the side walls in the second gate trench and the third gate conductive material layer in the third gate trench by deposition and back etching methods.

[0040] Preferably, the Schottky metal layer patterned in step three also forms a source, a gate and the Schottky diode at the same time, and the Schottky metal layer on the P-type column, the well contact area and the source area and the Schottky diode formed by the N-type epitaxial layer and the Schottky metal layer jointly form a source contact hole, and the Schottky metal layer on the third gate conductive material layer serves as a gate.

[0041] Preferably, the first to third gate conductive material layers are made of polysilicon.

[0042] Preferably, the first to third gate dielectric layers are oxide layers.

[0043] Preferably, for the manufacture of devices above 200V, the resistance of the epitaxial layer is greater than 0.4Ω, and a Schottky structure can be formed without additional injection.

[0044] As described above, the Schottky integrated super junction device and the manufacturing method thereof of the present invention have the following beneficial effects:

[0045] Blank spaces are reserved between the split-gate structures of the present invention as Schottky contact areas; during the reverse recovery process, current reflux is performed through the Schottky tube, which greatly reduces the current tailing problem; for devices above 200V and with a high-resistance epitaxial layer, a Schottky structure can be formed without additional injection, thereby avoiding the adverse effects of the irradiation process on the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Figure 1 Shown is a schematic diagram of a Schottky integrated super junction device of the prior art;

[0047] Figure 2 Shown is a schematic diagram of the process flow of the present invention;

[0048] Figure 3 It is a schematic diagram showing the formation of a P-type column according to the first embodiment of the present invention;

[0049] Figure 4 It is a schematic diagram showing a split-gate structure formed according to a first embodiment of the present invention;

[0050] Figure 5 It is a schematic diagram of ion implantation according to a first embodiment of the present invention;

[0051] Figure 6 Shown is a schematic diagram of a patterned Schottky metal layer according to a first embodiment of the present invention;

[0052] Figure 7 It is a schematic diagram of ion implantation according to a second embodiment of the present invention;

[0053] Figure 8It is a schematic diagram showing the formation of the second and third gate trenches according to the second embodiment of the present invention;

[0054] Fig. 9 It is a schematic diagram showing the formation of a split gate structure and a gate lead-out region structure according to a second embodiment of the present invention;

[0055] Fig.10 It is a schematic diagram of a patterned Schottky metal layer according to a second embodiment of the present invention. DETAILED DESCRIPTION

[0056] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0057] The present invention provides a Schottky integrated super junction device, comprising:

[0058] A substrate, an N-type epitaxial layer 102 is formed on the substrate, a P-type column 101 is formed on the epitaxial layer 102, and the area between the P-type columns 101 and the P-type columns 101 is an alternately arranged super junction MOSFET formation area;

[0059] A super junction MOSFET is provided in which a Schottky diode formed by a Schottky contact and a substrate is integrated in parallel in the super junction MOSFET, wherein:

[0060] The super junction MOSFET has a split gate structure, with blank spaces reserved between the split gate structures as Schottky contact areas;

[0061] A well region 105 is formed on the epitaxial layer 102 between the trench gate structure and the P-type pillar 101 , and a well contact region 107 and a source region 106 are formed on the well region 105 ;

[0062] Schottky metal layer 108; the anode of the Schottky diode is located on the Schottky metal layer 108 in the Schottky contact region, and the cathode of the Schottky diode shares the drain electrode of the super junction MOSFET located on the back side of the substrate.

[0063] In some embodiments, see Figure 5 The split-gate structure includes: two first gate trenches formed in the super junction MOSFET formation area, with a blank space reserved between the two first gate trenches as a Schottky contact area; a first gate dielectric layer formed in the first gate trenches and a first gate conductive material layer 104 filling the remaining first gate trenches.

[0064] In some embodiments, see Figure 6The Schottky metal layer 108 also forms a source and a gate at the same time, wherein the N-type epitaxial layer 102 and the Schottky metal layer 108 form a Schottky diode, the P-type column 101, the well contact area 107, the Schottky metal layer 108 on the source area 106 and the N-type epitaxial layer 102, and the Schottky metal layer 108 on the upper Schottky diode serve as the source, and the Schottky metal layer 108 on the first gate conductive material layer 104 serves as the gate.

[0065] In some embodiments, see Fig. 9 The split-gate structure includes: a second gate trench formed in the super junction MOSFET formation area and a third gate trench outside the P-type column, a second gate dielectric layer 109 is formed on the second gate trench, and a sidewall 110 formed by etching the second gate conductive material layer is formed on the sidewall of the gate trench; a blank space is reserved on the epitaxial layer 102 between the sidewalls 110 formed by etching the second gate conductive material layer as a Schottky contact area; a third gate dielectric layer 111 in the third gate trench and a third gate conductive material layer 112 filling the remaining third gate trench.

[0066] In some embodiments, see Fig.10 The Schottky metal layer 108 also forms a source and a gate at the same time, wherein the N-type epitaxial layer 102 and the Schottky metal layer 108 form a Schottky diode, the P-type column 101, the well contact area 107, the Schottky metal layer 108 on the source area 106 and the N-type epitaxial layer 102, and the Schottky metal layer 108 on the Schottky diode serve as the source, and the Schottky metal layer 108 on the third gate conductive material layer 112 serves as the gate.

[0067] In some embodiments, the material of the first to third gate conductive material layers is polysilicon.

[0068] In some embodiments, the first to third gate dielectric layers are oxide layers.

[0069] In some embodiments, for the manufacture of devices above 200 V, the resistance of the epitaxial layer 102 is greater than 0.4Ω, and a Schottky structure can be formed without additional implantation.

[0070] The present invention also provides a method for manufacturing a Schottky integrated super junction device, comprising:

[0071] Step 1: Provide a substrate, form an N-type epitaxial layer 102 on the substrate, and form a P-type column 101 on the epitaxial layer 102 to form a Figure 3 In the structure shown, the area between the P-type pillars 101 and the P-type pillars 101 is an alternately arranged super junction MOSFET formation area;

[0072] Step 2: forming a super junction MOSFET, integrating a Schottky diode formed by a Schottky contact and a substrate in parallel in the super junction MOSFET, wherein:

[0073] The super junction MOSFET has a split gate structure, with blank spaces reserved between the split gate structures as Schottky contact areas;

[0074] A well region 105 is formed on the epitaxial layer 102 between the trench gate structure and the P-type pillar 101 , and a well contact region 107 and a source region 106 are formed on the well region 105 ;

[0075] In some embodiments, the split-gate structure in step two includes: two first gate trenches formed in the super junction MOSFET formation area, with a blank space reserved between the two first gate trenches as a Schottky contact area; a first gate dielectric layer formed in the first gate trenches and a first gate conductive material layer 104 filling the remaining first gate trenches.

[0076] In some embodiments, the method for forming the split gate structure in step 2 includes: forming two first gate trenches in the super junction MOSFET formation area simultaneously by photolithography and etching; depositing a first gate dielectric layer and a first gate conductive material layer 104 in the first gate trenches in sequence; grinding the first gate conductive material layer 104 onto the epitaxial layer 102 to form a Figure 4 The structure shown; a well region 105 is formed by ion implantation, a well contact region 107 and a source region 106 are formed on the well region 105, and a well contact region 107 and a source region 106 are formed as shown in FIG. Figure 5 The structure shown.

[0077] In some embodiments, the split-gate structure in step two includes: a second gate trench formed in the super junction MOSFET formation area and a third gate trench outside the P-type column 101, a second gate dielectric layer 109 is formed on the second gate trench, and a sidewall 110 formed by etching the second gate conductive material layer is formed on the sidewall of the gate trench; a blank space is reserved on the epitaxial layer 102 between the sidewalls 110 formed by etching the second gate conductive material layer as a Schottky contact area; a third gate dielectric layer 111 in the third gate trench and a third gate conductive material layer 112 filling the remaining third gate trench.

[0078] In some embodiments, the method for forming the split gate structure in step 2 includes: forming a well region 105 by ion implantation, forming a well contact region 107 and a source region 106 on the well region 105, and forming a Figure 7 The structure shown in FIG. 1 is formed by photolithography and etching to form the second and third gate trenches at the same time, forming a structure as shown in FIG. Figure 8The structure shown in FIG. 1 ; forming the second and third gate dielectric layers in the second and second gate trenches by deposition and grinding; forming the sidewall 110 in the second gate trench and the third gate conductive material layer 112 in the third gate trench by deposition and back etching, forming the structure shown in FIG. 1 ; forming the second and third gate dielectric layers by deposition and back etching; forming the sidewall 110 in the second gate trench and the third gate conductive material layer 112 in the third gate trench, forming the structure shown in FIG. Fig. 9 The structure shown.

[0079] Step 3: forming a Schottky metal layer 108 by deposition and patterning;

[0080] The anode of the Schottky diode is located on the Schottky metal layer 108 in the Schottky contact region, and the cathode of the Schottky diode shares the drain electrode of the super junction MOSFET located on the back side of the substrate.

[0081] In some embodiments, see Figure 6 The Schottky metal layer 108 patterned in step three also forms a source and a gate at the same time. The Schottky metal layer 108 also forms a source and a gate at the same time, wherein the N-type epitaxial layer 102 and the Schottky metal layer 108 form a Schottky diode, the P-type column 101, the well contact area 107, the Schottky metal layer 108 on the source area 106 and the Schottky metal layer 108 on the Schottky diode serve as the source, and the Schottky metal layer 108 on the first gate conductive material layer 104 serves as the gate.

[0082] In some embodiments, see Fig.10 The patterned Schottky metal layer 108 in step three also forms a source and a gate at the same time, wherein the N-type epitaxial layer 102 and the Schottky metal layer 108 form a Schottky diode, the P-type column 101, the well contact area 107, the Schottky metal layer 108 on the source area 106 and the Schottky metal layer 108 on the Schottky diode serve as the source, and the Schottky metal layer 108 on the third gate conductive material layer 112 serves as the gate.

[0083] In some embodiments, the material of the first to third gate conductive material layers is polysilicon.

[0084] In some embodiments, the first to third gate dielectric layers are oxide layers.

[0085] In some embodiments, for the manufacture of devices above 200 V, the resistance of the epitaxial layer 102 is greater than 0.4Ω, and a Schottky structure can be formed without additional implantation.

[0086] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner. Therefore, the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0087] In summary, the blank space between the split-gate structures of the present invention is reserved as the Schottky contact area; during the reverse recovery process, the current is refluxed through the Schottky tube, which greatly reduces the current tailing problem; for devices above 200V and high-resistance epitaxial layers, the Schottky structure can be formed without additional injection, which can avoid the adverse effects of the irradiation process on the device. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.

[0088] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A Schottky integrated super junction device, characterized in that: include: A substrate, an N-type epitaxial layer is formed on the substrate, a P-type column is formed on the epitaxial layer, and the area between the P-type columns is an alternately arranged super junction MOSFET formation area; A super junction MOSFET, in which a Schottky diode formed by a Schottky contact and a substrate is integrated in parallel, wherein: The super junction MOSFET is a split gate structure, and a blank space is reserved between the split gate structures as a Schottky contact area; A well region is formed on the epitaxial layer between the trench gate structure and the P-type column, and a well contact region and a source region are formed on the well region; A Schottky metal layer; an anode of the Schottky diode is located on the Schottky metal layer in the Schottky contact region, and a cathode of the Schottky diode shares a drain electrode of the super junction MOSFET located on the back side of the substrate.

2. The Schottky integrated super junction device according to claim 1, characterized in that: The split-gate structure includes: two first gate trenches formed in the super junction MOSFET formation area, with a blank space reserved between the two first gate trenches as the Schottky contact area; a first gate dielectric layer formed in the first gate trenches and a first gate conductive material layer filling the remaining first gate trenches.

3. The Schottky integrated super junction device according to claim 2, characterized in that: The Schottky metal layer also forms a source and a gate at the same time. The P-type column, the Schottky metal layer on the well contact area and the source area, and the Schottky diode composed of the N-type epitaxial layer and the Schottky metal layer, together serve as a source, and the Schottky metal layer on the first gate conductive material layer serves as a gate.

4. The Schottky integrated super junction device according to claim 1, characterized in that: The split-gate structure includes: a second gate trench formed in the super junction MOSFET formation area and a third gate trench outside the P-type column, a second gate dielectric layer formed on the second gate trench, and a side wall formed by etching the second gate conductive material layer is formed on the side wall of the gate trench; a blank space is reserved on the epitaxial layer between the side walls formed by etching the second gate conductive material layer as the Schottky contact area; a third gate dielectric layer in the third gate trench and a third gate conductive material layer filling the remaining third gate trench.

5. The Schottky integrated super junction device according to claim 4, characterized in that: The Schottky metal layer also simultaneously forms a source, a gate and the Schottky diode. The Schottky metal layer on the P-type column, the well contact area and the source area and the Schottky diode formed by the N-type epitaxial layer and the Schottky metal layer serve as a source, and the Schottky metal layer on the third gate conductive material layer serves as a gate.

6. The Schottky integrated super junction device according to claim 2 or 4, characterized in that: The material of the first to third gate conductive material layers is polysilicon.

7. The Schottky integrated super junction device according to claim 2 or 4, characterized in that: The first to third gate dielectric layers are oxide layers.

8. The Schottky integrated super junction device according to claim 1, characterized in that: For the manufacture of devices above 200V, the resistance of the epitaxial layer is greater than 0.4Ω, and a Schottky structure can be formed without additional injection.

9. The method for manufacturing a Schottky integrated super junction device according to any one of claims 1 to 8, characterized in that: At least: Step 1: providing a substrate, forming an N-type epitaxial layer on the substrate, forming a P-type column on the epitaxial layer, and the area between the P-type columns is an alternately arranged super junction MOSFET formation area; Step 2: forming a super junction MOSFET, in which a Schottky diode formed by a Schottky contact and a substrate is integrated in parallel in the super junction MOSFET, wherein: The super junction MOSFET is a split gate structure, and a blank space is reserved between the split gate structures as a Schottky contact area; A well region is formed on the epitaxial layer between the trench gate structure and the P-type column, and a well contact region and a source region are formed on the well region; Step 3: forming a Schottky metal layer by deposition and patterning; The anode of the Schottky diode is located on the Schottky metal layer of the Schottky contact region, and the cathode of the Schottky diode shares the drain electrode of the super junction MOSFET located on the back side of the substrate.

10. The method for manufacturing a Schottky integrated super junction device according to claim 9, characterized in that: The split-gate structure in step two includes: two first gate trenches formed in the super junction MOSFET formation area, with a blank space reserved between the two first gate trenches as the Schottky contact area; a first gate dielectric layer formed in the first gate trenches and a first gate conductive material layer filling the remaining first gate trenches.

11. The method for manufacturing a Schottky integrated super junction device according to claim 10, characterized in that: The method for forming the split-gate structure in step 2 includes: using photolithography and etching methods to simultaneously form two first gate trenches in the super junction MOSFET formation area; sequentially depositing the first gate dielectric layer and the first gate conductive material layer in the first gate trenches; grinding the first gate conductive material layer onto the epitaxial layer; forming a well region by ion implantation, and forming a well contact region and a source region on the well region.

12. The method for manufacturing a Schottky integrated super junction device according to claim 10 or 11, characterized in that: The Schottky metal layer patterned in step three also forms a source and a gate at the same time. The P-type column, the well contact area and the Schottky diode composed of the N-type epitaxial layer and the Schottky metal layer on the source area jointly form a source contact hole, and the Schottky metal layer on the first gate conductive material layer serves as a gate.

13. The method for manufacturing a Schottky integrated super junction device according to claim 9, characterized in that: The split-gate structure in step two includes: a second gate trench formed in the super junction MOSFET formation area and a third gate trench outside the P-type column, a second gate dielectric layer formed on the second gate trench, and a side wall formed by etching the second gate conductive material layer is formed on the side wall of the gate trench; a blank space is reserved on the epitaxial layer between the side walls formed by etching the second gate conductive material layer as the Schottky contact area; a third gate dielectric layer in the third gate trench and a third gate conductive material layer filling the remaining third gate trench.

14. The method for manufacturing a Schottky integrated super junction device according to claim 13, characterized in that: The method for forming the split-gate structure in step 2 includes: forming a well region by ion implantation, and forming a well contact region and a source region on the well region; forming the second and third gate trenches simultaneously by photolithography and etching methods; forming the second and third gate dielectric layers in the second and third gate trenches by deposition and grinding methods; forming the sidewalls in the second gate trench and the third gate conductive material layer in the third gate trench by deposition and back etching methods.

15. The method for manufacturing a Schottky integrated super junction device according to claim 13 or 14, characterized in that: The Schottky metal layer patterned in step three also forms a source, a gate and the Schottky diode at the same time. The Schottky metal layer on the P-type column, the well contact area and the source area and the Schottky diode formed by the N-type epitaxial layer and the Schottky metal layer jointly form a source contact hole, and the Schottky metal layer on the third gate conductive material layer serves as a gate.

16. The method for manufacturing a Schottky integrated super junction device according to claim 10 or 13, characterized in that: The material of the first to third gate conductive material layers is polysilicon.

17. The method for manufacturing a Schottky integrated super junction device according to claim 10 or 13, characterized in that: The first to third gate dielectric layers are oxide layers.

18. The method for manufacturing a Schottky integrated super junction device according to claim 9, characterized in that: For the manufacture of devices above 200V, the resistance of the epitaxial layer is greater than 0.4Ω, and a Schottky structure can be formed without additional injection.

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