Phased-array antenna multi-task test control system based on sequential control

Abstract

The invention discloses a sequential control-based phased-array antenna multi-task test control system, the hardware structure of the system comprises a structural case, a power conversion module and a main control board, the system receives a serial port instruction of a PC (Personal Computer), outputs a frequency code, a wave position code and a switch code according to a timing sequence required by the instruction under the trigger of a scanning frame position trigger pulse, and sends the frequency code, the wave position code and the switch code to the main control board; and synchronously triggering, transmitting conduction and triggering a trigger signal acquired by the vector network. In the design process, external electromagnetic signal interference is fully considered, the closed case is adopted, and external signal radiation can be effectively isolated; the grounding design is safe and reliable; the main control board and the power supply module are in common ground, and are in common ground with the case shell through mounting screws; all input and output signals are provided with reference ground wires and are in common ground with a case.

Description

Technical Field

[0001] The present invention belongs to the field of phased array antennas, and more specifically, particularly relates to a phased array antenna multi-task test control system based on timing control. Background Art

[0002] With the development and widespread application of active phased array radar technology, the scale of phased array antenna systems is becoming larger and larger, the amount of data that needs to be controlled is large, and the phased array antenna has multiple working modes and complex functions. Before these phased array antenna systems are put into formal use, the directional patterns of different antennas need to be verified by the antenna darkroom test system, which takes a long time to test, especially for large-caliber phased array antennas, which are complex to control and have many functions that need to be verified. Before formal testing, it often takes a long time to debug, which will occupy a lot of darkroom resources, resulting in insufficient darkroom space, which seriously affects the progress of project development and production. Therefore, a more scientific and reasonable method is urgently needed to achieve performance testing of phased array antenna systems.

[0003] In the existing technology, most of the multi-task test control systems of phased array antennas have weak anti-external interference capabilities. We propose a multi-task test control system for phased array antennas based on timing control. Summary of the invention

[0004] The purpose of the present invention is to solve the shortcomings of the prior art and propose a phased array antenna multi-task test control system based on timing control. The system adopts a closed chassis to effectively isolate external signal radiation.

[0005] To achieve the above object, the present invention provides the following technical solutions:

[0006] A phased array antenna multi-task test control system based on timing control, the hardware structure of the system includes: a structural chassis, a power conversion module, and a main control board. The system receives PC serial port instructions, and under the triggering of the scanning frame position trigger pulse, outputs frequency code, wave position code, switch code, synchronous trigger, transmission conduction and triggering signal of vector network acquisition according to the timing sequence required by the instruction;

[0007] Software includes:

[0008] Wave control module, radio frequency switch module, the signal between the system and the wave control module and radio frequency switch module is transmitted by RS422 to avoid interference of long-distance transmission signals;

[0009] It also includes: a control module, a beam control module, a timing control module, a radio frequency amplitude and phase analysis module, and a radio frequency signal switching module;

[0010] The control module is connected to the antenna array through the beam control module, and is used to send the parameter control command to the antenna array through the beam control module;

[0011] The timing control module is respectively connected to the RF signal switching module, the beam control module and the RF amplitude and phase analysis module;

[0012] The control module is connected to the RF amplitude and phase analysis module via a network interface, and is used to send parameter setting instructions and test instructions to the RF amplitude and phase analysis module;

[0013] The radio frequency signal switching module is respectively connected to the timing control module and the radio frequency amplitude and phase analysis module, and is used to switch radio frequency signals of different antenna subarrays.

[0014] Preferably, the control module is connected to the timing control module, and is used to generate a signal through the timing control module to switch different channels of the RF signal switching module, and to synchronize the beam control module and the RF amplitude and phase analysis module.

[0015] Preferably, the software also includes:

[0016] The software self-verification module is connected to the control module, the beam control module, the timing control module, the RF amplitude and phase analysis module, and the RF signal switching module through corresponding buses, and is used to realize self-check of the working status of each module in the device.

[0017] Preferably, the system has two functions, remote control and local control, and can be triggered by an external busy signal to generate a collection trigger signal, and can also generate a collection trigger signal according to a fixed period in the local control mode;

[0018] The system supports four test modes: unidirectional forward sequence mode, unidirectional reverse sequence mode, bidirectional row scan mode, and bidirectional column scan mode; the system supports remote command reset, and sends a reset command to the test controller through the host computer. The test controller terminates the current test process, but retains the test command content.

[0019] Preferably, the system acquisition trigger delay and acquisition trigger pulse width can be set through instructions;

[0020] The system sends a synchronization signal, and the AUT samples the wave position and frequency code at the rising edge of the synchronization signal to obtain the current test parameters;

[0021] In addition to timing the test process, the system also sends a command after the test is completed to inform the host computer that the current test is completed, and supports querying whether the current test is completed through commands.

[0022] Preferably, the main control board has a built-in DB50 chip, the DB50 chip frequency code is 8 bits, supports 256 frequency points, and the output frequency code bit number can be trimmed. When the output frequency code bit number is less than 8 bits, the output is in the low position and the high position is invalid;

[0023] The DB50 chip wave code is 8 bits, supporting 256 wave positions. The output wave code bit number can be trimmed. When the output wave code bit number is less than 8 bits, the output is in the low position and the high position is invalid.

[0024] The switch code of DB50 chip switches 4 bits, supports 16 groups of switch states, and the number of output switch code bits can be trimmed. When the number of output switch code bits is less than 4 bits, the output is in the low position and the high position is invalid;

[0025] The frequency code, wave position code and switch code are 20 bits in total, and the 20-bit parallel control bit is controlled according to the agreed frequency code, wave position code and switch code.

[0026] Preferably, a connector is provided on the structural chassis panel, and the side where the power button is located is designated as the front side, and the side where the 220V socket is located is designated as the back side;

[0027] The power module can be selected with an input of 220V and an output of 5V / 3A. The size is about 100mm*80mm. The module has its own fan and does not require additional heat dissipation.

[0028] The main control board uses the FPGA chip as its core, completes all functions required by the system within the FPGA, and is equipped with power conversion, reset, crystal oscillator and other chips as well as required interface chips to convert input and output signals into corresponding interface levels. To ensure the reliability and stability of the system, high-quality chips are selected as much as possible for each type of chip to reduce device failures due to reliability.

[0029] Preferably, the control module is connected to the beam control module and the timing control module respectively through the CPCI bus; the control module is connected to the network port of the RF amplitude and phase analysis module through a LAN network interface; the beam control module includes a telemetry code word readback functional unit; the parameter control command includes: antenna operating mode, polarization mode, repetition frequency, pulse width, and wave control code.

[0030] Technical effects and advantages of the present invention: Compared with the prior art, the phased array antenna multi-task test control system provided by the present invention fully considers the interference of external electromagnetic signals during the design process and adopts the form of a closed chassis, which can effectively isolate the radiation of external signals;

[0031] The grounding design is safe and reliable: the main control board shares the same ground with the power module and the chassis shell through the mounting screws; all input and output signals have reference ground wires and share the same ground with the chassis;

[0032] The signals output to the DUT are in RS422 format, which can effectively suppress the common-mode interference of the outside world on the signal and improve the signal integrity under the condition of cross-chassis transmission;

[0033] The output TTL signal uses a BNC connector, the internal cables are grounded and shielded, and the final shield ground is shared with the chassis shell to achieve a good shielding effect;

[0034] When selecting internal components, high-quality chips are used, and ceramic packaging devices are selected as much as possible, which can effectively reduce the impact of the external environment on the normal operation of the device and extend the service life of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 This is a schematic diagram of the structure of the chassis panel of the present invention;

[0036] Figure 2 Schematic diagram of the installation of components of the main control board of the present invention;

[0037] Figure 3 This is an architecture diagram of a phased array antenna multi-task test control system based on timing control of the present invention;

[0038] Figure 4 This is a pulse forwarding control timing diagram of the present invention;

[0039] Figure 5 This is a one-way control timing diagram of the present invention;

[0040] Figure 6 This is a timing diagram of bidirectional control (odd-numbered rows / columns) of the present invention;

[0041] Figure 7 This is a timing diagram of bidirectional control (even-numbered rows / columns) of the present invention;

[0042] Figure 8 This is the internal trigger timing diagram of the present invention. DETAILED DESCRIPTION

[0043] In order to make the purpose, technical scheme and advantages of the present invention clearer, the present invention is further described in detail below in conjunction with specific embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0044] The present invention provides Figure 1-8 The phased array antenna multi-task test control system based on timing control is shown;

[0045] The hardware structure of the system includes: structural chassis, power conversion module, main control board. The system receives PC serial port instructions, and under the trigger of the scanning frame position trigger pulse, outputs frequency code, wave position code, switch code, synchronous trigger, transmission conduction and trigger signal of vector network acquisition according to the timing sequence required by the instruction;

[0046] Software includes:

[0047] The signal between the wave control module, RF switch module, system and wave control module, RF switch module is transmitted by RS422 to avoid interference of long-distance transmission signals;

[0048] It also includes: a control module, a beam control module, a timing control module, a radio frequency amplitude and phase analysis module, and a radio frequency signal switching module;

[0049] The control module is connected to the antenna array surface through the beam control module, and is used to send the parameter control command to the antenna array surface through the beam control module;

[0050] The timing control module is respectively connected to the radio frequency signal switching module, the beam control module and the radio frequency amplitude and phase analysis module;

[0051] The control module is connected to the RF amplitude and phase analysis module through a network interface, and is used to send parameter setting instructions and test instructions to the RF amplitude and phase analysis module; the control module is connected to the timing control module, and is used to generate a signal through the timing control module to switch different channels of the RF signal switching module, as well as synchronize the beam control module and the RF amplitude and phase analysis module.

[0052] The RF signal switching module is connected to the timing control module and the RF amplitude and phase analysis module respectively, and is used to switch the RF signals of different antenna subarrays. The control module is connected to the beam control module and the timing control module respectively through the CPCI bus; the control module is connected to the network port of the RF amplitude and phase analysis module through the LAN network interface; the beam control module includes a telemetry code word readback function unit; the parameter control commands include: antenna working mode, polarization mode, repetition frequency, pulse width, and wave control code.

[0053] The software also includes:

[0054] The software self-verification module is connected to the control module, the beam control module, the timing control module, the RF amplitude and phase analysis module, and the RF signal switching module through corresponding buses, and is used to realize self-check of the working status of each module in the device.

[0055] It should be noted that the system has two functions, remote control and local control. It can be triggered by an external busy signal to generate a collection trigger signal, and can also generate a collection trigger signal according to a fixed period in the local control mode.

[0056] The system supports four test modes: unidirectional forward sequence mode, unidirectional reverse sequence mode, bidirectional row scan mode, and bidirectional column scan mode; it supports remote command reset, and sends a reset command to the test controller through the host computer. The test controller terminates the current test process, but retains the test command content.

[0057] Furthermore, the external interface of the test controller is as follows: The connectors on the panel are all female, as follows

[0058]

[0059]

[0060]

[0061] It should be noted that in this embodiment, the system acquisition trigger delay and acquisition trigger pulse width can be set through instructions;

[0062] The system sends a synchronization signal, and the AUT samples the wave position and frequency code at the rising edge of the synchronization signal to obtain the current test parameters;

[0063] In addition to timing the test process, the system also sends a command to inform the host computer that the current test is over after the test is completed, and supports querying whether the current test is over through commands.

[0064] The main control board has a built-in DB50 chip. The frequency code of the DB50 chip is 8 bits, supporting 256 frequency points. The output frequency code bit can be trimmed. When the output frequency code bit is less than 8 bits, the output is in the low position and the high position is invalid.

[0065] The DB50 chip wave code is 8 bits, supporting 256 wave positions. The output wave code bit number can be trimmed. When the output wave code bit number is less than 8 bits, the output is in the low position and the high position is invalid.

[0066] The switch code of DB50 chip switches 4 bits, supports 16 groups of switch states, and the number of output switch code bits can be trimmed. When the number of output switch code bits is less than 4 bits, the output is in the low position and the high position is invalid;

[0067] The frequency code, wave position code, and switch code are 20 bits in total, and the 20-bit parallel control bit is controlled according to the agreed frequency code, wave position code, and switch code. The details are as follows:

[0068]

[0069]

[0070]

[0071] Each connector is designed with a wire-swinging style. The lead end is directly welded on the main control board, and the connector end is installed on the surface of the chassis. The lead length will be checked and determined after the main control board is designed and the installation position is fixed.

[0072] The connector is set on the structure chassis panel. The side where the power button is located is the front side, and the side where the 220V socket is located is the back side.

[0073] The power module should have a 220V input and 5V / 3A output. The size is about 100mm*80mm. The module has its own fan and does not require additional heat dissipation.

[0074] The main control board uses FPGA chip as the core, completes all functions required by the system in FPGA, and is equipped with power conversion, reset, crystal oscillator and other chips as well as required interface chips to convert input and output signals into corresponding interface levels. To ensure the reliability and stability of the system, various chips are selected as high-quality as possible to reduce device failures due to reliability.

[0075] As this embodiment needs to be explained:

[0076] In pulse forwarding mode, a position trigger is received and a corresponding acquisition trigger signal is generated according to the set trigger delay and pulse width. In this cycle, the control signals of the switch, wave position and frequency output in this mode remain fixed.

[0077] During one-way testing, trigger timing and wave position output:

[0078] The first beam state starts with the receipt of the position trigger pulse. The acquisition trigger for the vector network and the synchronization trigger for the antenna under test are generated according to the delay parameters in the instruction. The delay can be set within the delay range of [20us, 500ms].

[0079] Starting from the second beam state, the falling edge of the received network loss idle signal is taken as the starting time, and the acquisition trigger for the vector network and the synchronization trigger for the antenna under test are generated according to the delay parameters in the instruction.

[0080] In the case of bidirectional testing, when odd-numbered row / column testing is performed, the test controller outputs frequency code, wave position code, and switch code in the order of command input, from 1 to N.

[0081] In the case of bidirectional testing, when testing even-numbered rows / columns, the test controller outputs frequency code, wave position code, and switch code in the reverse order of the command input, from N to 1;

[0082] During the transmission test, the test controller gives the antenna a transmission on signal so that the antenna can transmit a transmission pulse.

[0083] The interface protocol between the test controller and the host computer is as follows, which includes two types of instructions: the control instructions sent by the computer and the status instructions returned by the test controller.

[0084] In addition, the test controller has the ability to self-test in an independent state. At this time, no external device support is required to complete the basic function self-test of the test controller. When the instruction in Table 1 is sent and the command code is 30, the controller enters the internal trigger mode; the position trigger pulse is generated internally with a period of 1s and a pulse width of 20us. After the position trigger is generated, a network loss idle signal is generated periodically with a period of 2ms and a pulse width of 20us. T0 and T1 parameters can be controlled by instructions. However, they must be less than 2ms. The control code output is also controlled by instructions.

[0085] At this time, it can be triggered by an internal trigger signal to periodically generate output control codes, acquisition triggers, and synchronization trigger signals.

[0086] Finally, it should be noted that the above are only preferred embodiments of the present invention and are not intended to limit the present invention. Although the present invention has been described in detail with reference to the aforementioned embodiments, it is still possible for those skilled in the art to modify the technical solutions described in the aforementioned embodiments or to make equivalent substitutions for some of the technical features therein. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A phased array antenna multi-task test control system based on timing control, characterized in that: The hardware structure of the system includes: a structural chassis, a power conversion module, and a main control board. The system receives PC serial port instructions, and under the triggering of the scanning frame position trigger pulse, outputs frequency code, wave position code, switch code, synchronous triggering, transmission conduction, and triggering signal of vector network acquisition according to the timing sequence required by the instruction; Software includes: Wave control module, radio frequency switch module, the signal between the system and the wave control module and radio frequency switch module is transmitted by RS422 to avoid interference of long-distance transmission signals; It also includes: a control module, a beam control module, a timing control module, a radio frequency amplitude and phase analysis module, and a radio frequency signal switching module; The control module is connected to the antenna array through the beam control module, and is used to send the parameter control command to the antenna array through the beam control module; The timing control module is respectively connected to the RF signal switching module, the beam control module and the RF amplitude and phase analysis module; The control module is connected to the RF amplitude and phase analysis module via a network interface, and is used to send parameter setting instructions and test instructions to the RF amplitude and phase analysis module; The radio frequency signal switching module is respectively connected to the timing control module and the radio frequency amplitude and phase analysis module, and is used to switch radio frequency signals of different antenna subarrays.

2. The phased array antenna multi-task test control system based on timing control according to claim 1 is characterized in that: The control module is connected to the timing control module, and is used to generate a signal through the timing control module to switch different channels of the radio frequency signal switching module, and to synchronize the beam control module and the radio frequency amplitude and phase analysis module.

3. The phased array antenna multi-task test control system based on timing control according to claim 1 is characterized in that: The software also includes: The software self-verification module is connected to the control module, the beam control module, the timing control module, the RF amplitude and phase analysis module, and the RF signal switching module through corresponding buses, and is used to realize self-check of the working status of each module in the device.

4. The phased array antenna multi-task test control system based on timing control according to claim 1 is characterized in that: The system has two functions: remote control and local control. It can be triggered by an external busy signal to generate a collection trigger signal, and can also generate a collection trigger signal according to a fixed period in the local control mode. The system supports four test modes: unidirectional forward sequence mode, unidirectional reverse sequence mode, bidirectional row scan mode, and bidirectional column scan mode; the system supports remote command reset, and sends a reset command to the test controller through the host computer. The test controller terminates the current test process, but retains the test command content.

5. The phased array antenna multi-task test control system based on timing control according to any one of claims 1 to 4, characterized in that: The system acquisition trigger delay and acquisition trigger pulse width can be set through instructions; The system sends a synchronization signal, and the AUT samples the wave position and frequency code at the rising edge of the synchronization signal to obtain the current test parameters; In addition to timing the test process, the system also sends a command after the test is completed to inform the host computer that the current test is completed, and supports querying whether the current test is completed through commands.

6. The phased array antenna multi-task test control system based on timing control according to claim 1, characterized in that: The main control board has a built-in DB50 chip, the DB50 chip frequency code is 8 bits, supports 256 frequency points, and the output frequency code bit can be trimmed. When the output frequency code bit is less than 8 bits, the output is in the low position and the high position is invalid; The DB50 chip wave code is 8 bits, supporting 256 wave positions. The output wave code bit number can be trimmed. When the output wave code bit number is less than 8 bits, the output is in the low position and the high position is invalid. The switch code of DB50 chip switches 4 bits, supports 16 groups of switch states, and the number of output switch code bits can be trimmed. When the number of output switch code bits is less than 4 bits, the output is in the low position and the high position is invalid; The frequency code, wave position code and switch code are 20 bits in total, and the 20-bit parallel control bit is controlled according to the agreed frequency code, wave position code and switch code.

7. The phased array antenna multi-task test control system based on timing control according to claim 1 is characterized in that: The structural chassis panel is provided with a connector, and the side where the power button is located is the front side, and the side where the 220V socket is located is the back side; The power module can be selected with an input of 220V and an output of 5V / 3A. The size is about 100mm*80mm. The module has its own fan and does not require additional heat dissipation. The main control board uses the FPGA chip as its core, completes all functions required by the system within the FPGA, and is equipped with power conversion, reset, crystal oscillator and other chips as well as required interface chips to convert input and output signals into corresponding interface levels. To ensure the reliability and stability of the system, high-quality chips are selected as much as possible for each type of chip to reduce device failures due to reliability.

8. The phased array antenna multi-task test control system based on timing control according to claim 1, characterized in that: The control module is connected to the beam control module and the timing control module respectively through the CPCI bus; the control module is connected to the network port of the radio frequency amplitude and phase analysis module through the LAN network interface; The beam control module includes a telemetry codeword readback functional unit; The parameter control commands include: antenna working mode, polarization mode, repetition frequency, pulse width, and wave control code.

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