RISC-V chip software and hardware collaborative design method, system and product

Abstract

The invention discloses an RISC-V chip software and hardware collaborative design method, system and product. The method comprises the following steps: sequentially performing optimization from an instruction, a memory and parallel computing to a hardware accelerator; according to instruction optimization, the data processing efficiency and the instruction execution speed are improved by designing and adding a special instruction; memory optimization: improving data access efficiency and reducing memory access delay by adjusting a cache structure, introducing a memory prefetching mechanism and designing a memory hierarchical structure; parallel computing optimization: implementing execution of a multi-thread parallel computing task by designing a hardware structure supporting multi-thread parallel execution; and optimizing a hardware accelerator, and designing a special hardware accelerator to meet the requirements of specific calculation tasks. The performance and energy efficiency of the chip can be remarkably improved, a collaborative design strategy is adopted, the system stability and reliability of the chip are improved, an efficient and reliable processor solution is provided for the power industry, and transformation of the power industry to intelligence and digitization is promoted.

Description

Technical Field

[0001] The present invention relates to the field of chip design technology for power business applications, and in particular to a RISC-V chip software and hardware collaborative design method, system and product. Background Art

[0002] With the rapid development of information technology and the digital transformation of the power industry, the demand for high-performance and low-power processor chips continues to increase. Existing processor architectures often face performance bottlenecks and energy consumption issues when dealing with complex data processing and high real-time requirements. RISC-V (Reduced Instruction Set Computer Version Five), as an open instruction set architecture, provides a powerful processor solution for power business applications due to its flexibility and customizability. However, how to fully tap the potential of RISC-V chips in the power business still faces many challenges, including instruction set optimization, memory system optimization, parallel computing optimization, and hardware accelerator design. Summary of the invention

[0003] The purpose of the present invention is to provide a RISC-V chip hardware and software collaborative design method, system and product to address the problems in the above-mentioned prior art, which can significantly improve the performance and energy efficiency of RISC-V chips in power business applications, provide the power industry with efficient and reliable processor solutions, and promote the transformation of the power industry towards intelligence and digitalization.

[0004] In order to achieve the above object, the present invention has the following technical solutions:

[0005] In the first aspect, a RISC-V chip hardware and software co-design method is provided, including optimizing from instructions, memory, parallel computing to hardware accelerator in sequence:

[0006] Instruction optimization, improving data processing efficiency and instruction execution speed by designing and adding dedicated instructions;

[0007] Memory optimization: improve data access efficiency and reduce memory access latency by adjusting cache structure, introducing memory prefetch mechanism and designing memory hierarchy;

[0008] Parallel computing optimization, by designing a hardware structure that supports multi-threaded parallel execution, to achieve the execution of multi-threaded parallel computing tasks;

[0009] Hardware accelerator optimization, design dedicated hardware accelerators to meet the needs of specific computing tasks.

[0010] As a preferred solution, the step of improving data processing efficiency and instruction execution speed by designing and adding dedicated instructions includes:

[0011] Design and add single instruction multiple data SIMD instructions to support simultaneous multi-data operations;

[0012] Design simplified bit operation instructions to simplify the execution process of bit operations.

[0013] As a preferred solution, the steps of designing and adding single instruction multiple data SIMD instructions to support simultaneous multiple data operations include: adding corresponding elements in the vs1 and vs2 registers through vector addition instructions, and storing the results in the vd register.

[0014] As a preferred solution, the design simplifies the bit operation instruction, and the execution process of the simplified bit operation includes:

[0015] Clears the bit at the specified position in the rs1 register and stores the result in the rd register;

[0016] Sets the bit at the specified position in the rs1 register to 1 and stores the result in the rd register.

[0017] As a preferred solution, the step of adjusting the cache structure includes loading data into the rd register, setting the base address to rs1, and the offset to imm, and improving the data cache hit rate and reducing the access delay by adjusting the cache structure and replacement strategy.

[0018] As a preferred solution, the step of introducing a memory prefetch mechanism includes prefetching data located at a base address rs1 plus an offset imm into a cache, and by introducing a memory prefetch mechanism, the data that may be needed is preloaded into the cache according to program execution characteristics.

[0019] As a preferred solution, the step of designing a memory hierarchy structure includes loading the aligned data into the rd register, setting the base address to rs1, and the offset to imm. By designing the memory hierarchy structure, a larger cache capacity or a faster storage medium is used to improve data access efficiency.

[0020] As a preferred solution, the parallel computing optimization step implements the execution of the following multi-threaded parallel computing tasks:

[0021] Start a new thread START_THREAD; load data into register rd LOAD rdrs1 with rs1 as the data address; execute the computing task COMPUTErd; store the computing result STORErd rs2 with rs2 as the result storage address.

[0022] As a preferred solution, the steps of designing a dedicated hardware accelerator to meet the requirements of a specific computing task include:

[0023] Design a dedicated fast Fourier transform hardware accelerator to speed up the calculation process of signal processing;

[0024] Design a dedicated matrix multiplication hardware accelerator to speed up the execution of matrix calculations;

[0025] Design a dedicated data compression hardware accelerator to improve data transmission efficiency and reduce storage space;

[0026] Design dedicated encryption and decryption hardware accelerators to provide data encryption and decryption functions.

[0027] In the second aspect, a RISC-V chip hardware and software co-design system is provided, including an instruction optimization module, a memory optimization module, a parallel computing optimization module and a hardware accelerator optimization module, which respectively perform optimization from instructions, memory, parallel computing to hardware accelerator in sequence:

[0028] Instruction optimization module, used to improve data processing efficiency and instruction execution speed by designing and adding special instructions;

[0029] A memory optimization module is used to improve data access efficiency and reduce memory access latency by adjusting the cache structure, introducing a memory prefetch mechanism, and designing a memory hierarchy;

[0030] The parallel computing optimization module is used to implement the execution of multi-threaded parallel computing tasks by designing a hardware structure that supports multi-threaded parallel execution;

[0031] The hardware accelerator optimization module is used to design dedicated hardware accelerators to meet the needs of specific computing tasks.

[0032] As a preferred solution, the steps of improving data processing efficiency and instruction execution speed by designing and adding special instructions in the instruction optimization module include:

[0033] Design and add single instruction multiple data SIMD instructions to support simultaneous multi-data operations;

[0034] Design simplified bit operation instructions to simplify the execution process of bit operations;

[0035] The steps of designing and adding SIMD instructions to support simultaneous multi-data operations include: adding corresponding elements in vs1 and vs2 registers by means of vector addition instructions, and storing the result in the vd register;

[0036] The design simplifies the bit operation instruction, and the execution process of the simplified bit operation includes:

[0037] Clears the bit at the specified position in the rs1 register and stores the result in the rd register;

[0038] Sets the bit at the specified position in the rs1 register to 1 and stores the result in the rd register.

[0039] As a preferred solution, the step of adjusting the cache structure by the memory optimization module includes loading data into the rd register, setting the base address to rs1 and the offset to imm, and improving the data cache hit rate and reducing the access delay by adjusting the cache structure and the replacement strategy; the step of introducing the memory prefetch mechanism by the memory optimization module includes prefetching the data located at the base address rs1 plus the offset imm into the cache, and loading the data that may be needed into the cache in advance according to the program execution characteristics by introducing the memory prefetch mechanism; the step of designing the memory hierarchy by the memory optimization module includes loading the aligned data into the rd register, setting the base address to rs1 and the offset to imm, and improving the data access efficiency by designing the memory hierarchy and adopting a larger cache capacity or a faster storage medium.

[0040] As a preferred solution, the parallel computing optimization module implements the execution of the following multi-threaded parallel computing tasks:

[0041] Start a new thread START_THREAD; load data into register rd LOAD rdrs1 with rs1 as the data address; execute the computing task COMPUTErd; store the computing result STORErd rs2 with rs2 as the result storage address.

[0042] As a preferred solution, the hardware accelerator optimization module designs a dedicated hardware accelerator to meet the needs of a specific computing task, including the following steps:

[0043] Design a dedicated fast Fourier transform hardware accelerator to speed up the calculation process of signal processing;

[0044] Design a dedicated matrix multiplication hardware accelerator to speed up the execution of matrix calculations;

[0045] Design a dedicated data compression hardware accelerator to improve data transmission efficiency and reduce storage space;

[0046] Design dedicated encryption and decryption hardware accelerators to provide data encryption and decryption functions.

[0047] In a third aspect, an electronic device is provided, comprising a processor and a memory, wherein the processor is used to execute a computer program stored in the memory to implement the RISC-V chip hardware and software collaborative design method.

[0048] In a fourth aspect, a computer-readable storage medium is provided, wherein the computer-readable storage medium stores at least one instruction, and when the at least one instruction is executed by a processor, the RISC-V chip hardware and software collaborative design method is implemented.

[0049] Compared with the prior art, the first aspect of the present invention has at least the following beneficial effects:

[0050] The RISC-V chip software and hardware collaborative design method of the present invention starts from the bottom-level instructions, and optimizes from instructions, memory, parallel computing to hardware accelerators in sequence. Through instruction set optimization, memory system optimization, parallel computing optimization and hardware accelerator design, the performance and energy efficiency of the chip are significantly improved to meet the large-scale data processing needs of the power business. By optimizing the instruction set and memory system, the data processing speed is improved, and the computing power of the chip is enhanced to cope with the increasingly complex data processing needs in the power business. By optimizing the RISC-V chip hardware structure and software algorithm, low-power design is achieved, chip energy consumption is reduced, the service life of the equipment is extended, and the requirements of power equipment for high energy efficiency are met. Through parallel computing optimization and hardware accelerator design, the adaptability of the chip to different application scenarios is improved, ensuring stable operation in various environments. The present invention adopts a collaborative design strategy to improve the system stability and reliability of the chip and ensure efficient operation in the power business. The present invention provides an efficient and reliable processor solution for the power industry, promoting the transformation of the power industry to intelligence and digitalization.

[0051] It can be understood that the beneficial effects of the second to fourth aspects mentioned above can be found in the relevant description of the first aspect mentioned above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0053] Figure 1 Schematic diagram of the working principle of the RISC-V chip according to an embodiment of the present invention;

[0054] Figure 2 A schematic diagram of an embodiment of the present invention implementing parallel computing instruction set expansion for single instruction multiple data (SIMD) instructions;

[0055] Figure 3 Flowchart of execution of instruction code program according to an embodiment of the present invention;

[0056] Figure 4Comparison diagram of the improvement effect of power data processing performance in an embodiment of the present invention;

[0057] Figure 5 A diagram showing changes in power consumption according to an embodiment of the present invention;

[0058] Figure 6 Energy efficiency change diagram of an embodiment of the present invention. DETAILED DESCRIPTION

[0059] In the following description, specific details such as specific system structures, technologies, etc. are provided for the purpose of illustration rather than limitation, so as to provide a thorough understanding of the embodiments of the present application. However, it should be clear to those skilled in the art that the present application may also be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to prevent unnecessary details from obstructing the description of the present application.

[0060] In order to give full play to the potential of RISC-V (Reduced Instruction Set Computer Version Five) chips in the power business, the embodiment of the present invention proposes a RISC-V chip hardware and software collaborative design method, system and product, which optimizes the instruction set, memory system, parallel computing and hardware accelerator in turn. The specific contents include:

[0061] Instruction optimization, improving data processing efficiency and instruction execution speed by designing and adding dedicated instructions;

[0062] Memory optimization: improve data access efficiency and reduce memory access latency by adjusting cache structure, introducing memory prefetch mechanism and designing memory hierarchy;

[0063] Parallel computing optimization, by designing a hardware structure that supports multi-threaded parallel execution, to achieve the execution of multi-threaded parallel computing tasks;

[0064] Hardware accelerator optimization, design dedicated hardware accelerators to meet the needs of specific computing tasks.

[0065] In a possible implementation, the steps of improving data processing efficiency and instruction execution speed by designing and adding dedicated instructions include:

[0066] Design and add single instruction multiple data SIMD instructions to support simultaneous multi-data operations;

[0067] Design simplified bit operation instructions to simplify the execution process of bit operations.

[0068] Furthermore, the steps of designing and adding single instruction multiple data SIMD instructions to support simultaneous multiple data operations include: adding corresponding elements in the vs1 and vs2 registers through vector addition instructions, and storing the results in the vd register, which is expressed in software language as VADD vd vs1 vs2.

[0069] The design simplifies the bit operation instruction, and the execution process of the simplified bit operation includes:

[0070] Clear the bit at the specified position in the rs1 register and store the result in the rd register. The software language expression is BCLR rd rs1 imm.

[0071] Set the bit at the specified position in the rs1 register to 1 and store the result in the rd register. The software language expression is BSET rd rs1 imm.

[0072] In a possible implementation, the step of adjusting the cache structure includes:

[0073] Load data into the rd register, set the base address to rs1, the offset to imm, and express it in software language as LOADrd rs1 imm. By adjusting the cache structure and replacement strategy, the data cache hit rate can be improved and the access delay can be reduced.

[0074] In a possible implementation, the step of introducing a memory prefetch mechanism includes:

[0075] The data located at the base address rs1 plus the offset imm is prefetched into the cache, which is expressed in software language as PREFETCHrs1imm. By introducing the memory prefetch mechanism, the data that may be needed can be loaded into the cache in advance according to the program execution characteristics.

[0076] In a possible implementation, the step of designing a memory hierarchy includes:

[0077] Load the aligned data into the rd register, set the base address to rs1, and the offset to imm, which is expressed in software language as LOAD_ALIGNED rd rs1 imm. By designing the memory hierarchy, for example, using a larger cache capacity or a faster storage medium, the data access efficiency can be improved.

[0078] In a possible implementation, the parallel computing optimization step designs a hardware structure that supports multi-threaded parallel execution, optimizes the code generated by the compiler, and implements the execution of multi-threaded parallel computing tasks.

[0079] For example, implement the following multi-threaded parallel computing tasks:

[0080] START_THREAD (start a new thread); LOAD rd rs1 (load data into the rd register, rs1 is the data address); COMPUTERd (execute the calculation task); STORErd rs2 (store the calculation result, rs2 is the result storage address).

[0081] In a possible implementation, the step of designing a dedicated hardware accelerator to meet the requirements of a specific computing task includes:

[0082] 1) Design a dedicated Fast Fourier Transform (FFT) hardware accelerator to accelerate the calculation process of signal processing;

[0083] Run the fast Fourier transform FFT hardware accelerator, rs1 is the input data address, rs2 is the output data address, rs3 is the accelerator control register, and the software language expression is RUN_FFT_ACCELERATOR(rs1 rs2 rs3).

[0084] 2) Design a dedicated matrix multiplication hardware accelerator to speed up the execution of matrix calculations;

[0085] Run the matrix multiplication hardware accelerator, rs1 is the address of matrix A, rs2 is the address of matrix B, rs3 is the address of matrix C, rs4 is the accelerator control register, and the software language is expressed as:

[0086] RUN_MATRIX_MULTIPLICATION_ACCELERATOR(rs1 rs2 rs3 rs4).

[0087] 3) Design a dedicated data compression hardware accelerator to improve data transmission efficiency and reduce storage space;

[0088] Run the data compression hardware accelerator, rs1 is the input data address, rs2 is the output data address, and the software language expression is: RUN_COMPRESSION_ACCELERATOR(rs1 rs2).

[0089] 4) Design dedicated encryption and decryption hardware accelerators to provide data encryption and decryption functions.

[0090] Run the encryption and decryption hardware accelerator, rs1 is the input data address, rs2 is the output data address, rs3 is the accelerator control register, and the software language expression is: RUN_CRYPTOGRAPHY_ACCELERATOR(rs1 rs2 rs3).

[0091] See also Figures 1 to 3In an actual power business application scenario, the embodiment of the present invention uses RISC-V chips for real-time monitoring and data processing of power systems. Since the power system needs to process a large amount of real-time data streams, including data collection, cleaning, analysis, and visualization, real-time monitoring and analysis of the power system can be achieved. By implementing the RISC-V chip software and hardware collaborative design method of the embodiment of the present invention, the processing speed and energy efficiency of the system can be significantly improved. The specific implementation is as follows:

[0092] 1. Data acquisition: Utilize the designed SIMD (single instruction multiple data) instructions (such as vector addition VADD) and memory system optimization strategies to improve the efficiency of data acquisition and storage and reduce the delay of data transmission and storage.

[0093] 2. Data cleaning: By designing simplified bit operation instructions (such as bit clear BCLR and bit set BSET), the data cleaning process is accelerated and the accuracy and speed of data processing are improved. The BCLR (bit clear) instruction is used to clear the specified position (that is, set the bit to 0). Two parameters are usually required: one is the register or memory address to be modified, and the other is the index (or position) of the bit to be cleared. After executing this instruction, the bit at the specified position will be set to 0, while the other bits in the register or memory address remain unchanged. The BSET (bit set) instruction is used to set the specified position to 1 (that is, set the bit to the active state). Two parameters are also required: the target register or memory address and the index of the bit to be set. After executing this instruction, the bit at the specified position will be set to 1, and the other bits in the register or memory address will not be affected.

[0094] 3. Data analysis: Utilize parallel computing optimization strategies and hardware accelerators (such as fast Fourier transform FFT and matrix multiplication accelerator) to achieve rapid analysis and processing of large-scale data and improve the efficiency of data analysis.

[0095] 4. Visual display: By designing an efficient memory prefetch mechanism and an optimized instruction set, we ensure fast loading and real-time display of data, improving the system's response speed and user experience.

[0096] See also Figures 4 to 6 , simulate the baseline design and the optimized design separately in the same simulation environment. Measure and compare the performance of the baseline design and the optimized design in power data processing applications, including processing speed and response time. Analyze and compare the energy efficiency indicators of the baseline design and the optimized design, such as power consumption, energy efficiency, and area efficiency.

[0097] Through the optimal embodiments of the above-mentioned specific applications, it can be verified that the RISC-V chip hardware and software collaborative design method of the present invention has significant effects in improving performance, reducing power consumption and meeting power data processing requirements.

[0098] The RISC-V chip software and hardware co-design method for power business applications proposed in the present invention significantly improves the performance and energy efficiency of the chip by optimizing the instruction set, memory system, parallel computing, and hardware accelerator design, and meets the large-scale data processing requirements of the power business. The RISC-V chip software and hardware co-design method of the present invention provides an efficient and reliable processor solution for the power industry, which has important application value and promotion prospects.

[0099] The RISC-V chip software and hardware co-design method for power business applications of the present invention starts from the bottom-level instructions. First, the instruction set is optimized: by designing and adding special instructions (such as SIMD instructions and bit operation instructions) to improve data processing efficiency and instruction execution speed. Secondly, the memory system is optimized: by adjusting the cache structure, introducing a memory prefetch mechanism and designing an appropriate memory hierarchy, the data access efficiency is improved and the memory access delay is reduced. After that, parallel computing optimization is performed: by designing a hardware structure that supports multi-threading and SIMD parallel computing, multiple data elements are implemented to perform the same operation at the same time, and the execution of parallel computing tasks is optimized. Finally, the hardware accelerator design is completed: a dedicated hardware accelerator (such as an FFT accelerator, a matrix multiplication accelerator, a data compression accelerator and an encryption and decryption accelerator) is designed to provide efficient acceleration processing to meet the needs of specific computing tasks. In the RISC-V chip software and hardware co-design method of the present invention, a software and hardware co-design strategy is adopted: through the close combination of software and hardware, performance optimization and energy efficiency are achieved, and the overall performance and stability of the system are improved.

[0100] The RISC-V chip hardware and software collaborative design method of the present invention can improve chip performance: by optimizing the instruction set and memory system, the data processing speed is increased, and the computing power of the chip is enhanced to cope with the increasingly complex data processing needs in the power business. Reduce power consumption: by optimizing the hardware structure and software algorithm, low-power design is achieved, chip energy consumption is reduced, the service life of the equipment is extended, and the requirements of power equipment for high energy efficiency are met. Enhance adaptability: through parallel computing optimization and hardware accelerator design, the chip's adaptability to different application scenarios is improved to ensure stable operation in various environments. Improve reliability: through collaborative design strategies, the system stability and reliability of the chip are improved to ensure efficient operation in the power business.

[0101] Another embodiment of the present invention further proposes a RISC-V chip hardware and software co-design system, including an instruction optimization module, a memory optimization module, a parallel computing optimization module and a hardware accelerator optimization module, which respectively perform optimization from instructions, memory, parallel computing to hardware accelerator in sequence:

[0102] Instruction optimization module, used to improve data processing efficiency and instruction execution speed by designing and adding special instructions;

[0103] A memory optimization module is used to improve data access efficiency and reduce memory access latency by adjusting the cache structure, introducing a memory prefetch mechanism, and designing a memory hierarchy;

[0104] The parallel computing optimization module is used to implement the execution of multi-threaded parallel computing tasks by designing a hardware structure that supports multi-threaded parallel execution;

[0105] The hardware accelerator optimization module is used to design dedicated hardware accelerators to meet the needs of specific computing tasks.

[0106] In a possible implementation, the step of the instruction optimization module improving data processing efficiency and instruction execution speed by designing and adding special instructions includes:

[0107] Design and add single instruction multiple data SIMD instructions to support simultaneous multi-data operations;

[0108] Design simplified bit operation instructions to simplify the execution process of bit operations;

[0109] The steps of designing and adding SIMD instructions to support simultaneous multi-data operations include: adding corresponding elements in vs1 and vs2 registers by means of vector addition instructions, and storing the result in the vd register;

[0110] The design simplifies the bit operation instruction, and the execution process of the simplified bit operation includes:

[0111] Clears the bit at the specified position in the rs1 register and stores the result in the rd register;

[0112] Sets the bit at the specified position in the rs1 register to 1 and stores the result in the rd register.

[0113] In a possible implementation, the step of adjusting the cache structure by the memory optimization module includes loading data into the rd register, setting the base address to rs1 and the offset to imm, and improving the data cache hit rate and reducing the access delay by adjusting the cache structure and the replacement strategy; the step of introducing the memory prefetch mechanism by the memory optimization module includes prefetching the data located at the base address rs1 plus the offset imm into the cache, and loading the data that may be needed into the cache in advance according to the program execution characteristics by introducing the memory prefetch mechanism; the step of designing the memory hierarchy by the memory optimization module includes loading the aligned data into the rd register, setting the base address to rs1 and the offset to imm, and improving the data access efficiency by designing the memory hierarchy and adopting a larger cache capacity or a faster storage medium.

[0114] In a possible implementation, the parallel computing optimization module implements the execution of the following multi-threaded parallel computing tasks:

[0115] Start a new thread START_THREAD; load data into register rd LOAD rdrs1 with rs1 as the data address; execute the computing task COMPUTErd; store the computing result STORErd rs2 with rs2 as the result storage address.

[0116] In a possible implementation, the step of the hardware accelerator optimization module designing a dedicated hardware accelerator to meet the requirements of a specific computing task includes:

[0117] Design a dedicated fast Fourier transform hardware accelerator to speed up the calculation process of signal processing;

[0118] Design a dedicated matrix multiplication hardware accelerator to speed up the execution of matrix calculations;

[0119] Design a dedicated data compression hardware accelerator to improve data transmission efficiency and reduce storage space;

[0120] Design dedicated encryption and decryption hardware accelerators to provide data encryption and decryption functions.

[0121] Another embodiment of the present invention further proposes an electronic device, comprising a processor and a memory, wherein the processor is used to execute a computer program stored in the memory to implement the RISC-V chip hardware and software collaborative design method.

[0122] Another embodiment of the present invention further proposes a computer-readable storage medium, wherein the computer-readable storage medium stores at least one instruction, and when the at least one instruction is executed by a processor, the RISC-V chip hardware and software collaborative design method is implemented.

[0123] The computer program includes computer program code, which may be in source code form, object code form, executable file or some intermediate form. The computer-readable storage medium may include: any entity or device, medium, USB flash drive, mobile hard disk, disk, optical disk, computer memory, read-only memory, random access memory, electric carrier signal, telecommunication signal and software distribution medium, etc. that can carry the computer program code. It should be noted that the content contained in the computer-readable medium can be appropriately increased or decreased according to the requirements of legislation and patent practice in the jurisdiction. For example, in some jurisdictions, according to legislation and patent practice, computer-readable media do not include electric carrier signals and telecommunication signals. For ease of explanation, the above content only shows the part related to the embodiment of the present invention. For specific technical details not disclosed, please refer to the method part of the embodiment of the present invention. The computer-readable storage medium is non-temporary and can be stored in a storage device formed by various electronic devices, which can realize the execution process recorded in the method of the embodiment of the present invention.

[0124] It will be appreciated by those skilled in the art that embodiments of the present invention may be provided as methods, systems or computer program products. Therefore, the present invention may take the form of a complete hardware embodiment, a complete software embodiment or an embodiment combining software and hardware. Moreover, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0125] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (systems) and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the process in the flowchart. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0126] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0127] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0128] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, ordinary technicians in the relevant field should understand that the specific implementation methods of the present invention can still be modified or replaced by equivalents. Any modification or equivalent replacement that does not depart from the spirit and scope of the present invention should be covered within the scope of protection of the claims of the present invention.

Claims

1. A RISC-V chip hardware and software collaborative design method, characterized in that: This includes optimization from instructions, memory, parallel computing to hardware accelerators: Instruction optimization, improving data processing efficiency and instruction execution speed by designing and adding dedicated instructions; Memory optimization: improve data access efficiency and reduce memory access latency by adjusting cache structure, introducing memory prefetch mechanism and designing memory hierarchy; Parallel computing optimization, by designing a hardware structure that supports multi-threaded parallel execution, to achieve the execution of multi-threaded parallel computing tasks; Hardware accelerator optimization, design dedicated hardware accelerators to meet the needs of specific computing tasks.

2. The RISC-V chip hardware and software collaborative design method according to claim 1, characterized in that: The steps of improving data processing efficiency and instruction execution speed by designing and adding special instructions include: Design and add single instruction multiple data SIMD instructions to support simultaneous multi-data operations; Design simplified bit operation instructions to simplify the execution process of bit operations.

3. The RISC-V chip hardware and software collaborative design method according to claim 2, characterized in that: The steps of designing and adding SIMD instructions to support simultaneous multi-data operations include: adding corresponding elements in vs1 and vs2 registers through vector addition instructions, and storing the results in the vd register.

4. The RISC-V chip hardware and software collaborative design method according to claim 2, characterized in that: The design simplifies the bit operation instruction, and the execution process of the simplified bit operation includes: Clears the bit at the specified position in the rs1 register and stores the result in the rd register; Sets the bit at the specified position in the rs1 register to 1 and stores the result in the rd register.

5. The RISC-V chip hardware and software collaborative design method according to claim 1, characterized in that: The step of adjusting the cache structure includes loading data into the rd register, setting the base address to rs1, and the offset to imm, and improving the data cache hit rate and reducing the access delay by adjusting the cache structure and replacement strategy.

6. The RISC-V chip software and hardware collaborative design method according to claim 5, characterized in that: The step of introducing the memory prefetch mechanism includes prefetching data at the base address rs1 plus the offset imm into the cache, and loading the data that may be needed into the cache in advance according to the program execution characteristics by introducing the memory prefetch mechanism.

7. The RISC-V chip hardware and software collaborative design method according to claim 6, characterized in that: The step of designing the memory hierarchy structure includes loading the aligned data into the rd register, setting the base address to rs1 and the offset to imm, and improving the data access efficiency by designing the memory hierarchy structure and adopting a larger cache capacity or a faster storage medium.

8. The RISC-V chip hardware and software collaborative design method according to claim 1, characterized in that: The parallel computing optimization step implements the execution of the following multi-threaded parallel computing tasks: Start a new thread START_THREAD; load data into register rd LOAD rd rs1 with rs1 as the data address; execute the computing task COMPUTErd; store the computing result STORErd rs2 with rs2 as the result storage address.

9. The RISC-V chip hardware and software collaborative design method according to claim 1, characterized in that: The steps of designing a dedicated hardware accelerator to meet the requirements of a specific computing task include: Design a dedicated fast Fourier transform hardware accelerator to speed up the calculation process of signal processing; Design a dedicated matrix multiplication hardware accelerator to speed up the execution of matrix calculations; Design a dedicated data compression hardware accelerator to improve data transmission efficiency and reduce storage space; Design dedicated encryption and decryption hardware accelerators to provide data encryption and decryption functions.

10. A RISC-V chip hardware and software collaborative design system, characterized in that: It includes instruction optimization module, memory optimization module, parallel computing optimization module and hardware accelerator optimization module, which respectively perform optimization from instruction, memory, parallel computing to hardware accelerator: Instruction optimization module, used to improve data processing efficiency and instruction execution speed by designing and adding special instructions; A memory optimization module is used to improve data access efficiency and reduce memory access latency by adjusting the cache structure, introducing a memory prefetch mechanism, and designing a memory hierarchy; The parallel computing optimization module is used to implement the execution of multi-threaded parallel computing tasks by designing a hardware structure that supports multi-threaded parallel execution; The hardware accelerator optimization module is used to design dedicated hardware accelerators to meet the needs of specific computing tasks.

11. The RISC-V chip hardware and software collaborative design system according to claim 10, characterized in that: The steps of improving data processing efficiency and instruction execution speed by designing and adding special instructions in the instruction optimization module include: Design and add single instruction multiple data SIMD instructions to support simultaneous multi-data operations; Design simplified bit operation instructions to simplify the execution process of bit operations; The steps of designing and adding SIMD instructions to support simultaneous multi-data operations include: adding corresponding elements in vs1 and vs2 registers by means of vector addition instructions, and storing the result in the vd register; The design simplifies the bit operation instruction, and the execution process of the simplified bit operation includes: Clears the bit at the specified position in the rs1 register and stores the result in the rd register; Sets the bit at the specified position in the rs1 register to 1 and stores the result in the rd register.

12. The RISC-V chip hardware and software collaborative design system according to claim 10, characterized in that: The step of adjusting the cache structure by the memory optimization module includes loading data into the rd register, setting the base address to rs1 and the offset to imm, and improving the data cache hit rate and reducing the access delay by adjusting the cache structure and the replacement strategy; the step of introducing the memory prefetch mechanism by the memory optimization module includes prefetching the data located at the base address rs1 plus the offset imm into the cache, and loading the data that may be needed into the cache in advance according to the program execution characteristics by introducing the memory prefetch mechanism; The step of designing the memory hierarchy by the memory optimization module includes loading the aligned data into the rd register, setting the base address to rs1 and the offset to imm, and improving the data access efficiency by designing the memory hierarchy and adopting a larger cache capacity or a faster storage medium.

13. The RISC-V chip hardware and software collaborative design system according to claim 10, characterized in that: The parallel computing optimization module implements the execution of the following multi-threaded parallel computing tasks: Start a new thread START_THREAD; load data into register rd LOAD rd rs1 with rs1 as the data address; execute the computing task COMPUTErd; store the computing result STORErd rs2 with rs2 as the result storage address.

14. The RISC-V chip hardware and software collaborative design system according to claim 10, characterized in that: The hardware accelerator optimization module designs a dedicated hardware accelerator to meet the needs of a specific computing task, including the following steps: Design a dedicated fast Fourier transform hardware accelerator to speed up the calculation process of signal processing; Design a dedicated matrix multiplication hardware accelerator to speed up the execution of matrix calculations; Design a dedicated data compression hardware accelerator to improve data transmission efficiency and reduce storage space; Design dedicated encryption and decryption hardware accelerators to provide data encryption and decryption functions.

15. An electronic device, characterized in that: It comprises a processor and a memory, wherein the processor is used to execute a computer program stored in the memory to implement the RISC-V chip hardware and software collaborative design method as described in any one of claims 1 to 9.

16. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores at least one instruction, and when the at least one instruction is executed by the processor, it implements the RISC-V chip hardware and software collaborative design method according to any one of claims 1 to 9.

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