Instruction verification method, device, electronic device and storage medium

Abstract

An embodiment of the present application provides an instruction verification method, device, electronic device and storage medium, the method comprising: obtaining an instruction set to be verified; performing directed testing and random testing on the instruction set to be verified, respectively, to obtain an assembly file corresponding to the instruction set to be verified; using preset simulation software and the assembly file corresponding to the instruction set to be verified, to determine a verification result corresponding to the instruction set to be verified. In an embodiment of the present application, directed testing and random testing are performed on the instruction set to be verified, wherein the directed test is used to test special functions of the set, and the random verification method can randomly verify the loop depth, number of loops, and instructions within the loop body. The instruction verification method provided by the present application has good scalability and reusability, and can meet the needs of related verification system upgrades brought about by future adjustments to the number of loop instructions, loop depth, etc.

Description

Technical Field

[0001] The present application relates to the field of chip testing technology, and in particular to an instruction verification method, device, electronic device and storage medium. Background Art

[0002] With the continuous development of chip technology, the structure and functions of chips are becoming more and more complex. Various different programs need to be downloaded into the chip. These programs include various different instruction sets. Before the chip leaves the factory, the chip hardware and programs need to be tested. However, there is currently no specific solution in the existing technology to test the instruction set in the chip. Therefore, how to quickly verify the instruction set in the chip and thus ensure the stability of the chip function is a problem that needs to be solved urgently. Summary of the Invention

[0003] The purpose of some embodiments of the present application is to provide an instruction verification method, device, electronic device and storage medium. Through the technical solutions of the embodiments of the present application, an instruction set to be verified is obtained; the instruction set to be verified is subjected to directed testing and random testing respectively to obtain an assembly file corresponding to the instruction set to be verified; and preset simulation software and the assembly file corresponding to the instruction set to be verified are used to determine the verification result corresponding to the instruction set to be verified. In the embodiments of the present application, directed testing and random testing are performed on the instruction set to be verified, wherein the directed test is used to test the special functions of the set, and the random verification method can randomly verify the loop depth, number of loops, and instructions in the loop body. The instruction verification method provided by the present application has good scalability and reusability, and can meet the needs of related verification system upgrades brought about by future adjustments to the number of loop instructions, loop depth, etc.

[0004] In a first aspect, some embodiments of the present application provide an instruction verification method, including:

[0005] Get the instruction set to be verified;

[0006] Performing a directed test and a random test on the instruction set to be verified respectively to obtain an assembly file corresponding to the instruction set to be verified;

[0007] A verification result corresponding to the instruction set to be verified is determined by using preset simulation software and an assembly file corresponding to the instruction set to be verified.

[0008] Some embodiments of the present application perform directed testing and random testing on the instruction set to be verified, wherein the directed test is used to test the special functions of the set, and the random verification method can randomly verify the loop depth, number of loops, and instructions within the loop body. The instruction verification method provided by the present application has good scalability and reusability, and can meet the needs of related verification system upgrades brought about by future adjustments to the number of loop instructions, loop depth, etc.

[0009] Optionally, the performing a directed test on the instruction set to be verified includes:

[0010] A preset directed test case is used to verify the preset functions of the instruction set to be verified, wherein the preset functions of the instruction set to be verified include at least whether a branch instruction is included in the loop body, whether the loop body triggers an interrupt, and boundary testing, and the boundary testing includes at least one or more of the maximum number of loops, the minimum number of loops, the maximum loop depth, and the minimum loop depth.

[0011] Some embodiments of the present application use preset directional test cases to test the interruption and exception triggered by the loop body, and also perform directional verification on boundary conditions such as the maximum and minimum values ​​of the number of loop times / depth.

[0012] Optionally, the performing random testing on the instruction set to be verified includes:

[0013] Testing each instruction function in the instruction set to be verified to obtain a test result;

[0014] Comparing the test result with a preset verification result corresponding to the instruction function to obtain a comparison result;

[0015] The test result, the preset verification result and the comparison result are saved in an assembly file.

[0016] Some embodiments of the present application set random constraints in the main function, generate loop body instructions according to the number of loops, output the randomly generated instructions to the assembly file (testcase.S), and calculate the final result by calling each instruction function in the main function, output it to the corresponding assembly file, and finally output the comparison instruction of the instruction calculation result with the C++ calculation result to the assembly file.

[0017] Optionally, the using preset simulation software and an assembly file corresponding to the instruction set to be verified to determine a verification result corresponding to the instruction set to be verified includes:

[0018] Compiling an assembly file corresponding to the instruction set to be verified using a preset compiler to obtain a disassembly file corresponding to the assembly file;

[0019] The disassembled file is simulated using preset simulation software to obtain a verification result corresponding to the instruction set to be verified.

[0020] In some embodiments of the present application, an instruction compiler is used to compile an assembly file to generate corresponding disassembly and data files, etc., and preset simulation software is used to simulate the disassembly file to obtain a verification result corresponding to the instruction set to be verified. In this way, the verification result of the instruction set to be verified can be clearly understood.

[0021] Optionally, the method further includes:

[0022] The disassembly file is stored in a storage unit.

[0023] Some embodiments of the present application execute simulation scripts of a simulation platform, initialize data files to storage units, and the kernel fetches instructions from the storage units to execute instructions, and finally outputs execution results.

[0024] In a second aspect, some embodiments of the present application provide an instruction verification device, including:

[0025] An acquisition module, used to obtain the instruction set to be verified;

[0026] A testing module, configured to perform a directed test and a random test on the instruction set to be verified, respectively, to obtain an assembly file corresponding to the instruction set to be verified;

[0027] The simulation module is used to use preset simulation software and an assembly file corresponding to the instruction set to be verified to determine a verification result corresponding to the instruction set to be verified.

[0028] Some embodiments of the present application perform directed testing and random testing on the instruction set to be verified, wherein the directed test is used to test the special functions of the set, and the random verification method can randomly verify the loop depth, number of loops, and instructions within the loop body. The instruction verification method provided by the present application has good scalability and reusability, and can meet the needs of related verification system upgrades brought about by future adjustments to the number of loop instructions, loop depth, etc.

[0029] Optionally, the testing module is used to:

[0030] A preset directed test case is used to verify the preset functions of the instruction set to be verified, wherein the preset functions of the instruction set to be verified include at least whether a branch instruction is included in the loop body, whether the loop body triggers an interrupt, and boundary testing, and the boundary testing includes at least one or more of the maximum number of loops, the minimum number of loops, the maximum loop depth, and the minimum loop depth.

[0031] Some embodiments of the present application use preset directional test cases to test the interruption and exception triggered by the loop body, and also perform directional verification on boundary conditions such as the maximum and minimum values ​​of the number of loop times / depth.

[0032] Optionally, the testing module is used to:

[0033] Testing each instruction function in the instruction set to be verified to obtain a test result;

[0034] Comparing the test result with a preset verification result corresponding to the instruction function to obtain a comparison result;

[0035] The test result, the preset verification result and the comparison result are saved in an assembly file.

[0036] Some embodiments of the present application set random constraints in the main function, generate loop body instructions according to the number of loops, output the randomly generated instructions to the assembly file (testcase.S), and calculate the final result by calling each instruction function in the main function, output it to the corresponding assembly file, and finally output the comparison instruction of the instruction calculation result with the C++ calculation result to the assembly file.

[0037] Optionally, the simulation module is used to:

[0038] Compiling an assembly file corresponding to the instruction set to be verified using a preset compiler to obtain a disassembly file corresponding to the assembly file;

[0039] The disassembled file is simulated using preset simulation software to obtain a verification result corresponding to the instruction set to be verified.

[0040] In some embodiments of the present application, an instruction compiler is used to compile an assembly file to generate corresponding disassembly and data files, etc., and preset simulation software is used to simulate the disassembly file to obtain a verification result corresponding to the instruction set to be verified. In this way, the verification result of the instruction set to be verified can be clearly understood.

[0041] Optionally, the simulation module is used to:

[0042] The disassembly file is stored in a storage unit.

[0043] Some embodiments of the present application execute simulation scripts of a simulation platform, initialize data files to storage units, and the kernel fetches instructions from the storage units to execute instructions, and finally outputs execution results.

[0044] In a third aspect, some embodiments of the present application provide an electronic device comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, wherein when the processor executes the program, the instruction verification method as described in any embodiment of the first aspect may be implemented.

[0045] In a fourth aspect, some embodiments of the present application provide a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, can implement the instruction verification method as described in any embodiment of the first aspect.

[0046] In a fifth aspect, some embodiments of the present application provide a computer program product, comprising a computer program, wherein when the computer program is executed by a processor, the instruction verification method as described in any embodiment of the first aspect can be implemented. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] In order to more clearly illustrate the technical solutions of some embodiments of the present application, the following is a brief introduction to the drawings required for use in some embodiments of the present application. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without paying any creative work.

[0048] Figure 1 A flowchart of an instruction verification method provided in an embodiment of the present application;

[0049] Figure 2 A flowchart of another instruction verification method provided in an embodiment of the present application;

[0050] Figure 3 A schematic diagram of the structure of an instruction verification device provided in an embodiment of the present application;

[0051] Figure 4 A schematic diagram of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0052] The technical solutions in some embodiments of the present application will be described below in conjunction with the drawings in some embodiments of the present application.

[0053] It should be noted that similar reference numerals and letters represent similar items in the following drawings. Therefore, once an item is defined in one drawing, it does not need to be further defined or explained in subsequent drawings. At the same time, in the description of this application, the terms "first", "second", etc. are only used to distinguish the description and should not be understood as indicating or implying relative importance.

[0054] With the continuous development of chip technology, the structure and function of chips are becoming more and more complex. Various different programs need to be downloaded into the chip, and these programs include various different instruction sets. Before the chip leaves the factory, the chip hardware and programs need to be tested. However, there is no specific solution in the existing technology to test the instruction set in the chip. Therefore, how to quickly verify the instruction set in the chip and thus ensure the stability of the chip function is a problem that is urgently needed to be solved. In view of this, some embodiments of the present application provide an instruction verification method, which includes obtaining an instruction set to be verified; performing directed testing and random testing on the instruction set to be verified to obtain an assembly file corresponding to the instruction set to be verified; using preset simulation software and the assembly file corresponding to the instruction set to be verified to determine the verification result corresponding to the instruction set to be verified. In the embodiments of the present application, directed testing and random testing are performed on the instruction set to be verified, wherein the directed test is used to test the special functions of the set, and the random verification method can randomly verify the loop depth, number of loops, and instructions in the loop body. The instruction verification method provided by the present application has good scalability and reusability, and can meet the needs of related verification system upgrades brought about by future adjustments to the number of loop instructions, loop depth, etc.

[0055] like Figure 1 As shown, an embodiment of the present application provides an instruction verification method, the method comprising:

[0056] S101, obtaining an instruction set to be verified;

[0057] Specifically, the instruction set to be verified in the embodiment of the present application is a repeat loop instruction set. The repeat loop instruction is a hardware loop instruction. The first instruction after the repeat loop instruction is the first instruction of the loop body. loopend defines the end instruction of the loop body as an offset, and the loop register defines the number of loops. The loop register has a value range of 1-222, loopend is the offset of the PC program execution, which distinguishes between 16-bit instructions and 32-bit instructions, and the repeat instruction requires address alignment.

[0058] An instruction set will be loaded into each chip. The instruction set in the chip needs to be verified before leaving the factory, and the terminal device obtains the instruction set to be verified.

[0059] S102, performing directed testing and random testing on the instruction set to be verified, respectively, to obtain an assembly file corresponding to the instruction set to be verified;

[0060] Specifically, after obtaining the instruction set to be verified, the terminal device performs directed testing and random testing on the instruction set to be verified. Since some special functions need to be set in the loop body, the special functions include at least: branch instructions cannot be used in the loop body, such as CSR instructions, and the loop body is interrupted or interrupted by exceptions, and the LOOP register needs to be protected when entering the interrupt / exception service program and restored when returning. Therefore, directed testing is used to verify the special function. At the same time, random verification is used to randomly verify the basic information in the loop body instruction set, such as the loop depth, number of loops, and instructions in the loop body.

[0061] S103 : Using preset simulation software and an assembly file corresponding to the instruction set to be verified, determine a verification result corresponding to the instruction set to be verified.

[0062] Specifically, after the terminal device performs directed tests and random tests on the instructions to be verified, it generates an assembly file, and then uses the preset compilation software to assemble the assembly file to obtain a disassembly file, and determines whether the assembly file is normal. If the assembly file is normal, the preset simulation software is used to simulate the disassembly file to obtain a data table or curve, and then determines whether the instruction set to be verified has passed the verification. If it has passed the verification, it means that the chip functions normally and can be put into use.

[0063] Some embodiments of the present application perform directed testing and random testing on the instruction set to be verified, wherein the directed test is used to test the special functions of the set, and the random verification method can randomly verify the loop depth, number of loops, and instructions within the loop body. The instruction verification method provided by the present application has good scalability and reusability, and can meet the needs of related verification system upgrades brought about by future adjustments to the number of loop instructions, loop depth, etc.

[0064] Another embodiment of the present application further supplements the instruction verification method provided in the above embodiment.

[0065] Optionally, perform targeted testing on the instruction set to be verified, including:

[0066] Preset directed test cases are used to verify the preset functions of the instruction set to be verified, wherein the preset functions of the instruction set to be verified include at least whether the loop body includes branch instructions, whether the loop body triggers an interrupt, and boundary testing, and the boundary testing includes at least one or more of the maximum number of loops, the minimum number of loops, the maximum loop depth, and the minimum loop depth.

[0067] Some embodiments of the present application use preset directional test cases to test the interruption and exception triggered by the loop body, and also perform directional verification on boundary conditions such as the maximum and minimum values ​​of the number of loop times / depth.

[0068] Optionally, random testing is performed on the instruction set to be verified, including:

[0069] Test each instruction function in the instruction set to be verified and obtain the test results;

[0070] Comparing the test result with a preset verification result corresponding to the instruction function to obtain a comparison result;

[0071] Save the test results, preset verification results and comparison results in an assembly file.

[0072] Some embodiments of the present application set random constraints in the main function, generate loop body instructions according to the number of loops, output the randomly generated instructions to the assembly file (testcase.S), and calculate the final result by calling each instruction function in the main function, output it to the corresponding assembly file, and finally output the comparison instruction of the instruction calculation result with the C++ calculation result to the assembly file.

[0073] Assembly files need to be compiled by a compiler to generate data files, disassembly files, and other files before simulation.

[0074] Optionally, using preset simulation software and an assembly file corresponding to the instruction set to be verified to determine a verification result corresponding to the instruction set to be verified includes:

[0075] Compile the assembly file corresponding to the instruction set to be verified using a preset compiler to obtain a disassembly file corresponding to the assembly file;

[0076] The disassembly file is simulated using preset simulation software to obtain verification results corresponding to the instruction set to be verified.

[0077] In some embodiments of the present application, an instruction compiler is used to compile the assembly file, generate corresponding disassembly and data files, etc., and the disassembly file is simulated using preset simulation software to obtain verification results corresponding to the instruction set to be verified. In this way, the verification results of the instruction set to be verified can be clearly understood.

[0078] Optionally, the method further includes:

[0079] Save the disassembled file in the storage unit.

[0080] The data file needs to be initialized and entered into the storage unit. During simulation, the kernel fetches instructions or accesses memory from the storage unit.

[0081] Some embodiments of the present application execute simulation scripts of a simulation platform, initialize data files to storage units, and the kernel fetches instructions from the storage units to execute instructions, and finally outputs execution results.

[0082] An embodiment of the present application provides an instruction verification system based on loop instructions. The system generates random test cases of random loop depth, number of loops, and instructions within the loop body by writing assembly-oriented instruction test cases and C++ program constraints to ensure the reliability of verification.

[0083] Figure 2 A flowchart of another instruction verification method provided in an embodiment of the present application is shown as follows: Figure 2 As shown, the system includes a simulation platform, which includes a kernel, a storage unit for storing instructions, and an instruction compiler (HaawkingIDE). The storage unit for storing instructions includes at least a static random access memory (SRAM). The simulation platform can simulate and run scripts and other files; the storage unit stores programs for compiling assembled directed test cases and random test cases.

[0084] Among them: the simulation platform uses the SystemVerilog language to write the testbench simulation environment, instantiates the tested core module and storage unit, uses the Advanced High Performance Bus (AHB) protocol to connect the core and storage unit (SRAM), and provides other stimulus signals such as clock and reset signals. The stimulus signals are used to control the execution of each test case. It also includes a simulation script, compiles the simulation platform and calls the VCS software for simulation; the data processing script processes the data file so that the simulation platform can initialize the data to the storage unit.

[0085] The directed test cases provided in the embodiments of the present application require directed verification of boundary conditions such as loop body triggering interruptions, exceptions, and maximum and minimum loop counts / depths.

[0086] The embodiment of the present application also generates a program for generating random loop times, random loop depths, and random loop bodies. It is written in C++ language, sets random constraints in the main function, generates loop body instructions according to the number of loops, and outputs the random instructions to the assembly file (testcase.S). The final result is calculated by calling each instruction function in the main function and output to the corresponding assembly file. Finally, the comparison instruction between the instruction calculation result (actual verification result) and the C++ calculation result (preset verification result) is output to the assembly file.

[0087] The instruction compiler (Haawking IDE) provided in the embodiment of the present application compiles the above-mentioned assembly file to generate corresponding disassembly and data files, etc.

[0088] According to the loop instruction verification system of the embodiment of the present application, each directed and random test case is effectively organized, and each instruction-related scenario of the design to be tested is also covered as much as possible. After each test case is automatically compared, the results are more reliable. Moreover, compared with the traditional waveform debugging method, the automatic comparison method is more efficient.

[0089] The specific verification process based on the above verification system is as follows:

[0090] Step 1: Write directed test cases for loop instructions through boundary functions.

[0091] Step 2: Generate a large number of assembly files by generating programs in a random manner.

[0092] Step 3: Compile the assembly file through the instruction compiler to generate disassembly and data files.

[0093] Step 4: Execute the simulation script of the simulation platform, initialize the data file to the storage unit, the core fetches instructions from the storage unit and executes the instructions, and finally outputs the execution results.

[0094] The verification system provided in the embodiment of the present application has a simple structure and clear layers, and takes into account the systematicity, completeness and reliability. In addition, the above-mentioned verification system also has good scalability and reusability, and can meet the needs of related verification system upgrades brought about by future adjustments to the number of loop instructions, loop depth, etc.

[0095] It should be noted that each implementable method in this embodiment can be implemented separately, or can be implemented in combination in any combination without conflict, and this application does not limit it.

[0096] Another embodiment of the present application provides an instruction verification device for executing the instruction verification method provided in the above embodiment.

[0097] like Figure 3 FIG. 3 is a schematic diagram of the structure of the instruction verification device provided in an embodiment of the present application. The instruction verification device includes an acquisition module 301, a test module 302 and a simulation module 303, wherein:

[0098] The acquisition module 301 is used to obtain the instruction set to be verified;

[0099] The testing module 302 is used to perform directed testing and random testing on the instruction set to be verified, and obtain an assembly file corresponding to the instruction set to be verified;

[0100] The simulation module 303 is used to use preset simulation software and an assembly file corresponding to the instruction set to be verified to determine a verification result corresponding to the instruction set to be verified.

[0101] Regarding the device in this embodiment, the specific manner in which each module performs operations has been described in detail in the embodiment of the method and will not be elaborated here.

[0102] Some embodiments of the present application perform directed testing and random testing on the instruction set to be verified, wherein the directed test is used to test the special functions of the set, and the random verification method can randomly verify the loop depth, number of loops, and instructions within the loop body. The instruction verification method provided by the present application has good scalability and reusability, and can meet the needs of related verification system upgrades brought about by future adjustments to the number of loop instructions, loop depth, etc.

[0103] Another embodiment of the present application further supplements the instruction verification device provided in the above embodiment.

[0104] Optionally, a test module for:

[0105] Preset directed test cases are used to verify the preset functions of the instruction set to be verified, wherein the preset functions of the instruction set to be verified include at least whether the loop body includes branch instructions, whether the loop body triggers an interrupt, and boundary testing, and the boundary testing includes at least one or more of the maximum number of loops, the minimum number of loops, the maximum loop depth, and the minimum loop depth.

[0106] Some embodiments of the present application use preset directional test cases to test the interruption and exception triggered by the loop body, and also perform directional verification on boundary conditions such as the maximum and minimum values ​​of the number of loop times / depth.

[0107] Optionally, a test module for:

[0108] Test each instruction function in the instruction set to be verified and obtain the test results;

[0109] Comparing the test result with a preset verification result corresponding to the instruction function to obtain a comparison result;

[0110] Save the test results, preset verification results and comparison results in an assembly file.

[0111] Some embodiments of the present application set random constraints in the main function, generate loop body instructions according to the number of loops, output the randomly generated instructions to the assembly file (testcase.S), and calculate the final result by calling each instruction function in the main function, output it to the corresponding assembly file, and finally output the comparison instruction of the instruction calculation result with the C++ calculation result to the assembly file.

[0112] Optionally, a simulation module for:

[0113] Compile the assembly file corresponding to the instruction set to be verified using a preset compiler to obtain a disassembly file corresponding to the assembly file;

[0114] The disassembly file is simulated using preset simulation software to obtain verification results corresponding to the instruction set to be verified.

[0115] In some embodiments of the present application, an instruction compiler is used to compile the assembly file, generate corresponding disassembly and data files, etc., and the disassembly file is simulated using preset simulation software to obtain verification results corresponding to the instruction set to be verified. In this way, the verification results of the instruction set to be verified can be clearly understood.

[0116] Optionally, a simulation module for:

[0117] Save the disassembled file in the storage unit.

[0118] Some embodiments of the present application execute simulation scripts of a simulation platform, initialize data files to storage units, and the kernel fetches instructions from the storage units to execute instructions, and finally outputs execution results.

[0119] Regarding the device in this embodiment, the specific manner in which each module performs operations has been described in detail in the embodiment of the method and will not be elaborated here.

[0120] It should be noted that each implementable method in this embodiment can be implemented separately, or can be implemented in combination in any combination without conflict, and this application does not limit it.

[0121] An embodiment of the present application further provides a computer-readable storage medium on which a computer program is stored. When the program is executed by a processor, the operation of the method corresponding to any embodiment of the instruction verification method provided in the above embodiments can be implemented.

[0122] An embodiment of the present application further provides a computer program product, which includes a computer program, wherein when the computer program is executed by a processor, it can implement the operations corresponding to any embodiment of the instruction verification method provided in the above embodiments.

[0123] like Figure 4 As shown, some embodiments of the present application provide an electronic device 400, which includes: a memory 410, a processor 420, and a computer program stored in the memory 410 and executable on the processor 420, wherein the processor 420 can implement a method such as any embodiment of the above-mentioned instruction verification method when reading the program from the memory 410 through the bus 430 and executing the program.

[0124] Processor 420 can process digital signals and can include various computing architectures, such as a complex instruction set computer architecture, a reduced instruction set computer architecture, or an architecture that implements a combination of multiple instruction sets. In some examples, processor 420 can be a microprocessor.

[0125] The memory 410 can be used to store instructions executed by the processor 420 or data related to the execution of instructions. These instructions and / or data may include code for implementing some or all functions of one or more modules described in the embodiments of this application. The processor 420 of the embodiment of the present disclosure can be used to execute the instructions in the memory 410 to implement the method shown above. The memory 410 includes dynamic random access memory, static random access memory, flash memory, optical memory, or other memory known to those skilled in the art.

[0126] The above are merely examples of the present application and are not intended to limit the scope of protection of the present application. For those skilled in the art, the present application may have various modifications and variations. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included in the scope of protection of the present application. It should be noted that similar numbers and letters represent similar items in the following figures. Therefore, once an item is defined in one figure, it does not need to be further defined or explained in subsequent figures.

[0127] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present application should be included in the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.

[0128] It should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply the existence of any such actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or device comprising the element.

Claims

1. A method for verifying an instruction, characterized in that: The method comprises: Obtaining an instruction set to be verified, wherein the instruction set to be verified is a repeat loop instruction set, the repeat loop instruction is a hardware loop instruction, the first instruction after the repeat loop instruction is the first instruction of the loop body, loopend defines the end instruction of the loop body in an offset manner, and the loop register defines the number of loops; Performing a directed test and a random test on the instruction set to be verified respectively to obtain an assembly file corresponding to the instruction set to be verified; Using preset simulation software and an assembly file corresponding to the instruction set to be verified, determining a verification result corresponding to the instruction set to be verified; performing a directed test on the instruction set to be verified, including: Using preset targeted test cases to verify preset functions of the instruction set to be verified, wherein the preset functions of the instruction set to be verified include at least whether a loop body includes a branch instruction, whether the loop body triggers an interrupt, and boundary testing, wherein the boundary testing includes at least one or more of a maximum number of loops, a minimum number of loops, a maximum loop depth, and a minimum loop depth; The randomly testing the instruction set to be verified includes: Testing each instruction function in the instruction set to be verified to obtain a test result; Comparing the test result with a preset verification result corresponding to the instruction function to obtain a comparison result; The test result, the preset verification result and the comparison result are saved in an assembly file.

2. The instruction verification method according to claim 1, characterized in that: The using of preset simulation software and an assembly file corresponding to the instruction set to be verified to determine a verification result corresponding to the instruction set to be verified includes: Compiling an assembly file corresponding to the instruction set to be verified using a preset compiler to obtain a disassembly file corresponding to the assembly file; The disassembled file is simulated using preset simulation software to obtain a verification result corresponding to the instruction set to be verified.

3. The instruction verification method according to claim 2, characterized in that: The method further comprises: The disassembly file is stored in a storage unit.

4. An instruction verification device, characterized in that: The device comprises: an acquisition module, configured to acquire an instruction set to be verified, wherein the instruction set to be verified is a repeat loop instruction set, the repeat loop instruction is a hardware loop instruction, the first instruction after the repeat loop instruction is the first instruction of the loop body, loopend defines the end instruction of the loop body in the form of an offset, and the loop register defines the number of loops; A test module is used to perform a directed test and a random test on the instruction set to be verified, respectively, to obtain an assembly file corresponding to the instruction set to be verified; the test module is used to: Using preset targeted test cases to verify preset functions of the instruction set to be verified, wherein the preset functions of the instruction set to be verified include at least whether a loop body includes a branch instruction, whether the loop body triggers an interrupt, and boundary testing, wherein the boundary testing includes at least one or more of a maximum number of loops, a minimum number of loops, a maximum loop depth, and a minimum loop depth; The test module is used to: Testing each instruction function in the instruction set to be verified to obtain a test result; Comparing the test result with a preset verification result corresponding to the instruction function to obtain a comparison result; Saving the test result, the preset verification result and the comparison result in an assembly file; The simulation module is used to use preset simulation software and an assembly file corresponding to the instruction set to be verified to determine a verification result corresponding to the instruction set to be verified.

5. An electronic device, characterized in that: The invention comprises a memory, a processor and a computer program stored in the memory and executable on the processor, wherein the processor can implement the instruction verification method according to any one of claims 1 to 3 when executing the program.

6. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, wherein when the program is executed by a processor, the instruction verification method according to any one of claims 1 to 3 can be implemented.

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