Memory device with segmented SGD drain

Abstract

The invention relates to a memory device with segmented SGD drain. Various applications may include memory devices designed to provide enhanced gate-induced drain leakage (GIDL) current during memory erase operations. An enhancement operation may be provided to a string of memory cells at a segmented drain of a select gate transistor by enhancing an electric field in a channel structure of the select gate transistor. The segmented drain may have conductive fins integrated with the transistor channel structure and extending vertically from a top boundary of the transistor channel structure, wherein the conductive fins are separated from each other by a non-conductive region on the top boundary. The segmented drain may include a portion extending downward below the top boundary. The transistor channel structure may be integrated with a channel structure forming a pillar of the memory cell string. Additional apparatus, systems, and methods are discussed.

Description

Technical Field

[0001] Embodiments of the present disclosure relate generally to memory devices and operations of memory devices, and more particularly, to structures and methods related to erase operations of memory devices. Background Art

[0002] Memory devices are typically provided as internal semiconductor integrated circuits in computers or other electronic devices. There are many different types of memory, including volatile and non-volatile memory. Volatile memory requires power to maintain its data, and includes random access memory (RAM), dynamic random access memory (DRAM), or synchronous dynamic random access memory (SDRAM), etc. Non-volatile memory can retain stored data when power is not supplied, and includes flash memory, read-only memory (ROM), electrically erasable programmable ROM (EEPROM), erasable programmable ROM (EPROM), resistance variable memory (such as phase change random access memory (PCRAM)), resistive random access memory (RRAM), magnetoresistive random access memory (MRAM), or three-dimensional (3D) XPoint TM Memory, etc. The properties of memory devices and other electronic devices may be improved by enhancing the structure and fabrication of components in the memory devices to access the memory cells of the memory devices. Summary of the invention

[0003] In one aspect, the present disclosure relates to a memory device, comprising: a vertical semiconductor pillar coupled to a memory cell, the vertical semiconductor pillar having a channel structure arranged as a channel portion of the memory cell; a digit line; and a transistor for coupling the digit line to the vertical semiconductor pillar, the transistor comprising: a gate and a gate dielectric; a transistor channel structure separated from the gate by the gate dielectric, the transistor channel structure being vertically integrated with the channel structure of the memory cell of the vertical semiconductor pillar; a segmented drain having a conductive fin integrated with the transistor channel structure and extending vertically from a top boundary of the transistor channel structure, the conductive fins being separated from each other by a non-conductive region on the top boundary, the segmented drain comprising a portion extending downward from an intersection of the conductive fin and the non-conductive region below the top boundary; and a drain contact contacting the conductive fin, the drain contact comprising titanium at the conductive fin.

[0004] In another aspect, the present disclosure relates to a memory device comprising: a digit line; a vertical semiconductor pillar coupled to a memory cell of a memory array, the vertical semiconductor pillar having a polysilicon channel structure arranged as a channel portion of the memory cell; a drain-side select gate (SGD) transistor comprising: a polysilicon transistor channel structure integrated with the polysilicon channel structure; and a segmented drain having a conductive fin integrated with the polysilicon transistor channel structure and extending vertically from a top boundary of the polysilicon transistor channel structure, the conductive fins being separated from each other by a non-conductive region on the top boundary, the segmented drain comprising a portion extending downwardly from an intersection of the conductive fin and the non-conductive region below the top boundary; a drain contact contacting the conductive fin, the drain contact comprising titanium at the conductive fin; and a memory controller comprising a processing circuit system, the memory controller being configured to perform an erase operation on the memory cell of the vertical semiconductor pillar by applying an erase voltage to the gate of the SGD transistor that electrically couples the vertical semiconductor pillar to the digit line.

[0005] In another aspect, the present disclosure relates to a method for forming a memory device, the method comprising: forming a vertical semiconductor pillar for vertically arranged memory cells of a memory array; forming a drain-side select gate (SGD) transistor integrated with the vertical semiconductor pillar, which comprises: forming a transistor channel structure of the SGD transistor extending vertically from the channel structure of the vertical semiconductor pillar; forming a conductive fin extending vertically from a top boundary of the transistor channel structure, the conductive fins being separated from each other by a non-conductive region on the top boundary, the conductive fins and the non-conductive region being structured as a segmented drain of the SGD transistor; forming a portion of the segmented drain extending downward from an intersection of the conductive fin and the non-conductive region below the top boundary; and forming a drain contact contacting the conductive fin, the drain contact comprising titanium at the conductive fin. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The drawings, which are not necessarily drawn to scale, generally illustrate the various embodiments discussed in this document by way of example and not by way of limitation.

[0007] Figures 1 to 4 A set of example segmented structures that may be implemented in a transistor to couple a digit line to a vertical pillar of a memory cell are illustrated in accordance with various embodiments.

[0008] Figure 5 An example segmented structure of transistors arranged to couple a digit line to the channel material of a vertical pillar of a memory cell of a memory device is illustrated in accordance with various embodiments.

[0009] Figures 6 to 50 Features of an example method of forming a memory device having an array of strings of memory cells, wherein each string is formed as a vertical pillar coupled to a drain side select gate transistor of the string, are described in accordance with various embodiments.

[0010] Fig.51 is a flow chart featuring an example method of forming a memory device having a drain side select gate coupling a string of memory cells to a digit line, according to various embodiments.

[0011] Fig.52 A block diagram illustrating features of an example memory device including a memory array having a plurality of memory cells and one or more circuits or components for providing communications with or performing one or more memory operations on the memory array in accordance with various embodiments. DETAILED DESCRIPTION

[0012] The following detailed description refers to the accompanying drawings that show various embodiments that can be implemented by way of illustration. These embodiments are described in sufficient detail to enable those of ordinary skill in the art to practice these and other embodiments. Other embodiments may be utilized, and structural, logical, mechanical and electrical changes may be made to these embodiments. As used in this application, the term "horizontal" is defined as a plane parallel to the conventional plane or surface of a wafer or substrate, regardless of the orientation of the wafer or substrate. The term "vertical" refers to a direction perpendicular to the horizontal defined above. Various embodiments are not necessarily mutually exclusive, as some embodiments may be combined with one or more other embodiments to form new embodiments. Therefore, the following detailed description should not be understood in a restrictive sense.

[0013] Flash memory is used in various electronic applications as non-volatile memory. Flash memory devices typically include one or more groups of single transistor, floating gate, or charge trapping memory cells that allow high memory density, high reliability, and low power consumption. Two common types of flash memory array architectures include NAND and NOR architectures, named after the logical form in which the basic memory cell configuration of each is arranged. The memory cells of the memory array are typically arranged in a matrix. In an example, the gate of each floating gate memory cell in a row of the array is coupled to an access line (e.g., a word line). In a NOR architecture, the drain of each memory cell in a column of the array is coupled to a digital line (e.g., a bit line). In a NAND architecture, the drain of each memory cell in a string of the array is coupled in series, source to drain, between a source line and a digital line.

[0014] Using 3D architecture for memory devices such as NAND memory devices can provide increased capacity over planar structures. A 3D structured memory array can include memory cells stacked vertically into strings of memory cells. When selecting one or more strings to access a given memory cell, a gate structure can be positioned at the top and bottom of these strings with the memory cells storing data between the top and bottom. The gate structure can include a select gate transistor whose drain is coupled to a digit line (e.g., a bit line) at one end of the string and whose source is coupled to a source line at the other end of the string.

[0015] In many NAND flash devices, an erase operation is performed on a string of memory cells by applying a relatively high positive voltage to the string body. In the case of a 3D NAND architecture, when the string body of the memory cell is electrically isolated, holes can be generated and injected into the string body to maintain a positive potential in the string during the erase of the memory cells of the string. Gate-induced drain leakage (GIDL) is a technology that achieves high performance and reliable erase operations. Due to the large field effect in the drain junction, it is a leakage mechanism in devices such as insulated gate field effect transistors (IGFETs). Existing methods for enhancing GIDL operations in 3D NAND flash memory devices include attempts to optimize the device doping distribution of the select transistor to the memory cell string to cause the junction of the select transistor to mutate. As the number of levels of memory cells in a vertical string in a 3D NAND flash memory device rises to several hundred or more, it is important to provide sufficient GIDL current during erase operations.

[0016] Both NOR and NAND flash architecture semiconductor memory arrays of flash memory devices are accessed through decoders that activate a particular memory cell by selecting an access line (WL) coupled to the gate of the particular memory cell. In a NOR architecture semiconductor memory array, once activated, the selected memory cell places its data value on the digit line, causing different currents to flow depending on the state of programming the particular cell. In a NAND architecture semiconductor memory array, a relatively high bias voltage is applied to the drain side select gate (SGD) line. The access line coupled to the gates of the unselected memory cells of each group is driven with a specified pass voltage (Vpass) to operate the unselected memory cells of each group as pass transistors to pass current, for example, in a manner that is not limited by their stored data values. The current then flows in the line between the source line and the digit line through each series-coupled group, limited only by the selected memory cells of each group, thereby placing the current-encoded data value of the selected memory cell on the digit line.

[0017] Each flash memory cell in a NOR or NAND architecture semiconductor memory array can be individually or collectively programmed to one or more programming states. For example, a single-level cell (SLC) can represent one of two programming states (e.g., 1 or 0), thereby representing one data bit. Flash memory cells can also represent more than two programming states, thereby allowing higher density memory to be manufactured without increasing the number of memory cells, because each cell can represent more than one binary digit (e.g., more than one bit). Such cells may be referred to as multi-state memory cells, multi-digit cells, or multi-level cells (MLC). In some instances, MLC has been referred to as a memory cell that can store two data bits per cell (e.g., one of four programming states). MLC is used herein in its broader context to refer to any memory cell that can store more than one data bit per cell (i.e., can represent more than two programming states). In this article, a memory cell that can store two data bits per cell (e.g., one of four programming states) is referred to as a dual-level cell (DLC). A three-level cell (TLC) refers to a memory cell that can store three bits of data per cell (e.g., one of eight programming states). A four-level cell (QLC) can store four bits of data per cell and a five-level cell (PLC) can store five bits of data per cell. In a string of memory cells in a 3D memory device such as a 3D NAND memory, access to the string to operate on the memory cells in the string can be controlled by a gate-controlled selector device (e.g., a select gate transistor) in series with the memory cells of the string.

[0018] In various embodiments, inter-band charge generation in a transistor channel of a select gate transistor at a digit line side of a 3D NAND flash pillar of a memory cell may be increased based on segmentation of a drain of the select gate transistor. The pillar may include a string of memory cells coupled to a source line at one end of the pillar by one or more source side select gate (SGS) transistors coupled to the pillar, wherein the string of memory cells is arranged in series with the source line. At the other end, the string of memory cells may be coupled to a digit line by one or more SGD transistors coupled to the pillar and arranged to couple the string of memory cells to the digit line. The pillar providing the string may be a vertical semiconductor pillar coupled to the memory cell, wherein the vertical semiconductor pillar has a channel structure arranged as a channel portion of the memory cell. The SGD transistor may include a gate, a gate dielectric, a transistor channel structure, and a segmented drain. The transistor channel structure is separated from the gate by a gate dielectric, wherein the transistor channel structure is vertically integrated with the channel structure of the memory cell of the vertical semiconductor pillar. The segmented drain may have a conductive fin integrated with the transistor channel structure and may extend vertically from a top boundary of the transistor channel structure. The conductive fins are separated from each other by a non-conductive region on the top boundary. The segmented drain may also include a conductive portion extending downward from the intersection of the conductive fin and the non-conductive region below the top boundary. The drain contact may contact the conductive fin of the segmented drain, wherein the drain contact may include titanium at the conductive fin. Each of the plurality of pillars of a memory cell in a 3D NAND memory array may be coupled to a digit line via one SGD transistor and to a source line via one SGS transistor.

[0019] Increasing the generation of inter-band charge based on the structural interface of the transistor channel structure integrated with the channel structure of the segmented drain and the pillar can further enhance the drain side current GIDL in the erase operation. This structural interface of the segmented drain provides a different approach to doping optimization between the contact and the channel structure of the SGD transistor. The inter-band tunneling field that causes the GIDL current can be enhanced by using a segmented drain integrated with the channel structure of the pillar via the channel structure of the SGD transistor. The cross-cut segmented drain provided by the fins and non-conductive regions of the segmented drain disrupts the uniformity of the electric field and allows the electric field lines to be concentrated in the cut area, thereby enhancing the inter-band offset.

[0020] The SGD transistor of a vertical NAND string of memory cells may be implemented with a segmented drain having a fin butting against the channel region of the SGD transistor, wherein a fang region extends from the fin into the channel region. The SGD transistor with segmented fins and fangs may be implemented in many arrangements. In one arrangement, a thin, low capacitance drain contact may be constructed in situ with the segmented module. The drain contact may be, but is not limited to, a tungsten (W) drain contact. In another arrangement, the drain contact may be constructed to touch down to a conductive landing pad. The drain contact may be, but is not limited to, a W drain contact, and the conductive landing pad may be, but is not limited to, an n+ drain landing pad. The drain contact may include titanium (Ti) / titanium nitride (TiN) / W in contact with the fin of the segmented drain. When the fin of the segmented drain is composed of silicon, the Ti / TiN / W drain contact may form a titanium silicide (TiSi) with the silicon of the segmented drain. X ) interface, which can enhance the ohmic properties of the drain contact. X The interface may be one or more monolayers or greater in thickness. Other semiconductor materials may be used for segmented drains and drain contacts with enhanced ohmic properties.

[0021] The configuration and shape of the interface between the channel structure of the SGD transistor and the segmented fin of the drain of the SGD transistor can be designed to improve performance. The segmented fin of the drain can be more heavily doped than the channel region. For example, the segmented fin of the drain can be an n+ region and the channel region can be an n- region or an n- region. The fangs extending from the segmented fins can also be structured as n+ regions.

[0022] Figures 1 to 4 A set of example structures 102, 202, 302, and 402 that can be implemented in a transistor to couple a digit line to a vertical pillar of a memory cell are described, wherein the structures include segmented fins and are integrated into the corresponding vertical pillars of the memory cell. For example, a transistor that couples a digit line to a vertical pillar of a memory cell can be implemented as an SGD transistor in a memory array of a NAND memory device. Each of the structures 102, 202, 302, and 402 includes a transistor channel structure for coupling to a channel material of a vertical pillar of a memory cell and extending vertically from the channel material of the vertical pillar in an integrated manner. The transistor channel structure provides transistor operation and is separated from the gate of the transistor by a dielectric material that provides a transistor tunnel region. Each of the structures 102, 202, 302, and 402 may also include one or more fins of a segmented drain that is more heavily doped than the transistor channel structure. The one or more fins may be separated from each other by one or more non-conductive regions. One or more fins may contact and may extend vertically from and over the transistor channel structure, and one or more non-conductive regions may contact and extend vertically from and over the transistor channel structure.

[0023] Figure 1A structure 102 is shown forming part of a SGD transistor. The structure 102 has fins 105-1, 105-2, 105-3, 105-4, 105-5, and 105-6 and non-conductive regions 107-1, 107-2, 107-3, 107-4, 107-5, and 107-6, wherein the fins 105-1, 105-2, 105-3, 105-4, 105-5, and 105-6 and non-conductive regions 107-1, 107-2, 107-3, 107-4, 107-5, and 107-6 extend vertically from a channel structure 110 of the structure 102 of the SGD transistor. Although the non-conductive regions 107-1, 107-2, 107-3, 107-4, 107-5, and 107-6 are shown as voids, these non-conductive regions may include dielectric materials. The interface between the non-conductive region 107-1 and the channel structure 110 has a rounded corner 108-2, which is the rounded corner boundary of the channel structure 110 from the lower end corner of the fin 105-1 to the lower end corner of the fin 105-2. The interface between the non-conductive region 107-6 and the channel structure 110 has a rounded corner 108-1, which is the rounded corner boundary of the channel structure 110 from the lower end corner of the fin 105-6 to the lower end corner of the fin 105-1. The interface between the non-conductive region 107-5 and the channel structure 110 has a rounded corner 108-6, which is the rounded corner boundary of the channel structure 110 from the lower end corner of the fin 105-5 to the lower end corner of the fin 105-6. The non-conductive region between the fin 105-2 and the fin 105-3 may also have a rounded corner as the rounded corner boundary of the channel structure 110. The non-conductive region between fin 105-3 and fin 105-4 may also have rounded corners as a rounded corner boundary of channel structure 110. The non-conductive region between fin 105-4 and fin 105-5 may also have rounded corners as a rounded corner boundary of channel structure 110. The rounded corners of structure 102 may be structured as a more heavily doped region than channel structure 110. For example, when channel structure 110 is doped as an n- structure, the rounded corners of structure 102 may include n+ doping. When implemented in an SGD transistor of a memory string of a memory array of a memory device, structure 102 may be disposed around a dielectric region.

[0024] Figure 2A structure 202 is shown forming part of a SGD transistor. The structure 202 has fins 205-1, 205-2, 205-3, 205-4, 205-5, and 205-6 and non-conductive regions 207-1, 207-2, 207-3, 207-4, 207-5, and 207-6, wherein the fins 205-1, 205-2, 205-3, 205-4, 205-5, and 205-6 and non-conductive regions 207-1, 207-2, 207-3, 207-4, 207-5, and 207-6 extend vertically from a channel structure 210 of the structure 202. Although the non-conductive regions 207-1, 207-2, 207-3, 207-4, 207-5, and 207-6 are shown as voids, these non-conductive regions may include dielectric materials. The interface between the non-conductive region 207-1 and the channel structure 210 has a rounded corner 208-2, which is the rounded corner boundary of the channel structure 210 from the lower end corner of the fin 205-1 to the lower end corner of the fin 205-2. The interface between the non-conductive region 207-6 and the channel structure 210 has a rounded corner 208-1, which is the rounded corner boundary of the channel structure 210 from the lower end corner of the fin 205-6 to the lower end corner of the fin 205-1. The interface between the non-conductive region 207-5 and the channel structure 210 has a rounded corner 208-6, which is the rounded corner boundary of the channel structure 210 from the lower end corner of the fin 205-5 to the lower end corner of the fin 205-6. The interface between the non-conductive region 207-2 and the channel structure 210 may also have a rounded corner as a rounded corner boundary between the fin 205-2 and the fin 205-3 of the channel structure 210. The interface of the non-conductive region 207-3 and the channel structure 210 may also have rounded corners as the rounded corner boundary between the fin 205-3 and the fin 205-4 of the channel structure 210. The interface of the non-conductive region 207-4 and the channel structure 210 may also have rounded corners as the rounded corner boundary between the fin 205-4 and the fin 205-5 of the channel structure 210. The rounded corners of the structure 202 may be structured as a more heavily doped region than the channel structure 210. For example, when the channel structure 210 is doped as an n- structure, the rounded corners of the structure 202 may have an n+ doping.

[0025] In addition, emitter 209-1 may be structured to extend from fillet 208-1 into channel structure 210. Emitter 209-1 may be positioned in channel structure 210 extending downward from a location approximately at the center of fillet 208-1 and may have a width dimension along fillet 208-1 as a portion of fillet 208-1. Emitter 209-2 may be structured to extend from fillet 208-2 into channel structure 210. Emitter 209-2 may be positioned in channel structure 210 extending downward from a location approximately at the center of fillet 208-2 and may have a width dimension along fillet 208-2 as a portion of fillet 208-2. Emitter 209-6 may be structured to extend from fillet 208-6 into channel structure 210. The emitter 209-6 may be positioned in the channel structure 210 extending downward from a location approximately at the center of the fillet 208-6 and may have a width dimension along the fillet 208-6 as a portion of the fillet 208-6. Although not shown, the emitter may be structured into the channel structure 210, extending from other fillets at the interface of the non-conductive region and the channel structure 210. The emitter of the channel structure 202 may be structured to be more heavily doped than the channel structure 210. For example, when the channel structure 210 is doped as an n- structure, the emitter may be an n+ emitter. When implemented in an SGD transistor of a memory string of a memory array of a memory device, the structure 202 may be disposed around a dielectric region.

[0026] Figure 3A structure 302 is shown forming part of a SGD transistor. The structure 302 has fins 305-1, 305-2, 305-3, 305-4, 305-5, and 305-6 and non-conductive regions 307-1, 307-2, 307-3, 307-4, 307-5, and 307-6, wherein the fins 305-1, 305-2, 305-3, 305-4, 305-5, and 305-6 and non-conductive regions 307-1, 307-2, 307-3, 307-4, 307-5, and 307-6 extend vertically from a channel structure 310 of the structure 302. Although the non-conductive regions 307-1, 307-2, 307-3, 307-4, 307-5, and 307-6 are shown as voids, these non-conductive regions may include dielectric materials. The interface between the non-conductive region 307-1 and the channel structure 310 has a rounded corner 308-2, which is the rounded corner boundary of the channel structure 310 from the lower end corner of the fin 305-1 to the lower end corner of the fin 305-2. The interface between the non-conductive region 307-6 and the channel structure 310 has a rounded corner 308-1, which is the rounded corner boundary of the channel structure 310 from the lower end corner of the fin 305-6 to the lower end corner of the fin 305-1. The interface between the non-conductive region 307-5 and the channel structure 310 has a rounded corner 308-6, which is the rounded corner boundary of the channel structure 310 from the lower end corner of the fin 305-5 to the lower end corner of the fin 305-6. The interface between the non-conductive region 307-2 and the channel structure 310 may also have a rounded corner as a rounded corner boundary between the fin 305-2 and the fin 305-3 of the channel structure 310. The interface between the non-conductive region 307-3 and the channel structure 310 may also have rounded corners as the rounded corner boundary between the fin 305-3 and the fin 305-4 of the channel structure 310. The interface between the non-conductive region 307-4 and the channel structure 310 may also have rounded corners as the rounded corner boundary between the fin 305-4 and the fin 305-5 of the channel structure 310.

[0027] Emitter 309-1 may be structured to extend from fillet 308-1 into channel structure 310. Emitter 309-1 may be positioned in channel structure 310 extending downward from a location approximately at the center of fillet 308-1 and may have a width dimension along fillet 308-1 as a portion of fillet 308-1. Emitter 309-2 may be structured to extend from fillet 308-2 into channel structure 310. Emitter 309-2 may be positioned in channel structure 310 extending downward from a location approximately at the center of fillet 308-2 and may have a width dimension along fillet 308-2 as a portion of fillet 308-2. Emitter 309-6 may be structured to extend from fillet 308-6 into channel structure 310. The emitter 309-6 may be positioned in the channel structure 310 extending downward from a location approximately at the center of the fillet 308-6 and may have a width dimension along the fillet 308-6 as a portion of the fillet 308-6. Although not shown, other emitters may be similarly structured to extend from other fillets of the structure 302 at the interface of the non-conductive region and the channel structure 310 into the channel structure 310. The emitter of the structure 302 may be structured to be more heavily doped than the channel structure 310. For example, when the channel structure 310 is doped as an n- structure, the emitter may be an n+ emitter. Figure 3 The structure 302 and Figure 2 Structure 202 of structure 302 differs in that, except at the emitter, the rounded corners of channel structure 310 of structure 302 have no additional charge doping relative to channel structure 310. When implemented in an SGD transistor of a memory string of a memory array of a memory device, structure 302 may be structured around a dielectric region.

[0028] Figure 4 A structure 402 is shown forming part of a SGD transistor. The structure 402 has fins 405-1, 405-2, 405-3, 405-4, 405-5, and 405-6 and non-conductive regions 407-1, 407-2, 407-3, 407-4, 407-5, and 407-6, wherein the fins 405-1, 405-2, 405-3, 405-4, 405-5, and 405-6 and non-conductive regions 407-1, 407-2, 407-3, 407-4, 407-5, and 407-6 extend vertically from a channel structure 410 of the structure 402. Although the non-conductive regions 407-1, 407-2, 407-3, 407-4, 407-5, and 407-6 are shown as voids, these non-conductive regions may include dielectric materials. The interface of each of the non-conductive regions 407-1, 407-2, 407-3, 407-4, 407-5, and 407-6 may have rounded corners between adjacent fins.

[0029] Portions of the fillet from the non-conductive region 407-1 may be structured to be more heavily doped than the channel structure 410 and may be structured as two fang regions that enter the channel structure 410. One fang region 412-2 extends from the lower end corner of the fin 405-2 toward the lower end corner of the fin 405-1. The other of the fang regions 412-2 is not shown. The more heavily doped fang region 412-1 extends from the fin 405-1 into the channel structure 410. The more heavily doped fang region 412-6 extends from the fin 405-6 into the channel structure 410. Portions of the fillet from the non-conductive region 407-5 may be structured to be more heavily doped than the channel structure 410 and may be structured as two fang regions that enter the channel structure 410. One fang region 412-5 extends from the lower end corner of fin 405-5 toward the lower end corner of fin 405-6. The other of the fang regions 412-5 is not shown. When channel structure 410 is doped as an n-structure, the fangs of structure 402 may have an n+ doping and the area between the fangs under the non-conductive region has an n-structure. Although not shown, each fin of structure 402 may be structured with two fang regions extending into channel structure 410, wherein each fang region is disposed along a portion of a corresponding fillet of channel structure 410. Figure 4 The structure of 402 and Figure 1 The structure 102 of FIG. 1 is different in that the fillet of the structure 402 between the fins and under the non-conductive region has two fang regions that are more heavily doped than the channel structure, wherein the region between the fangs is part of the channel structure, and Figure 1 The rounded corners in the structure 102 are more heavily doped from one fin to an adjacent fin. When implemented in an SGD transistor of a memory string of a memory array of a memory device, the structure 402 can be structured around a dielectric region.

[0030] Figure 5 Features of an example arrangement 503 of an SGD transistor having a structure 502 having a segmented drain arranged to couple a digit line 525 to a channel structure of a vertical pillar 501 of a memory cell of a memory device through a transistor channel structure 510 of the SGD transistor integrated with the channel structure of the vertical pillar 501. Since the channel structure 510 of the SGD transistor is integrated with the channel structure of the vertical pillar 501 below the channel structure 510, Figure 5 501. Surrounding the channel structure of the vertical pillar 501 at the step below the channel structure 510 is the region for the memory cells in the pillar. The region includes a tunnel region 521, a charge storage region 522, and a blocking dielectric region 524, which extend substantially through the length of the vertical pillar 501.

[0031] The structure 502 of the SGD transistor may be structured with a segmented drain extending from a channel structure 510 of the SGD transistor. In order to focus on the segmented drain, not all features of the SGD transistor or the pillar with which the SGD transistor is integrated are shown. The segmented drain may include 6 fins 505-1, 505-2, ..., 505-5, and 505-6 and 6 non-conductive regions 507-1, ..., 507-5, and 507-6, although fins 505-3 and 505-4 and non-conductive regions 507-2, 507-3, and 507-4 are not shown. Although the segmented drain is shown as having 6 fins, the segmented drain may include more or less than 6 fins, which may depend on the size of the fins, the non-conductive regions, and the pillar with which the fins and non-conductive regions are integrated. In structure 502, each of fins 505-1, 505-2, ..., 505-5, and 505-6 contacts and extends vertically from a transistor channel structure 510 of structure 502. Each of non-conductive regions 507-1, ..., 507-5, and 507-6 contacts and extends vertically from a transistor channel structure 510 of structure 502. The segmented drain may also include fang regions 512-1, 512-2, ..., 512-6, although only fang regions 512-1, 512-2, 515-5, and 512-6 are shown. Fang regions 512-1, 512-2, ..., 512-6 extend from fins 505-1, 505-2, ..., 505-5, and 505-6 into the transistor channel structure 510 of structure 502. Structure 502 may be connected to Figure 4 The structure 402 is implemented similarly or identically.

[0032] Fins 505-1, 505-2, ..., 505-5, and 505-6 may extend from transistor channel structure 510 to drain contact 520 of the transistor. Drain contact 520 may be coupled to digit line 525 via conductive line contact 523 disposed on and contacting drain contact 520. Drain contact 520 may be a metal contact. The metal contact may include, but is not limited to, a combination of two or more of tungsten, titanium nitride, titanium, titanium silicide, tungsten, titanium nitride, titanium, titanium silicide, or other appropriate metals. Conductive line contact 523 may include, but is not limited to, a combination of two or more of tungsten, titanium nitride, titanium, titanium silicide, tungsten, titanium nitride, titanium, titanium silicide, or other appropriate metals. Drain contact 520 may include titanium silicide contacting fins 505-1, 505-2, ..., 505-5, and 505-6 of the segmented drain. Conductive line contact 523 may serve as an additional drain contact coupled to the fin of structure 502, wherein conductive line contact 523 may have a width equal to or less than the width of digit line 525. Fins 505-1, 505-2, ..., 505-5, and 505-6, fang regions 512-1, 512-2, ..., 512-5, and 512-6, conductive line contact 523, and drain contact 520 may be heavily doped relative to the doping of transistor channel structure 510. Transistor channel structure 510 may be n- doped and these other doped regions may be n+ doped.

[0033] Figures 6 to 50 An example method of forming a memory device having an array of strings of memory cells is described, wherein each string is formed as a vertical pillar of an SGD transistor coupled to the string. The SGD transistor having segmented fins and fangs is formed with a thin, low capacitance drain contact constructed in situ by building segmented modules. For the procedures discussed herein, the selection of process materials may depend on the materials selected to form the various components of the memory array and the contacts to the devices of the memory array. The process materials may be selected to allow removal of one or more materials while retaining one or more other materials. In addition, typical deposition techniques of the materials formed, the dimensions of the materials formed, and the architecture in which the materials are formed may be used.

[0034] Figures 6 to 50An embodiment of an example method of forming a memory device having a memory array of strings of memory cells is described, wherein each string is formed as a vertical pillar of an SGD transistor coupled to the string. Features associated with the stages of forming the SGD transistor coupled to the string of memory cells are shown in these figures. Features are not drawn to scale to focus on the architecture provided. In these figures, an SGD transistor having a segmented drain with fins and fangs extending downward from the fins is formed with a drain contact to the segmented drain that is constructed in situ by constructing the segmented drain. For the procedures discussed herein, the selection of processing materials may depend on the materials selected to form the various components of the memory array and the contacts to the components of the memory array. The processing materials may be selected to allow removal of one or more materials while retaining one or more other materials. Selective etching and conventional masking techniques may be used to remove selected areas in the process. The etching procedure may include (but is not limited to) wet etching, dry etching, and atomic layer etching deposition, among others. In addition, typical deposition techniques of the materials formed, the dimensions of the materials formed, and the architecture in which the materials are formed may be used.

[0035] Figure 6 A cross section of a vertical stack 600 of materials used to form a portion of a memory device is shown. The vertical stack 600 can be achieved by dielectric material layers. The dielectric layers can include alternating layers of two dielectric materials 613 and 614. Dielectric material 616 can be formed on dielectric material layer 613. Dielectric material layer 617 can be formed on dielectric material layer 616, and dielectric material layer 618 is on dielectric material layer 617. Dielectric material layer 619 can be formed on dielectric material layer 618. Dielectric material layers 613 and 614 can be used to form a vertical stack of memory cells when forming a pillar structure of a memory array of a memory device. Dielectric material layers 613 and 614 can be sacrificial region isolation dielectrics, where the sacrificial region will be used to form the gate of the memory cell, where each isolation dielectric separates adjacent levels of the memory cell. The number of dielectric materials 613 and 614 depends on the number of levels of memory cells to be formed. The number of memory cells in a string (and therefore the number of levels) may range from a few to thousands or more. Dielectric material layers 616, 617, 618, and 619 may be used to form SGD transistors integrated with the pillars of the memory cells. Dielectric materials 613, 617, and 619 may have the same composition or the same type of composition. Dielectric materials 613, 617, and 619 may be dielectric nitrides, such as, but not limited to, silicon nitride. Dielectric materials 614, 616, and 618 may have the same composition or the same type of composition. Dielectric materials 614, 616, and 618 may be dielectric oxides, such as, but not limited to, silicon oxide.

[0036] Figure 7 Display in processing Figure 6 6. A cross section of the structure 700 after the vertical stack 600 is formed. An opening 727 has been formed in the vertical stack 600. The opening 727 will be processed to provide a pillar of the memory cell with an SGD transistor integrated with the pillar.

[0037] Figure 8 Display in processing Figure 7 The cross section of structure 800 after structure 700 is shown. A cell membrane including a channel structure has been formed. The formation may use a deposition process suitable for the material used. Suitable deposition techniques may include, for example, chemical vapor deposition (CVD), atomic layer deposition (ALD), variations of CVD and ALD, or other techniques. Figure 7 Each opening 727 of can be filled in the same manner to form a similar or identical structure. Each cell formed in the opening 727 may include an element of a transistor for storing charge. For example, each cell may include a channel structure in which current can flow in the operation of the memory device, a tunnel region separating the channel structure from a charge trapping region for storing charge, and a dielectric barrier region separating the gate from the charge trapping region. The gate may be formed in a subsequent replacement gate process in which the sacrificial layer is replaced by a conductive gate material. Optionally, a dielectric barrier region structured as a thin region may be disposed between the dielectric barrier region and the gate, which implements an enhanced tunnel barrier to prevent electrons from tunneling back from the gate through the dielectric barrier region into the charge trapping region. The material used for the cell membrane formed in the opening 727 may include a blocking dielectric 824, a charge storage device 822, a tunnel region 821, and a channel structure 810, thereby reducing the opening 727 to an opening 827.

[0038] The blocking dielectric 824 may be formed on Figure 7 On the surface of the opening 727 (such as Figure 8 or Figure 7 The dielectric barrier material is formed on the surface of the opening 727 of the blocking dielectric 824 and then formed on the dielectric barrier material. The blocking dielectric 824 can be silicon oxide, a high-k dielectric, or silicon oxide or a combination of one or more high-k dielectric materials, where k is the dielectric constant. A high-k dielectric is a dielectric with a dielectric constant greater than that of silicon dioxide. When a dielectric barrier material is used, the material of the blocking dielectric 824 that abuts the dielectric barrier material is selected to be different from the material of the dielectric barrier material at the interface.

[0039] In the optional architecture where a dielectric barrier is used, although Figure 8 Not shown, but dielectric barrier material can be deposited on Figure 7on the surface of the opening 727 of the . The dielectric barrier material may be implemented as an aluminum oxide region or a dielectric region having a higher dielectric constant than aluminum oxide. For example, the dielectric barrier material may include one or more of aluminum oxide, hafnium oxide, zirconium oxide, or a mixture of hafnium oxide and / or zirconium oxide with one or more of aluminum oxide, silicon oxide, titanium oxide, gadolinium oxide, niobium oxide, or tantalum oxide. Other high-k dielectrics may be used in the dielectric barrier material. The dielectric barrier material may be formed in a region as a nanolaminate of several different compounds in each sub-region of the region in which the nanolaminate is formed, wherein the formed region has a total thickness in the nanoregion. The term "nanolaminate" means a composite film of ultra-thin layers of two or more materials in a layered stack, which may be layered in the horizontal direction for a vertical nanolaminate. Typically, each layer in the nanolaminate has a thickness in the order of magnitude in the nanometer range. In addition, each individual material layer of the nanolaminate may have a thickness as low as a single layer of material or as high as 5 nanometers. The dielectric barrier material may be formed from Figure 7 The walls of the opening 727 begin to have a thickness in the range of 10 to 50 angstroms. The transition of the dielectric barrier material from one layer of the nanolaminate to another layer of the nanolaminate further disrupts the tendency of the ordered structure in the nanolaminate stack, thereby reducing or eliminating the occurrence of convenient reverse tunneling paths.

[0040] The charge storage device 822 may be formed on the blocking dielectric 824 after forming the blocking dielectric 824. The charge storage device 822 may be constructed of a material that can hold electrons received from the channel structure of the corresponding memory cell in operation. For example, the charge storage device 822 may be a dielectric material that can store charge. The charge storage device 822 may be a dielectric nitride region, such as a region including dielectric silicon nitride. Other dielectric materials of the charge storage device 822 may be used to capture charge. Depending on the memory cell design, a material that operates as a floating gate structure may be used for the charge storage device 822.

[0041] The tunnel region 821 may be formed on the charge storage device 822 after the charge storage device 822 is formed. The tunnel region 821 may be constructed as an engineering region to meet selected criteria, such as (for example but not limited to) equivalent oxide thickness (EOT). The EOT quantifies the electrical properties of the tunnel region 821 of the dielectric, such as capacitance, in terms of a representative physical thickness. For example, the EOT may be defined as the thickness of a theoretical SiO2 layer required to have the same capacitance density as a given dielectric (tunnel region 821) (ignoring leakage current and reliability considerations). The tunnel region 821 may include oxynitride. The tunnel region 821 may include oxides and nitrides. The tunnel region 821 may include a high-k dielectric. The tunnel region 821 may include a set of dielectric regions. The tunnel region 821 may be a three-region structure. This three-region structure may be arranged as a dielectric oxide region followed by a dielectric nitride region followed by another dielectric oxide region. The tunnel region 821 may be a two-region tunnel region structure or a single-region tunnel region structure. Furthermore, the tunnel region 821 may have four or more regions, where the choice of materials and thicknesses depends on the ability of a material with a given thickness to behave as a tunnel region in charge trapping.

[0042] The channel structure 810 may be formed on the tunnel region 821 after forming the tunnel region 821. The channel structure 810 may be structured as a semiconductor material pillar arranged vertically from a source line for a memory cell string array and arranged to couple with an SGD transistor to be formed. The channel structure 810 may be implemented as a polysilicon channel structure. Other semiconductor types and materials may be used for the channel structure 810.

[0043] The horizontally extending top surfaces of the blocking dielectric 824, the charge storage device 822, the tunnel region 821, and the channel structure 810 will be removed in subsequent processing, thereby leaving the blocking dielectric 824, the charge storage device 822, the tunnel region 821, and the channel structure 810 as vertical structures. Figure 7 The top portion of structure 700 is shown formed at Figure 7 The blocking dielectric 824, the charge storage device 822, the tunnel region 821 and the channel structure 810 in the opening 727 of the cell membrane extend through Figure 7 Opening 727.

[0044] Fig. 9 Display in processing Figure 8 800. A dielectric material 926 has been formed in the opening 727. The dielectric material 926 may be a deposited oxide. In order to remove the dielectric material 926 that has been deposited on the top surface of the channel structure 810, a chemical mechanical planarization (CMP) process has been applied to remove the dielectric material 926 from the top surface. After its formation, the dielectric material 926 has been recessed, which provides an opening 927 to form a drain for the formed SGD transistor.

[0045] Fig.10 Display in processing Fig. 9 FIG. 1 is a cross-section of structure 1000 after the structure 900 is formed. A Ti / TiN / W layer 1020 for the drain contact has been deposited on the exposed surface of structure 900. The Ti of Ti / TiN / W layer 1020 is formed to make the exposed surface contact with the TiN formed on the Ti and the W formed on the TiN. Opening 927 has been reduced to opening 1027.

[0046] Fig.11 Display in processing Fig.10 1000. A dielectric layer 1126 has been formed on the Ti / TiN / W layer 1020. The dielectric layer 1126 has been formed to fill the opening 1027. The dielectric layer 1126 may be a deposited oxide that fills the void over the area of ​​the drain contact.

[0047] Fig.12 Display in processing Fig.11 FIG. 1 is a cross-section of structure 1200 after structure 1100 has been subjected to a CMP process, thereby leaving a portion of dielectric layer 1126 as dielectric layer 1226 for forming a drain contact over a region. The CMP process has stopped on the uppermost surface of Ti / TiN / W layer 1020. The uppermost surface of Ti / TiN / W layer 1020 may be W.

[0048] Fig.13 Display in processing Fig.12 1200. The Ti / TiN / W layer 1020 has been removed from the top surface of the structure 1200, exposing the channel structure 810. Portions of the Ti / TiN / W layer 1020 around the dielectric layer 1226 have been removed. The removal may be performed by wet etching the Ti / TiN / W layer 1020 to recess around the dielectric layer 1226, leaving portions of the Ti / TiN / W layer 1020 to form drain contacts 1320 integrated into the pillars of the formed memory cell. The wet etching leaves openings 1327 above the drain contacts 1320 and around the dielectric layer 1226.

[0049] Fig.14 Display in processing Fig.13 FIG. 1 is a cross-section of structure 1400 after structure 1300 is removed. Exposed channel structure 810 of structure 1300 has been removed, thereby exposing tunnel region 821 positioned on charge storage device 822. Exposed channel structure 810 may be removed by wet etching or vapor etching. Opening 1327 has been enlarged to opening 1427.

[0050] Fig.15 Display in processing Fig.14 1400. The exposed tunnel region 821 and the charge storage device 822 have been removed, leaving a blocking dielectric 824. The exposed tunnel region 821 and the charge storage device 822 may be removed by wet etching or vapor etching. The opening 1427 has been expanded to an opening 1527.

[0051] Fig.16 Display in processing Fig.15 1500. A dielectric 1626 has been formed on the top surface of the structure 1500. The dielectric 1626 may be a deposited oxide used to fill the opening 1527 above the drain contact 1320, the tunnel region 821 in the opening 1527, and the charge storage device 822.

[0052] Fig.17 Display in processing Fig.16 17 is a cross-section of structure 1700 after structure 1600 has been subjected to a CMP process. The top surface of structure 1600 has been subjected to a CMP process. Dielectric 1626 has been removed by the CMP process down to the top surface of dielectric material 619. Dielectric layer 1226 has been reduced to dielectric 1726. Dielectric 1626 remains between blocking dielectric 824 and dielectric 1726. The portion of blocking dielectric 824 level with the pillars has been removed. Blocking dielectric 824, dielectric 1626, and dielectric 1726 have been planarized with the top surface of dielectric material 619.

[0053] Fig.18 Display in processing Fig.17 18 is a cross-section of structure 1800 after structure 1700. Dielectric material 619 has been removed, exposing dielectric material 618 in opening 1827 and blocking dielectric 824. Dielectric material 619 may be removed by wet etching.

[0054] Fig.19 Display in processing Fig.18 1800. A photoresist 1929 has been formed, which may be deposited by a spin coating process. Photoresist 1929 may include carbon. Photoresist 1929 may be patterned and dry etched to develop the segmented pattern, as shown by photoresist opening 1927. Photoresist 1929 may be descummed to expose the pillar sidewalls at the pattern edges.

[0055] Fig. 20A top view of structure 1900 is shown. The top view shows six pillars 2001 around a central pillar 2001. Photoresist openings 1927 are between pillars 2001. Six photoresist openings are positioned around central pillar 2001. Direction 2031 is shown passing through the center of central pillar 2001 and the center of photoresist opening 1927. In subsequent processing, non-conductive regions of a segmented drain are formed by processing in direction 2031. When six photoresist openings surround central pillar 2001, a segmented drain having six conductive fins and six non-conductive regions can be formed.

[0056] Fig.21 Display with direction 2131 Fig. 20 A top view of the structure of FIG. 2131 is shown in FIG. 2132 . A direction 2131 passes through the central pillar 2001 and through the center of the pillar 2001 adjacent to the central pillar 2001 . In subsequent processing, a conductive region of the fin of the segmented drain is formed by processing in the direction 2131 .

[0057] Fig. 22 Display in processing Fig.19 The structure after 1900 is along Fig. 20 2031. The vertical blocking dielectric 824 in the opening 1927 has been removed. The opening 1927 has been enlarged to an opening 2227. The charge storage device 822 has been exposed in the opening 2227. The vertical blocking dielectric 824 of the opening 1927 may be removed using a wet etch.

[0058] Fig.23 Display in processing Fig. 22 After the structure 2200, follow Fig. 20 Cross section of structure 2300 processed in direction 2031. Portions of charge storage device 822 and tunnel region 821 have been removed. Opening 2227 has been enlarged to opening 2327. Channel structure 810 is exposed. Charge storage device 822 and tunnel region 821 may be removed using wet etching.

[0059] Fig.24 Display in processing Fig.23 After the structure 2300, follow Fig. 20 2031. The exposed channel structure 810 that formed the sidewalls of the opening 2327 has been removed. The opening 2327 has been enlarged to the opening 2427. The channel structure 810 has been recessed to a step below the top surface of the dielectric material 617, thereby creating a recessed opening 2431. The recessed opening 2431 will be used to create an n+ fang region under the non-conductive portion of the segmented drain. The exposed channel structure 810 can be removed using a wet etch. The photoresist 1929 has been removed.

[0060] Fig.25Display in processing Fig.24 After the structure 2400, follow Fig. 20 A cross section of structure 2500 processed in direction 2031. Dielectric 2526 has been deposited on Fig.24 2431, thereby reducing the recessed opening 2431 to an opening 2531. Dielectric 2526 may be a deposited thin oxide layer for subsequently creating an n+ fang region. Dielectric 2526 has been removed except for the dielectric 2526 oxide remaining in the n+ fang region, thereby changing opening 2427 to opening 2527. Wet etching may be performed when removing dielectric 2526. Removing dielectric 2526 may include removing blocking dielectric 824 from the region between the etched channel structures 810 on the fins of the segmented drain, which is not shown in this view.

[0061] Fig.26 Display in processing Fig.25 After the structure 2500 along Fig. 20 2031. Tunnel region 821 and charge storage device 822 adjacent opening 2531 of structure 2500 have been removed down to the top level of dielectric 2526. Opening 2531 has been enlarged to opening 2631. Tunnel region 821 and charge storage device 822 may be removed using wet etching.

[0062] Fig. 27 Display in processing Fig.26 After the structure 2600 Fig.21 21. This view shows the channel structure 810 after the tunnel region 821 and the charge storage device 822 above the dielectric material 618 are removed. The tunnel region 821 and the charge storage device 822 can be removed by wet etching. This removal of the tunnel region 821 and the charge storage device 822 is performed in preparation for creating a conductive fin for the segmented drain.

[0063] Fig.28 Display in processing Fig. 27 After the structure 2700 along Fig.21 2131. The channel structure 810 above the dielectric material 618 is converted to a conductive fin 1005 by the n+ doped channel structure 810 above the dielectric material 618. Because the channel structure 810 runs vertically through the pillar as the channel structure of the memory cell is formed in the pillar, the n+ fin 1005 of the segmented drain is integrated with the pillar of the memory cell.

[0064] Fig.29 Display in processing Fig.28 After the structure 2800 along Fig. 202031. After the fins are n+ doped along direction 2131, structure 2900 along direction 2031 maintains the architecture of structure 2600. During the formation of conductive fins 1005, dielectric 2526 has prevented channel structure 810 below the top step of dielectric material 617 from being doped.

[0065] Fig.30 Display in processing Fig.29 After the structure 2900 along Fig. 20 2031. A dielectric spacer 3026 has been formed on the top surface of the structure 2900. The opening 2527 has been reduced to an opening 3027. The dielectric spacer 3026 can be a deposited oxide spacer. The dielectric spacer 3026 covers the dielectric 1626 and the dielectric 1726. The dielectric spacer 3026 can provide protection for the conductive fin 1005 during further processing.

[0066] Fig.31 Display in processing Fig.30 After the structure 3000 follows Fig. 20 2031. The dielectric spacer 3026 has been subjected to the spacer etch. The spacer etch has removed portions of the dielectric spacer 3026 to leave dielectric spacer 3226 and has removed portions of the dielectric material 618 to leave dielectric 2218. Dielectric 1626 and dielectric 1726 may be reduced to dielectric 3126 and dielectric 3128 due to the spacer etch. Opening 3027 has become opening 3127.

[0067] Fig.32 Display in processing Fig.31 After the structure 3100 follows Fig. 20 2031. Dielectric material 617 has been removed, exposing blocking dielectric 824 over dielectric material 616 and further exposing dielectric 2218. Opening 3127 has been enlarged to opening 3227. Dielectric material 617 may be removed using a wet etch.

[0068] Fig.33 Display in processing Fig.32 After the structure 3200 follows Fig. 20 2031. The blocking dielectric 824 has been removed and the opening 3227 has been enlarged to an opening 3327. The blocking dielectric 824 may be removed using a wet etch. The charge storage device 822 has been exposed above the dielectric material 616.

[0069] Fig.34 Display in processing Fig.33 After the structure 3300 follows Fig. 20 2031. The charge storage device 822 and the tunnel region 821 have been removed and the opening 3327 has been enlarged to the opening 3427. The charge storage device 822 and the tunnel region 821 may be removed using a wet etch. The channel structure 810 has been exposed above the dielectric material 616.

[0070] Fig.35 Display in processing Fig.34 After the structure 3400 Fig. 20 2031. A gate dielectric 3504 has been formed on the top surface of structure 3400. Gate dielectric 3504 can be implemented as one or more dielectrics. Gate dielectric 3504 can be a deposited gate oxide. Opening 3427 has been enlarged to opening 3527.

[0071] Fig.36 Display in processing Fig.35 After the structure 3500 along Fig.21 36. A cross section of structure 3600 processed in direction 2131 of FIG. 36. Dielectric spacer 3613 has been formed on the surface of structure 3500, including at least partially filling opening 3527. Void region 3637 may be formed as a byproduct of forming dielectric spacer 3613. Void region 3637 may be air. Dielectric spacer 3613 may be a deposited nitride spacer. Note that the pillars and the spaces between the pillars are not drawn to scale. The spaces are scaled up and the pillars are scaled down.

[0072] Fig.37 Display in processing Fig.36 After the structure 3600 follows Fig.21 21. A cross section of structure 3700 processed in direction 2131 of FIG. 21. Dielectric spacer 3613 can be selectively etched. The selective etching can result in gate dielectric 3504 being substantially removed, leaving gate dielectric 3704 enclosing dielectric spacer 3713 as a remaining portion of dielectric spacer 3613. Opening 3727 is formed by the selective etching.

[0073] Fig.38 Display in processing Fig.37 After the structure 3700 along Fig.21 A cross section of structure 3800 processed in direction 2131 of FIG. 3826 has been formed on the surface of structure 3700. Dielectric 3826 may be a deposited oxide layer. Polysilicon 3822 has been formed on dielectric 3826.

[0074] Fig.39 Display in processing Fig.38 After the structure 3800 along Fig.21 21. A cross section of structure 3900 processed in direction 2131. Portions of polysilicon 3822 have been removed so that polysilicon 3922 remains at or below the top of dielectric spacer 3713 around channel structure 810 and gate dielectric 3704. A wet etch may be used to recess polysilicon 3822. Polysilicon at the edge of the memory array at slit region 3933 has been removed. Opening 3927 has been formed above polysilicon 3922.

[0075] Fig.40 Display in processing Fig.39 After the structure 3900, follow Fig.21 21. A cross section of structure 4000 processed in direction 2131. Dielectric 3826 has been removed or significantly reduced, exposing the ends of dielectric spacer 3713. Removal of dielectric 3826 may be performed by wet etching back dielectric 3826. Opening 3927 has been enlarged to opening 4027.

[0076] Fig.41 Display in processing Fig.40 After 4000, the structure follows Fig.21 21. A cross section of structure 4100 processed in direction 2131. A top portion of polysilicon 3922 has been oxidized, thereby forming oxide 4126. Polysilicon 4122 remains beneath oxide 4126.

[0077] Fig.42 Display in processing Fig.41 After the structure 4100 follows Fig.21 4126. The exposed dielectric spacer 3713 on top of the oxide 4126 has been removed. Decapping and wet etching may be applied to recess the exposed dielectric spacer 3713. Decapping is a process that removes residual material at the surface formed by different elements, such as the dielectric spacer 3713 with the oxide 4126. The dielectric spacer 3713 has been removed from the slit area 3933. The opening 4027 has been enlarged to the opening 4227.

[0078] Fig.43 Display in processing Fig.42 After the structure 4200, follow Fig.21 A cross section of structure 4300 processed in the direction 2131 of FIG. 4200 has been formed with dielectric 4313 for performing a replacement gate process on a SGD transistor formed with a segmented drain. Dielectric 4313 may be a deposited nitride. The space between the pillars may be approximately one to two thicknesses of dielectric material 613.

[0079] Fig.44 Display in processing Fig.43 After the structure 4300, follow Fig.21 A cross section of structure 4400 processed in direction 2131. Dielectric 4426 has been formed in slit region 3933 and subjected to a CMP process to planarize dielectric 4426 with dielectric 4313. Dielectric 4426 may be a deposited oxide.

[0080] Fig.45 Display in processing Fig.44 After the structure 4400 follows Fig.21 4131. The dielectric 4313 has been recessed down to a level close to the top of the oxide 4126, thereby forming the dielectric 4513 to leave enough dielectric 4313 for the bridge to replace the gate. The dielectric 4513 can be a nitride. The opening 4527 has been formed.

[0081] Fig.46 Display in processing Fig.45 After the structure 4500 follows Fig.21 4. A cross section of structure 4600 processed in direction 2131 of FIG. 46. Dielectric 4626 has been formed on structure 4500, thereby filling opening 4527. Dielectric 4626 may be an oxide. After dielectric 4626 is formed, dielectric 4626 has been planarized.

[0082] Fig.47 Display in processing Fig.46 After the structure 4600, follow Fig.21 21. A cross section of structure 4700 processed in direction 2131 of FIG. 21. A slit and contact etch has been performed in the pillar to remove the sacrificial dielectric and replace the removed dielectric with a conductive material of the gate 4715 of the SGD transistor and the gate 4715 of the memory cell of the corresponding pillar. The conductive material is formed by filling the slit. The conductive material forming the gate 4715 may include forming titanium nitride and then forming tungsten on the titanium nitride. Prior to forming the titanium nitride, aluminum oxide may be formed on the blocking dielectric 824 of the memory cell of the pillar.

[0083] Fig.48 Display in processing Fig.47 After the structure 4700 Fig.21 Cross section of structure 4800 processed in direction 2131. To isolate the SGD transistor from the SGD transistors of other sub-blocks of the memory array, the isolation location has been patterned and dielectric 4626 and conductive material 4715 have been etched to form trench 4847 to isolate the SGD of the sub-block.

[0084] Fig.49 Display in processing Fig.48 After the structure 4800, follow Fig.214847. A dielectric 4926 has been formed on the surface of the structure 4800 and fills the trench 4847. The dielectric 4926 has been planarized. The dielectric 4926 may be an oxide such as, but not limited to, silicon oxide. Step contacts may be made to the gates of the SGD transistors and the gates of the memory cells of the pillars of the memory array.

[0085] Fig.50 Display in processing Fig.49 After the structure 4900, follow Fig.21 A cross section of structure 5000 processed in the direction 2131 of FIG. An opening 5057 from the drain contact 1320 of the pillar to the line contact for the digit line of the memory cell of the pillar has been patterned and etched. Formation of the memory device may continue with back end of line (BEOL) processing.

[0086] Fig.51 5 is a flow chart of an embodiment of an example method 5100 for forming a memory device. At 5110, a vertical semiconductor pillar is formed for a vertically arranged memory cell of a memory array. At 5120, an SGD transistor integrated with the vertical semiconductor pillar is formed. At 5130, when forming the SGD transistor, a transistor channel structure of the SGD transistor extending vertically from the channel structure of the vertical semiconductor pillar is formed. At 5140, when forming the SGD transistor, a conductive fin extending vertically from a top boundary of the transistor channel structure is formed. The conductive fins are separated from each other by a non-conductive region on the top boundary. The conductive fins and the non-conductive region are structured as a segmented drain of the SGD transistor. At 5150, when forming the SGD transistor, a portion of the segmented drain extending downward from the intersection of the conductive fin and the non-conductive region is formed below the top boundary. At 5160, when forming the SGD transistor, a drain contact contacting the conductive fin is formed. The drain contact includes titanium at the conductive fin.

[0087] Variations of method 5100 or methods similar to method 5100 may include several different embodiments, which may be combined depending on the application of such methods and / or the architecture of such memory devices in which the memory devices are implemented. Such methods may include forming portions of the conductive fins and the segmented drain as n+ regions and forming the transistor channel structure as an n region or an n- region. The transistor channel structure and the channel structure of the vertical pillar may be formed as an n-type polysilicon channel structure.

[0088] Variations of method 5100 or methods similar to method 5100 may include forming a drain contact with titanium nitride formed between titanium and tungsten regions. Variations may include forming a vertical conductive contact coupling the drain to a digit line.

[0089] Variations of method 5100 or methods similar to method 5100 may include using a single replacement gate metallization to form the gate of the SGD transistor and the gate of the memory cell. Variations of method 5100 or methods similar to method 5100 may include etching a single level thickness through a conductive access line to isolate an SGD transistor formed in a sub-block of the memory array from an SGD transistor of another sub-block of the memory array.

[0090] In various embodiments, a first memory device may include a vertical semiconductor pillar coupled to a memory cell, a digit line, and a transistor for coupling the digit line to the vertical semiconductor pillar. The vertical semiconductor pillar may have a channel structure arranged as a channel portion of the memory cell. The transistor may include a gate, a gate dielectric, a transistor channel structure separated from the gate by the gate dielectric, wherein the transistor channel structure is vertically integrated with the channel structure of the memory cell of the vertical semiconductor pillar. The transistor may also include a segmented drain having a conductive fin integrated with the transistor channel structure and extending vertically from the top boundary of the transistor channel structure. The segmented drain includes conductive fins separated from each other by a non-conductive region on the top boundary. The segmented drain also includes a portion extending downward from the intersection of the conductive fin and the non-conductive region below the top boundary. A drain contact contacts the conductive fin, wherein the drain contact includes titanium at the conductive fin.

[0091] Variations of this first memory device or similar memory devices may include several different embodiments, which may be combined depending on the application of such memory devices and / or the architecture in which such memory devices are implemented. Such memory devices may include conductive fins that are more heavily doped than the transistor channel structure. The transistor channel structure and the channel structure of the vertical pillars may include n-type polysilicon. Variations of the first memory device may include a drain contact having titanium nitride and tungsten. The drain contact may include titanium nitride arranged between titanium and tungsten. The drain contact may be coupled to a digit line via a vertical conductive contact. The vertical conductive contact may include tungsten. Variations may include a segmented drain with 6 fins.

[0092] In various embodiments, a second memory device may include a digit line, a vertical semiconductor pillar coupled to a memory cell of a memory array, and an SGD transistor. The vertical semiconductor pillar may have a polysilicon channel structure arranged as a channel portion of the memory cell. The SGD transistor may include a polysilicon transistor channel structure and a segmented drain. The polysilicon transistor channel structure may be integrated with the polysilicon channel structure. The segmented drain may have a conductive fin integrated with the polysilicon transistor channel structure, wherein the conductive fin extends vertically from a top boundary of the polysilicon transistor channel structure. The conductive fins are separated from each other by a non-conductive region of the segmented drain on the top boundary. The segmented drain may include a portion extending downward from an intersection of the conductive fin and the non-conductive region below the top boundary. The drain contact may contact the conductive fin, wherein the drain contact may include titanium at the conductive fin. A memory controller of the second memory device may include a processing circuit system. The memory controller may be structured to perform an erase operation on the memory cell of the vertical semiconductor pillar by applying an erase voltage to the gate of the SGD transistor that electrically couples the vertical semiconductor pillar to the digit line.

[0093] Variations of this second memory device or similar memory devices may include a number of different embodiments, which may be combined depending on the application of such memory devices and / or the architecture in which such memory devices are implemented. Such memory devices may include a memory array structured into a plurality of sub-blocks, wherein each sub-block includes one or more vertical semiconductor pillars coupled to a plurality of memory cells. The SGD transistor may be located in a first sub-block of the plurality of sub-blocks and may be isolated from the SGD transistors of an adjacent sub-block by a dielectric region having a thickness of the level of an access line conductor.

[0094] Variations of this second memory device or similar memory devices may include conductive fins structured as n+ fins and the titanium at the n+ fins may be in a titanium silicide composition. Variations may include a drain contact coupled to a digit line through a vertical tungsten contact. Features of the first memory device may be implemented in the second memory device and features of the second memory device may be implemented in the first memory device. The first memory device, the second memory device, and variations thereof may include one or more other features taught herein.

[0095] although Figures 6 to 50 The method description forms a function similar to Figure 4 402, but other channel structures can be formed using variations of these methods. For example, the teachings of these methods can be implemented to form a SGD transistor similar to Figure 1 , 2 And the structures 102, 202 and 302 of 3.

[0096] Fig.52A block diagram of an example memory device 5200 is illustrated that includes a memory array 5262 having a plurality of memory cells 5263 and one or more circuits or components for providing communication with or performing one or more memory operations on the memory array 5262. The memory device 5200 may be a memory die, such as, but not limited to, a NAND memory die. The memory device 5200 may include a row decoder 5266, a column decoder 5268, a sub-block driver 5264, a sense amplifier 5282, a page buffer 5284, a selector 5286, an input / output (I / O) circuit 5288, and a memory controller 5270. The memory controller 5270 may include processing circuitry (including one or more processors 5275) and may be configured to perform operations of the memory device 5200 by executing instructions 5277. The memory controller 5270 may be coupled to registers 5271 that may contain parameter data for the memory controller 5270. For purposes of the present examples, the instructions 5277 may be executed by a memory within or dedicated to the memory controller 5270. In other examples, at least some portions of the instructions executed by the memory controller 5270 may be stored in other memory structures and, for example, loaded into a local (memory controller) memory for execution by the memory controller 5270. The operations may include an erase algorithm using SGD transistors coupling a string of memory cells to a digit line, wherein each SGD transistor has a segmented drain having one or more fins separated by one or more non-conductive regions, wherein the fins and non-conductive regions extend vertically from a transistor channel region of a given SGD transistor, as taught herein. The segmented drain and transistor channel region of each SGD transistor may be formed by Figure 1 , 2 , 3, 4 and 5 or one of the corresponding structures 102, 202, 302, 402 and 502 of , , 3, 4 and 5 or a similar structure defined by segmenting the drain.

[0097] The memory cells 5263 of the memory array 5262 may be arranged into blocks, such as first and second blocks 5262A, 5262B. Each block may include sub-blocks. For example, the first block 5262A may include first and second sub-blocks 5262A0, 5262A1, 5262A2, 5262A3, 5262A4, 5262A5, 5262A6, 5262A7, 5262A8, 5262A9, 5262A10, 5262A11, 5262A12, 5262A13, 5262A14, 5262A15 N , and the second block 5262B may include the first and second sub-blocks 5262B0, 5262B NEach sub-block may include a number of physical pages, where each page includes a number of memory cells 5263. Although described herein as having two blocks, where each block has two sub-blocks, and each sub-block has a number of memory cells 5263, in other examples, the memory array 5262 may include more or fewer blocks, sub-blocks, memory cells, etc. In other examples, the memory cells 5263 may be arranged into a number of rows, columns, pages, sub-blocks, blocks, etc. and accessed using, for example, access lines 5215, data lines 5225, or one or more select gates, source lines, etc.

[0098] The memory controller 5270 may control the memory operation of the memory device 5200 according to one or more signals or instructions received on the control line 5254 (including, for example, one or more clock signals or control signals indicating the desired operation (e.g., write, read, erase, etc.)) or address signals (A0 to AX) received on the one or more address lines 5252. One or more devices external to the memory device 5200 may control the value of the control signal on the control line 5254 or the address signal on the address line 5252. Examples of devices external to the memory device 5200 may include, but are not limited to: Fig.52 A host, an external memory controller, a processor, or one or more circuits or components not described in the specification.

[0099] The memory device 5200 may use access lines 5215 and digit lines 5225 to transfer (e.g., write or erase) data to or from (e.g., read) one or more of the memory cells 5263. The row decoder 5266 and column decoder 5268 may receive and decode address signals (A0 to AX) from the address lines 5252, may determine which memory cells 5263 are to be accessed, and may provide signals to the access lines 5215 (e.g., multiple access lines (WL0 to WL100). M ) or one or more of digital lines 5225 (e.g., one or more of multiple digital lines (BL0 to BLN)).

[0100] The memory device 5200 may include sensing circuitry, such as sense amplifiers 5282, configured to use the digit lines 5225 to determine (e.g., read) data values ​​on the memory cells 5263 or to determine data values ​​written to the memory cells 5263. For example, in a selected string of memory cells 5263, one or more of the sense amplifiers 5282 may read a logic level in the selected memory cell 5263 in response to a read current flowing in the memory array 5262 through the selected string associated with the digit line 5225.

[0101] One or more devices external to the memory device 5200 may communicate with the memory device 5200 using I / O lines (DQ0 to DQN) 5276, address lines 5252 (A0 to AX), or control lines 5254. The I / O circuits 5288 may use the I / O lines 5276 to transfer data values ​​into and out of the memory device 5200, such as into and out of the page buffers 5284 or the memory array 5262, in accordance with, for example, the control lines 5254 and the address lines 5252. The page buffers 5284 may store data received from one or more devices external to the memory device 5200 before the data is programmed into the relevant portions of the memory array 5262, or may store data read from the memory array 5262 before the data is transmitted to one or more devices external to the memory device 5200.

[0102] The column decoder 5268 may receive address signals (A0 to AX) and decode them into one or more column select signals (CSEL1 to CSEL2). N ). The selector 5286 (eg, a selection circuit) may receive column selection signals (CSEL1 to CSEL N ) and selects data in the page buffer 5284 representing a data value read from or programmed into the memory cell 5263. The selected data can be transmitted between the page buffer 5284 and the I / O circuit 5288 using the second data line 5278.

[0103] The memory controller 5270 may receive positive and negative supply signals, such as a supply voltage (Vcc) 5253 and a negative supply (Vss) 5256 relative to Vcc (e.g., ground potential), from an external source or supply, such as an internal or external battery, an AC / DC converter, etc. The memory controller 5270 may include a regulator 5258 for internally providing the positive or negative supply signals.

[0104] To program or write data to a memory cell, a program voltage (VPGM) (eg, one or more program pulses, etc.) may be applied to a selected access line (eg, WL i ) and thus applied to the control gate of each memory cell coupled to the selected access line. The programming pulse may, for example, start at or near 15V and, in certain examples, may increase in magnitude during each programming pulse application. When the programming voltage is applied to the selected access line, a potential, such as a ground potential (e.g., Vss), may be applied to the digit line and substrate (and thus the channel structure between the source and drain) of the memory cell targeted by programming, resulting in charge transfer (e.g., direct injection or Fowler-Nordheim (FN) tunneling, etc.) from the channel structure to the floating gate of the targeted memory cell.

[0105] Vpass may be applied to one or more access lines having memory cells not targeted by programming, or an inhibit voltage (e.g., Vcc) may be applied to digit lines having memory cells not targeted by programming to, for example, inhibit charge transfer from the pass structure to the floating gates of such non-target memory cells. The pass voltage may vary, for example, depending on the proximity of the applied pass voltage to the access lines targeted by programming. The inhibit voltage may include a supply voltage (Vcc) relative to a ground potential (e.g., Vss), such as a voltage from an external source or supply (e.g., a battery, an AC / DC converter, etc.).

[0106] As an example, if a programming voltage (e.g., 15V or the like) is applied to a particular access line (e.g., WL4), a pass voltage of 10V (lower than the programming voltage) may be applied to one or more other access lines (e.g., WL3, WL5, etc.) to inhibit programming of non-target memory cells or retain values ​​stored on such memory cells that are not targeted for programming. As the distance between the applied programming voltage and the non-target memory cells increases, the pass voltage used to avoid programming the non-target memory cells may decrease. For example, when a programming voltage of 15V is applied to WL4, a pass voltage of 10V may be applied to WL3 and WL5, a pass voltage of 8V may be applied to WL2 and WL6, a pass voltage of 7V may be applied to WL1 and WL7, and so on. In other examples, the pass voltages or the number of access lines, etc. may be higher or lower, more or less.

[0107] Between applying one or more programming pulses (e.g., VPGM), a verify operation may be performed to determine whether the selected memory cell has reached its intended programming state. If the selected memory cell has reached its intended programming state, it may be inhibited from further programming. If the selected memory cell has not yet reached its intended programming state, additional programming pulses may be applied. If the selected memory cell has not reached its intended programming state after a certain number (e.g., a maximum number) of programming pulses, the selected memory cell or a string, block, or page associated with the selected memory cell may be marked as defective.

[0108] In order to erase a memory cell or a group of memory cells (e.g., erasure is typically performed in blocks or sub-blocks), an erase voltage (Vers) (e.g., typically VPGM) may be applied to the substrate (and therefore the channel structure between the source and drain) of the memory cell targeted by the erase (e.g., using one or more digit lines, select gates, etc.), while the access line of the target memory cell is maintained at a potential (e.g., ground potential (e.g., Vss)), thereby causing charge transfer (e.g., direct injection or FN tunneling, etc.) from the floating gate of the target memory cell to the channel structure.

[0109] When the host as a user device sends an address to the memory device 5200, it may typically have identification of a block, page, and column. The identification of the block is used to select the block of interest for the operation. The identification of the page is used to select the WL on which the page resides, and it is also used to select a specific sub-block because the WL is shared between the sub-blocks of the block. The sub-block on which the page resides is decoded and this sub-block is selected. The address provided by the user device is used to turn on and off the selector device and access the memory cell. In typical operation, only one sub-block is selected so that the SGD of one sub-block is activated.

[0110] Based on the address provided by the user device, the memory controller 5270 can select any sub-block or all sub-blocks. The memory controller 5270 can generate a sub-block address for the sub-block driver 5264 and select any sub-block or all sub-blocks. The memory controller 5270 can send WL information to the row decoder 5266 and send the column address to the column decoder 5268.

[0111] The sub-block driver 5264 may include a select line 5255SL 0-0 …SL K-J The select lines 5255 may be coupled to different SGD transistors and different SGS transistors in different blocks. Multiple input signals may be assigned to each individual driver, depending on the different voltages designed for operation of the respective driver during erase operations, program operations, and read operations. The appropriate operating signals may be received from the sub-block drivers 5264 via the select lines 5255 (SL (子块#) -(SGD# or SGS#))SL 0-0 …SL K-J Sent to memory array 5262.

[0112] Electronic devices, such as mobile electronic devices (e.g., smart phones, tablets, etc.), electronic devices used in automotive applications (e.g., automotive sensors, control units, driver assistance systems, passenger safety or comfort systems, etc.), and Internet-connected appliances or devices (e.g., Internet of Things (IoT) devices, etc.) have different storage requirements that depend, among other things, on the type of electronic device, the usage environment, performance expectations, etc. An electronic device can be divided into several main components: a processor (e.g., a central processing unit (CPU) or other main processor); a memory (e.g., one or more volatile or non-volatile RAM memory devices, such as DRAM, mobile or low-power double data rate synchronous DRAM (DDR SDRAM), etc.); and a storage device (e.g., an NVM device, such as flash memory, ROM, SSD, multimedia card (MMC) or other memory card structure or assembly, etc.). In some examples, an electronic device may include a user interface (e.g., a display, a touch screen, a keyboard, one or more buttons, etc.), a graphics processing unit (GPU), a power management circuit, a baseband processor, or one or more transceiver circuits, etc.

[0113] Following are example devices and methods according to the teachings herein.

[0114] An example memory device 1 may include: a vertical semiconductor pillar coupled to a memory cell, the vertical semiconductor pillar having a channel structure arranged as a channel portion of the memory cell; a digit line; and a transistor for coupling the digit line to the vertical semiconductor pillar, the transistor comprising: a gate and a gate dielectric; a transistor channel structure separated from the gate by the gate dielectric, the transistor channel structure being vertically integrated with the channel structure of the memory cell of the vertical semiconductor pillar; a segmented drain having a conductive fin integrated with the transistor channel structure and extending vertically from a top boundary of the transistor channel structure, the conductive fins being separated from each other by a non-conductive region on the top boundary, the segmented drain comprising a portion extending downward from an intersection of the conductive fin and the non-conductive region below the top boundary; and a drain contact contacting the conductive fin, the drain contact comprising titanium at the conductive fin.

[0115] Example memory device 2 may include features of example memory device 1 and may include: the conductive fin being more heavily doped than the transistor channel structure.

[0116] Example memory device 3 may include features of example memory device 2 and any of the preceding example memory devices and may include: the transistor channel structure and the channel structure of the vertical pillars including n-type polysilicon.

[0117] Example memory device 4 may include features of example memory device 3 and any of the preceding example memory devices and may include that the drain contact includes titanium nitride and tungsten.

[0118] Example memory device 5 may include features of example memory device 4 and any of the preceding example memory devices and may include: the drain contact including the titanium nitride arranged between the titanium and the tungsten.

[0119] Example memory device 6 may include features of any of the foregoing example memory devices and may include: the drain contact being coupled to the digit line by a vertical conductive contact.

[0120] Example memory device 7 may include features of example memory device 6 and any of the preceding example memory devices and may include that the vertical conductive contacts include tungsten.

[0121] Example memory device 8 may include features of any of the foregoing example memory devices and may include: the segmented drain having 6 conductive fins.

[0122] In example memory device 9, any of the memory devices of example memory devices 1-8 may include a memory device incorporated into an electronic device further including a host processor and a communication bus extending between the host processor and the memory device.

[0123] In example memory device 10, any of the memory devices of example memory devices 1-9 may be modified to include any structure present in another of example memory devices 1-9.

[0124] In example memory device 11, any apparatus associated with the memory devices of example memory devices 1-10 may further include a machine-readable storage device configured to store instructions as a physical state, wherein the instructions may be used to perform one or more operations of the apparatus.

[0125] In example memory device 12, any of the memory devices of example memory devices 1-11 may operate according to any of the following example methods 1-11 of forming a memory device.

[0126] An example memory device 13 may include: a digit line; a vertical semiconductor pillar coupled to a memory cell of a memory array, the vertical semiconductor pillar having a polysilicon channel structure arranged as a channel portion of the memory cell; a drain-side select gate (SGD) transistor comprising: a polysilicon transistor channel structure integrated with the polysilicon channel structure; a segmented drain having a conductive fin integrated with the polysilicon transistor channel structure and extending vertically from a top boundary of the polysilicon transistor channel structure, the conductive fins being separated from each other by a non-conductive region on the top boundary, the segmented drain comprising a portion extending downwardly from an intersection of the conductive fin and the non-conductive region below the top boundary; a drain contact contacting the conductive fin, the drain contact comprising titanium at the conductive fin; and a memory controller comprising a processing circuit system, the memory controller being configured to perform an erase operation on the memory cell of the vertical semiconductor pillar by applying an erase voltage to a gate of the SGD transistor that electrically couples the vertical semiconductor pillar to the digit line.

[0127] Example memory device 14 may include features of example memory device 13 and may include: the memory array structured into a plurality of sub-blocks, each sub-block including one or more vertical semiconductor pillars coupled to a plurality of memory cells.

[0128] Example memory device 15 may include features of example memory device 14 and any of the aforementioned example memory device 13 and may include: the SGD transistor is positioned in a first sub-block of the plurality of sub-blocks and isolated from SGD transistors of adjacent sub-blocks by a dielectric region having a thickness of a level of an access line conductor.

[0129] Example memory device 16 may include features of any of the aforementioned example memory devices 13-15 and may include: the conductive fins are n+ fins and the titanium is in a titanium silicide composition at the n+ fins.

[0130] Example memory device 17 may include features of any of the foregoing example memory devices 13-16 and may include: the drain contact being coupled to the digit line by a vertical tungsten contact.

[0131] In example memory device 18, any of the memory devices of example memory devices 13-17 may include a memory device incorporated into an electronic device further including a host processor and a communication bus extending between the host processor and the memory device.

[0132] In example memory device 19 , any of the memory devices of example memory devices 13 - 18 may be modified to include any structure present in another of example memory devices 13 - 18 .

[0133] In example memory device 20, any apparatus associated with the memory devices of example memory devices 13-19 may further include a machine-readable storage device configured to store instructions as a physical state, where the instructions may be used to perform one or more operations of the apparatus.

[0134] In example memory device 21, any of the memory devices of example memory devices 13-20 may operate according to any of the following example methods 1-11 of forming a memory device.

[0135] In example memory device 22, any of the memory devices of example memory devices 1-21 may be modified to include any structure present in another of example memory devices 1-21.

[0136] An example method 1 for forming a memory device may include: forming a vertical semiconductor pillar for vertically arranged memory cells of a memory array; forming a drain-side select gate (SGD) transistor integrated with the vertical semiconductor pillar, which includes: forming a transistor channel structure of the SGD transistor extending vertically from a channel structure of the vertical semiconductor pillar; forming a conductive fin extending vertically from a top boundary of the transistor channel structure, the conductive fins being separated from each other by a non-conductive region on the top boundary, the conductive fins and the non-conductive region being structured as a segmented drain of the SGD transistor; forming a portion of the segmented drain extending downward from an intersection of the conductive fin and the non-conductive region below the top boundary; and forming a drain contact contacting the conductive fin, the drain contact including titanium at the conductive fin.

[0137] Example method 2 of forming a memory device may include features of example method 1 of forming a memory device and may include forming the conductive fin and the portion of the segmented drain as an n+ region and forming the transistor channel structure as an n region or an n- region.

[0138] Example method 3 of forming a memory device may include features of example method 2 of forming a memory device and any of the preceding example methods of forming a memory device and may include forming the transistor channel structure and the channel structure of the vertical pillar as an n-type polysilicon channel structure.

[0139] Example method 4 of forming a memory device may include features of any of the preceding example methods of forming a memory device and may include: forming the drain contact includes forming titanium nitride between the titanium and tungsten regions.

[0140] Example method 5 of forming a memory device may include features of any of the preceding example methods of forming a memory device and may include: forming a vertical conductive contact coupling the segmented drain to a digit line.

[0141] Example method 6 of forming a memory device may include features of any of the preceding example methods of forming a memory device and may include: forming a gate of the SGD transistor and a gate of the memory cell using a single replacement gate metallization.

[0142] Example method 7 of forming a memory device may include features of any of the preceding example methods of forming a memory device and may include: etching a single level thickness through a conductive access line to isolate the SGD transistor formed in a sub-block of the memory array from SGD transistors of another sub-block of the memory array.

[0143] In example method 8 of forming a memory device, any of example methods 1-7 of forming a memory device may be performed in forming an electronic device further comprising a host processor and a communication bus extending between the host processor and the memory device.

[0144] In example method 9 of forming a memory device, any of the example methods 1-8 of forming a memory device may be modified to include operations set forth in any other of the example methods 1-8 of forming a memory device.

[0145] In example method 10 of forming a memory device, any of example methods 1-9 of forming a memory device may be implemented at least in part by using instructions stored as a physical state in one or more machine-readable storage devices.

[0146] Example method 11 of forming a memory device may include features of any of the foregoing example methods 1-10 of forming a memory device and may include performing functions associated with any of the features of example memory devices 1-22.

[0147] An example machine-readable storage device storing instructions that, when executed by one or more processors, cause the machine to perform operations may include instructions for performing functions associated with any feature of example memory devices 1-22 or performing methods associated with any feature of example methods 1-11.

[0148] Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that any arrangement calculated to achieve the same purpose may be substituted for the specific embodiments shown. Various embodiments use permutations and / or combinations of the embodiments described herein. The above description is intended to be illustrative and not limiting, and the wording or terminology employed herein is for descriptive purposes. Combinations of the above embodiments with other embodiments will be apparent to those of ordinary skill in the art after studying the above description.

Claims

1. A memory device, comprising: a vertical semiconductor pillar coupled to a memory cell, the vertical semiconductor pillar having a channel structure arranged as a channel portion of the memory cell; Digital Line; and a transistor for coupling the digit line to the vertical semiconductor pillar, the transistor comprising: Gate and gate dielectric; a transistor channel structure separated from the gate by the gate dielectric, the transistor channel structure being vertically integrated with the channel structure of the memory cell of the vertical semiconductor pillar; a segmented drain having a conductive fin integrated with the transistor channel structure and extending vertically from a top boundary of the transistor channel structure, the conductive fins being separated from each other by a non-conductive region on the top boundary, the segmented drain including a portion extending downwardly from an intersection of the conductive fin and the non-conductive region below the top boundary; and A drain contact contacts the conductive fin, the drain contact comprising titanium at the conductive fin.

2. The memory device of claim 1, wherein the conductive fin is more heavily doped than the transistor channel structure.

3. The memory device of claim 2, wherein the transistor channel structure and the channel structure of the vertical pillar comprise n-type polysilicon.

4. The memory device of claim 1, wherein the drain contact comprises titanium nitride and tungsten.

5. The memory device of claim 4, wherein the drain contact comprises the titanium nitride arranged between the titanium and the tungsten.

6. The memory device of claim 1, wherein the drain contact is coupled to the digit line through a vertical conductive contact.

7. The memory device of claim 6, wherein the vertical conductive contacts comprise tungsten.

8. The memory device of claim 1, wherein the segmented drain has 6 conductive fins.

9. A memory device comprising: Digital Line; a vertical semiconductor pillar coupled to a memory cell of a memory array, the vertical semiconductor pillar having a polysilicon channel structure arranged as a channel portion of the memory cell; A drain side select gate SGD transistor comprising: a polysilicon transistor channel structure integrated with the polysilicon channel structure; and a segmented drain having a conductive fin integrated with the polysilicon transistor channel structure and extending vertically from a top boundary of the polysilicon transistor channel structure, the conductive fins being separated from each other by a non-conductive region on the top boundary, the segmented drain including a portion extending downwardly from an intersection of the conductive fin and the non-conductive region below the top boundary; a drain contact contacting the conductive fin, the drain contact comprising titanium at the conductive fin; and A memory controller includes processing circuitry configured to perform an erase operation on the memory cells of the vertical semiconductor pillar by applying an erase voltage to a gate of the SGD transistor electrically coupling the vertical semiconductor pillar to the digit line.

10. The memory device of claim 9, wherein the memory array is structured into a plurality of sub-blocks, each sub-block comprising one or more vertical semiconductor pillars coupled to a plurality of memory cells.

11. The memory device of claim 10, wherein the SGD transistor is located in a first sub-block of the plurality of sub-blocks and is isolated from SGD transistors of adjacent sub-blocks by a dielectric region having a thickness at the level of an access line conductor.

12. The memory device of claim 9, wherein the conductive fin is an n+ fin and the titanium is in a titanium silicide composition at the n+ fin.

13. The memory device of claim 9, wherein the drain contact is coupled to the digit line through a vertical tungsten contact.

14. A method of forming a memory device, the method comprising: forming vertical semiconductor pillars for vertically arranged memory cells of a memory array; forming a drain side select gate SGD transistor integrated with the vertical semiconductor pillar, comprising: forming a transistor channel structure of the SGD transistor extending vertically from the channel structure of the vertical semiconductor pillar; forming conductive fins extending vertically from a top boundary of the transistor channel structure, the conductive fins being separated from each other by non-conductive regions on the top boundary, the conductive fins and non-conductive regions being structured as a segmented drain of the SGD transistor; forming a portion of the segmented drain extending downwardly from an intersection of the conductive fin and the non-conductive region below the top boundary; and A drain contact is formed contacting the conductive fin, the drain contact comprising titanium at the conductive fin. 15 . The method of claim 14 , wherein the method includes forming the portions of the conductive fin and the segmented drain as n+ regions and forming the transistor channel structure as an n region or an n− region.

16. The method of claim 15, wherein the method includes forming the transistor channel structure and the channel structure of the vertical pillar as an n-type polysilicon channel structure.

17. The method of claim 14, wherein forming the drain contact comprises forming titanium nitride between the titanium and tungsten regions.

18. The method of claim 14, wherein the method includes forming a vertical conductive contact coupling the segmented drain to a digit line.

19. The method of claim 14, wherein the method includes forming a gate of the SGD transistor and a gate of the memory cell using a single replacement gate metallization.

20. The method of claim 14, wherein the method includes etching a single level thickness through a conductive access line to isolate the SGD transistor formed in a sub-block of the memory array from SGD transistors of another sub-block of the memory array.

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