Method for manufacturing a semiconductor device

Abstract

The present invention discloses a method for manufacturing a semiconductor device, which relates to the field of semiconductor technology and is intended to improve the yield of semiconductor devices. The method for manufacturing a semiconductor device comprises: forming a fin-shaped structure on a semiconductor substrate. The fin-shaped structure comprises an alternating first sacrificial layer and a channel layer, and an alternating second sacrificial layer and a third sacrificial layer. The material of one of the second sacrificial layer and the third sacrificial layer comprises silicon or silicon germanium, and the material of the other comprises silicon germanium or germanium. The difference in germanium content between the second sacrificial layer and the third sacrificial layer is less than 15%, and the second sacrificial layer is doped with an etching aid. A mask structure is formed across the fin-shaped structure. At least under the accelerated etching action of the etching aid, the second sacrificial layer is selectively removed to form a first dielectric filling region. A first middle dielectric isolation layer is formed within the first dielectric filling region. The first sacrificial layer, the channel layer, the first middle dielectric isolation layer, and the third sacrificial layer not covered by the mask structure are removed.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for manufacturing a semiconductor device. Background Art

[0002] The three-dimensional stacked complementary transistor includes vertically stacked N-type transistors and P-type transistors, eliminating the lateral spacing between the N-type transistors and the P-type transistors, which allows the effective channel width to be further increased, thereby improving the operating performance and integration of semiconductor devices.

[0003] However, existing methods for manufacturing three-dimensional stacked complementary transistors have high requirements on processing technology, making the manufacturing of three-dimensional stacked complementary transistors more difficult and resulting in a low yield of the three-dimensional stacked complementary transistors. Summary of the Invention

[0004] The present invention aims to provide a method for manufacturing a semiconductor device that alleviates existing issues in the prior art, such as the need to consider stress distribution and stress matching between films due to the significant material differences between the second and third sacrificial layers. This reduces the critical thickness limitations of epitaxial growth, further simplifies the manufacturing process for the central dielectric isolation layer, and improves the yield of semiconductor devices.

[0005] To achieve the above objectives, the present invention provides a method for manufacturing a semiconductor device, comprising: first, forming a fin structure on a semiconductor substrate. Along the thickness direction of the semiconductor substrate, the fin structure comprises alternating first sacrificial layers and channel layers, and alternating second sacrificial layers and third sacrificial layers. The alternating first sacrificial layers and channel layers are located on either side of the alternating second sacrificial layers and third sacrificial layers along the thickness direction. The bottom and top layers of the alternating first sacrificial layers and channel layers are both first sacrificial layers. The bottom and top layers of the alternating second sacrificial layers and third sacrificial layers are both second sacrificial layers. One of the second and third sacrificial layers comprises silicon or silicon-germanium, and the other comprises silicon-germanium or germanium. The difference in germanium content between the second and third sacrificial layers is less than 15%, and the second sacrificial layer is doped with an etch assist agent. Next, forming a mask structure across the fin structure. Next, selectively removing the second sacrificial layer, at least under the accelerated etching action of the etch assist agent, to form a first dielectric fill region. The third sacrificial layer remains. Next, a first middle dielectric isolation layer is formed within the first dielectric fill region. Next, the first sacrificial layer, channel layer, first middle dielectric isolation layer, and third sacrificial layer not covered by the mask structure are removed. Next, a first source region and a first drain region are formed on either side of the remaining first sacrificial layer and the channel layer below the remaining first middle dielectric isolation layer. Next, an insulating layer is formed on the first source region and the first drain region. Next, a second source region and a second drain region are formed on the insulating layer and on either side of the remaining first sacrificial layer and the channel layer above the remaining first middle dielectric isolation layer. The conductivity type of the second source region and the second drain region is opposite to the conductivity type of the first source region and the first drain region.

[0006] When the above technical solution is adopted, in the manufacturing method provided by the present invention, the first sacrificial layer, the second sacrificial layer and the third sacrificial layer respectively have different functions. Specifically, the remaining channel layer (the remaining channel layer is used to form the channel region) will be released by selectively removing the portion of the first sacrificial layer corresponding to the gate formation region, so as to form a gate stack structure surrounding the periphery of the remaining channel layer. Subsequently, the second sacrificial layer will be selectively etched to form a first middle dielectric isolation layer for isolating the gate stack structure of the upper device included in the three-dimensional stacked complementary transistor from the gate stack structure of the lower device. As for the above-mentioned third sacrificial layer, the position where the portion of the third sacrificial layer corresponding to the gate formation region is located may subsequently form a gate stack structure, or may form an insulating dielectric material for isolation. Based on this, the existing manufacturing method is to achieve sufficient etching selectivity of the three by completely limiting the types of materials of the first sacrificial layer, the second sacrificial layer and the third sacrificial layer. In the manufacturing method provided by the present invention, when the material of one of the second sacrificial layer and the third sacrificial layer includes silicon or silicon germanium, and the material of the other includes silicon germanium or germanium, the difference in germanium content between the second sacrificial layer and the third sacrificial layer is less than 15%. At this time, the material difference between the second sacrificial layer and the third sacrificial layer is small, and the corresponding lattice difference between the two is also small. When the materials used for epitaxy are manufactured, the problems of stress distribution and stress matching between thin films that need to be considered due to the large material difference between the second sacrificial layer and the third sacrificial layer in the existing technology can be alleviated, and the limitation of the critical thickness of epitaxy is reduced. There is no need to form more layers of second sacrificial layers and third sacrificial layers with smaller layer thicknesses as in the existing manufacturing method, or there is no need to form a fixed number of second sacrificial layers and third sacrificial layers due to the critical thickness limitation, resulting in a smaller thickness of the insulating layer used to isolate the first source region and the first drain region, and the second source region and the second drain region, to prevent leakage.

[0007] Furthermore, the second sacrificial layer is doped with an etching aid. With this arrangement, the second sacrificial layer can subsequently be selectively removed, at least under the accelerated etching action of the etching aid, to form the first dielectric filling region while retaining the third sacrificial layer, thereby improving the yield of the semiconductor device. Furthermore, the manufacturing method provided by the present invention forms the first central dielectric isolation layer before performing source and drain etching. Although the aspect ratio of the fin structure may still be large, even if the insulating dielectric material at the bottom of the gap between adjacent fin structures is not completely removed during the etching process of the insulating dielectric material used to form the first central dielectric isolation layer, this will not affect the subsequent formation of the first source region and the first drain region of the underlying device, nor will it affect the contact between the first source region and the first drain region of the underlying device and the first channel region. Furthermore, the insulating dielectric material remaining at the bottom of the gap between adjacent fin structures can further isolate different semiconductor devices formed based on different fin structures, reducing the risk of leakage, thereby increasing the yield of the manufactured semiconductor device and improving the operating performance of the manufactured semiconductor device.

[0008] In one example, the etching auxiliary agent is an N-type dopant.

[0009] In one example, a wet etching process or an isotropic dry etching process is used to selectively remove the second sacrificial layer.

[0010] In one example, the doping concentration of the etching auxiliary agent in the second sacrificial layer is greater than or equal to 1E18 cm -3 , and less than or equal to 1E19cm -3 .

[0011] In one example, when a wet etching process is used to selectively remove the second sacrificial layer, the wet etching solution includes a mixed solution of hydrofluoric acid and hydrogen peroxide.

[0012] In one example, when a dry etching process is used to selectively remove the second sacrificial layer, the etching gas includes a mixed gas of CF 4 , O 2 , and He.

[0013] In one example, the thickness of the second sacrificial layer and / or the third sacrificial layer is greater than or equal to 10 nm and less than or equal to 30 nm.

[0014] In one example, an in-situ doping method is used to dope the second sacrificial layer with an etching auxiliary agent.

[0015] In one example, the second sacrificial layer and the third sacrificial layer are made of the same material.

[0016] In one example, the material of the first sacrificial layer is the same as the material of the third sacrificial layer.

[0017] In one example, after removing the first sacrificial layer, the channel layer, the first middle dielectric isolation layer, and the third sacrificial layer not covered by the mask structure, and before forming the first source region and the first drain region on either side of the remaining first sacrificial layer and the channel layer below the remaining first middle dielectric isolation layer, the semiconductor device manufacturing method further includes: removing side edge portions of each remaining first sacrificial layer along the length direction of the fin structure to form a second dielectric filling region. Next, forming inner sidewalls within the second dielectric filling region.

[0018] In one example, the mask structure includes a sacrificial gate.

[0019] In one example, while forming the first middle dielectric isolation layer in the dielectric filling region, gate spacers are formed at least on two sides of the mask structure along the length direction of the fin structure.

[0020] In one example, the material of the first middle dielectric isolation layer includes at least one of SiN, SiCO, and SiCON.

[0021] In one example, after forming the second source region and the second drain region, the method for manufacturing a semiconductor device further includes: forming an interlayer dielectric layer covering the semiconductor substrate. Next, removing the mask structure. Next, removing the remaining first sacrificial layer and the remaining third sacrificial layer. Next, forming a gate stack structure surrounding at least the periphery of the remaining channel layer.

[0022] In one example, when the material of the first sacrificial layer is different from the material of the third sacrificial layer, after removing the mask structure and before removing the remaining first sacrificial layer, the method for manufacturing a semiconductor device includes: removing the third sacrificial layer to form a third dielectric-filled region; and then forming a second middle dielectric isolation layer within the third dielectric-filled region.

[0023] In one example, when the material of the first sacrificial layer is different from the material of the third sacrificial layer, after forming the first middle dielectric isolation layer in the first dielectric filling region, and before forming the first source region and the first drain region on either side of the remaining first sacrificial layer and the channel layer below the remaining first middle dielectric isolation layer, the method for manufacturing a semiconductor device includes: selectively removing the third sacrificial layer to form the third dielectric filling region; forming a second middle dielectric isolation layer in the third dielectric filling region; and removing the first sacrificial layer, the channel layer, the first middle dielectric isolation layer, and the second middle dielectric isolation layer not covered by the mask structure.

[0024] After forming the second source region and the second drain region, the semiconductor device manufacturing method further includes: forming an interlayer dielectric layer covering the semiconductor substrate; removing the mask structure; removing the remaining first sacrificial layer; and forming a gate stack structure surrounding the remaining channel layer.

[0025] In one example, the material of the second middle dielectric isolation layer is the same as the material of the first middle dielectric isolation layer.

[0026] In one example, the dielectric constant of the material of the second middle dielectric isolation layer is smaller than the dielectric constant of the material of the first middle dielectric isolation layer.

[0027] In one example, the material of the first middle dielectric isolation layer includes at least one of SiO2, SiN, SiCO, SiCON, and SiO2-SiF4. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0029] Figure 1 A flow chart of a method for manufacturing a semiconductor device provided by an embodiment of the present invention;

[0030] Figure 2 A schematic diagram of the structure of a semiconductor device manufactured by the manufacturing method provided by an embodiment of the present invention during the manufacturing process Figure 1 ;

[0031] Figure 3 A schematic diagram of the structure of a semiconductor device manufactured by the manufacturing method provided by an embodiment of the present invention during the manufacturing process Figure 2 ;

[0032] Figure 4 A schematic diagram of the structure of a semiconductor device manufactured by the manufacturing method provided by an embodiment of the present invention during the manufacturing process Figure 3 ;

[0033] Figure 5 A schematic diagram of the structure of a semiconductor device manufactured by the manufacturing method provided by an embodiment of the present invention during the manufacturing process Figure 4 ;

[0034] Figure 6 A schematic diagram of the structure of a semiconductor device manufactured by the manufacturing method provided by an embodiment of the present invention during the manufacturing process Figure 5 ;

[0035] Figure 7 A schematic diagram of the structure of a semiconductor device manufactured by the manufacturing method provided by an embodiment of the present invention during the manufacturing process Figure 6 ;

[0036] Figure 8A schematic diagram of the structure of a semiconductor device manufactured by the manufacturing method provided by an embodiment of the present invention during the manufacturing process Figure 7 ;

[0037] Figure 9 A schematic diagram of the structure of a semiconductor device manufactured by the manufacturing method provided by an embodiment of the present invention during the manufacturing process Figure 8 ;

[0038] Figure 10 A schematic diagram of the structure of a semiconductor device manufactured by the manufacturing method provided by an embodiment of the present invention during the manufacturing process Figure 9 ;

[0039] Figure 11 A schematic diagram of the structure of a semiconductor device manufactured by the manufacturing method provided by an embodiment of the present invention during the manufacturing process Figure 10 ;

[0040] Figure 12 A schematic diagram of the structure of a semiconductor device manufactured by the manufacturing method provided by an embodiment of the present invention during the manufacturing process Figure 10 one;

[0041] Figure 13 A schematic diagram of the structure of a semiconductor device manufactured by the manufacturing method provided by an embodiment of the present invention during the manufacturing process Figure 10 two;

[0042] Figure 14 A schematic diagram of the structure of a semiconductor device manufactured by the manufacturing method provided by an embodiment of the present invention during the manufacturing process Figure 10 three;

[0043] Figure 15 A schematic diagram of the structure of a semiconductor device manufactured by the manufacturing method provided by an embodiment of the present invention during the manufacturing process Figure 10 Four;

[0044] Figure 16 A schematic diagram of the structure of a semiconductor device manufactured by the manufacturing method provided by an embodiment of the present invention during the manufacturing process Figure 10 five;

[0045] Figure 17 A schematic diagram of the structure of a semiconductor device manufactured by the manufacturing method provided by an embodiment of the present invention during the manufacturing process Figure 10 six;

[0046] Figure 18 A schematic diagram of the structure of a semiconductor device manufactured by the manufacturing method provided by an embodiment of the present invention during the manufacturing process Figure 10 seven;

[0047] Figure 19A schematic diagram of the structure of a semiconductor device manufactured by the manufacturing method provided by an embodiment of the present invention during the manufacturing process Figure 10 eight;

[0048] Figure 20 A schematic diagram of the structure of a semiconductor device manufactured by the manufacturing method provided by an embodiment of the present invention during the manufacturing process Figure 10 Nine;

[0049] Figure 21 A schematic diagram of the structure of a semiconductor device manufactured by the manufacturing method provided by an embodiment of the present invention during the manufacturing process Figure 2 ten;

[0050] Figure 22 A schematic diagram of the structure of a semiconductor device manufactured by the manufacturing method provided by an embodiment of the present invention during the manufacturing process Figure 2 eleven;

[0051] Figure 23 A schematic diagram of the structure of a semiconductor device manufactured by the manufacturing method provided by an embodiment of the present invention during the manufacturing process Figure 2 twelve;

[0052] Figure 24 A schematic diagram of the structure of a semiconductor device manufactured by the manufacturing method provided by an embodiment of the present invention during the manufacturing process Figure 2 Thirteen;

[0053] Figure 25 A schematic diagram of the structure of a semiconductor device manufactured by the manufacturing method provided by an embodiment of the present invention during the manufacturing process Figure 2 fourteen;

[0054] Figure 26 A schematic diagram of the structure of a semiconductor device manufactured by the manufacturing method provided by an embodiment of the present invention during the manufacturing process Figure 2 fifteen;

[0055] Figure 27 A schematic diagram of the structure of a semiconductor device manufactured by the manufacturing method provided by an embodiment of the present invention during the manufacturing process Figure 2 sixteen;

[0056] Figure 28 A schematic diagram of the structure of a semiconductor device manufactured by the manufacturing method provided by an embodiment of the present invention during the manufacturing process Figure 2 Seventeen;

[0057] Figure 29 A schematic diagram of the structure of a semiconductor device manufactured by the manufacturing method provided by an embodiment of the present invention during the manufacturing process Figure 2 eighteen;

[0058] Figure 30A schematic diagram of the structure of a semiconductor device manufactured by the manufacturing method provided by an embodiment of the present invention during the manufacturing process Figure 2 nineteen;

[0059] Figure 31 A schematic diagram of the structure of a semiconductor device manufactured by the manufacturing method provided by an embodiment of the present invention during the manufacturing process Figure 3 ten;

[0060] Figure 32 A schematic diagram of the structure of a semiconductor device manufactured by the manufacturing method provided by an embodiment of the present invention during the manufacturing process Figure 3 eleven.

[0061] Figure numerals: 11 is a semiconductor substrate, 12 is a fin-shaped structure, 13 is a first sacrificial layer, 14 is a channel layer, 15 is a second sacrificial layer, 16 is a third sacrificial layer, 17 is a shallow trench isolation structure, 18 is a mask structure, 19 is a first dielectric filling area, 20 is a first middle dielectric isolation layer, 21 is a first source region, 22 is a first drain region, 23 is an insulating layer, 24 is a second source region, 25 is a second drain region, 26 is a second dielectric filling area, 27 is an inner sidewall, 28 is a gate sidewall, 29 is an interlayer dielectric layer, 30 is a gate stack structure, 31 is a third dielectric filling area, and 32 is a second middle dielectric isolation layer. DETAILED DESCRIPTION

[0062] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are merely exemplary and are not intended to limit the scope of the present invention. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessary confusion of the concepts of the present invention.

[0063] The accompanying drawings illustrate various structural schematics according to embodiments of the present invention. These figures are not drawn to scale; certain details are exaggerated and may be omitted for clarity. The shapes of the various regions and layers shown in the figures, as well as their relative sizes and positions, are merely exemplary and may deviate in practice due to manufacturing tolerances or technical limitations. Those skilled in the art may design regions / layers with different shapes, sizes, and relative positions as needed.

[0064] In the context of the present invention, when a layer / element is referred to as being "on" another layer / element, the layer / element may be directly on the other layer / element, or an intervening layer / element may exist between them. Furthermore, if a layer / element is "on" another layer / element in one orientation, it may be "below" the other layer / element when the orientation is reversed. To further clarify the technical problems, technical solutions, and beneficial effects of the present invention, the present invention is further described below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are intended solely to illustrate the present invention and are not intended to limit the present invention.

[0065] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Thus, a feature specified as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, "plurality" means two or more, unless otherwise specifically defined. "Several" means one or more, unless otherwise specifically defined.

[0066] In the description of the present invention, it should be noted that, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be understood in a broad sense. For example, they may refer to fixed, detachable, or integral connections; mechanical or electrical connections; direct or indirect connections through an intermediate medium; and may encompass internal communication between two components or interaction between two components. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on specific circumstances.

[0067] The three-dimensional stacked complementary transistor includes vertically stacked N-type transistors and P-type transistors, eliminating the lateral spacing between the N-type transistors and the P-type transistors, which allows the effective channel width to be further increased, thereby improving the operating performance and integration of semiconductor devices.

[0068] However, existing methods for manufacturing three-dimensional stacked complementary transistors have high processing requirements, which makes it difficult to manufacture three-dimensional stacked complementary transistors and is not conducive to improving the performance of three-dimensional stacked complementary transistors. Among them, existing methods for manufacturing three-dimensional stacked complementary transistors mainly include the following two integration schemes:

[0069] The first method: using a monolithic method to manufacture three-dimensional stacked complementary transistors. Specifically, taking the N-type transistor and the P-type transistor as ring-gate transistors, and the P-type transistor is located above the N-type transistor as an example, the process of manufacturing a three-dimensional stacked complementary transistor using the existing manufacturing method is described: First, a fin structure is formed on a semiconductor substrate. The fin structure includes at least two stacked layers. Each stacked layer includes a sacrificial layer and a channel layer located on the sacrificial layer, and the materials of the sacrificial layer and the channel layer are both semiconductor materials. Then, a sacrificial gate and sidewalls are formed across part of the fin structure. The sacrificial gate and sidewalls are used as masks to selectively etch the fin structure to remove the portion of the fin structure exposed outside the sacrificial gate and sidewalls. Then, a first semiconductor material for manufacturing the source and drain regions included in the N-type transistor is formed on the semiconductor substrate. At this point, since the remaining portions of the sacrificial layer and channel layer corresponding to the N-type transistor and P-type transistor are exposed after etching, these remaining portions of the sacrificial layer and channel layer can serve as seed layers for the epitaxial growth of the first semiconductor material. Therefore, the first semiconductor material is formed not only on both sides of the remaining portions of the sacrificial layer and channel layer corresponding to the N-type transistor after etching, but also on both sides of the remaining portions of the sacrificial layer and channel layer corresponding to the P-type transistor after etching. Next, it is necessary to remove the first semiconductor material located on both sides of the remaining portions of the sacrificial layer and channel layer corresponding to the P-type transistor after etching. The remaining portions of the first semiconductor material form the source and drain regions included in the N-type transistor. Then, an epitaxial isolation layer is formed covering the surface of the source and drain regions of the N-type transistor facing away from the substrate; and the source and drain regions of the P-type transistor are formed on the epitaxial isolation layer using an epitaxial growth process. Finally, the sacrificial gate and the portion of the sacrificial layer located within the gate formation area are removed; and a gate stack structure surrounding the periphery of the channel region is formed to obtain a three-dimensional stacked complementary transistor.

[0070] The second method uses a sequential approach to fabricate three-dimensional stacked complementary transistors. This involves forming the bottom layer of transistors using conventional semiconductor device manufacturing processes. After forming the corresponding contact electrodes for the bottom layer transistors, a semiconductor layer is deposited on top of the bottom layer transistors using wafer-to-wafer bonding technology and wafer transfer. The top layer transistors are then integrated onto this semiconductor layer, connecting the top and bottom gates to create a three-dimensional stacked complementary transistor.

[0071] As can be seen from the manufacturing process of the first method described above, the first method for manufacturing a three-dimensional stacked complementary transistor requires the use of an epitaxial process to form a channel layer and a sacrificial layer of semiconductor material. However, epitaxial materials require consideration of inter-film stress distribution and stress matching, posing significant technical challenges in the manufacture of three-dimensional stacked complementary transistors. Furthermore, in the first manufacturing method, the structure has a large aspect ratio. When fabricating the middle dielectric isolation (MDI) used to separate the upper and lower devices, after forming the sacrificial gate and performing source and drain etching, the gap between adjacent fin structures has a large depth-to-width ratio. This can easily lead to difficulty in completely removing the insulating dielectric material at the bottom of the gap between adjacent fin structures after filling the MDI with the insulating dielectric material, thereby affecting the subsequent formation of the source and drain regions of the lower device and compromising device performance. Furthermore, to form the MDI, a sacrificial layer of at least one other material is required. Consequently, in current manufacturing methods, the epitaxially grown channel layer and sacrificial layer contain at least three different semiconductor materials, further increasing the complexity of epitaxial growth. Secondly, due to the limitations of the critical epitaxial thickness, when the differences between different materials are significant, the thickness of the film formed in a single pass can only be reduced to ensure the quality of the formed film. Based on this, if only a fixed number of overlapping sacrificial layers are formed at the position corresponding to the central dielectric isolation, the thickness of the insulating layer separating the first source region and the first drain region, as well as the second source region and the second drain region, will also be relatively small, making it difficult to prevent leakage. To ensure sufficient thickness of the insulating layer, more sacrificial layers need to be formed alternately, which complicates the process.

[0072] Without forming the above-mentioned middle dielectric isolation, on the one hand, it will affect the leakage or interference between the upper and lower devices. On the other hand, when the upper and lower devices use different metal gate materials, it is necessary to fill the gate formation area with protective materials such as spin-coated carbon and perform back etching to expose only the nanostructure of the upper device. At this time, if there is no middle dielectric isolation, when etching back the above-mentioned protective material, the part of the protective material located below the nanostructure included in the upper device is difficult to clean, thereby affecting the subsequent formation of the first layer of metal gate and affecting device performance.

[0073] As for the second method of manufacturing three-dimensional stacked complementary transistors mentioned above, the bonding scheme it adopts has technical challenges such as alignment, and has high process requirements, which makes the manufacturing of three-dimensional stacked complementary transistors more difficult and is not conducive to improving the working performance of three-dimensional stacked complementary transistors.

[0074] In order to solve the above-mentioned technical problems, an embodiment of the present invention provides a method for manufacturing a semiconductor device. Specifically, in the method for manufacturing a semiconductor device provided by an embodiment of the present invention, the difference in germanium content between the second sacrificial layer and the third sacrificial layer is less than 15%. In this case, the material difference between the second sacrificial layer and the third sacrificial layer is small, which can alleviate the problems in the prior art that require consideration of stress distribution and stress matching between thin films due to the large material difference between the second sacrificial layer and the third sacrificial layer. Furthermore, the formation of the first middle dielectric isolation layer is performed in advance before source and drain etching, which does not affect the subsequent formation of the first source region and the first drain region of the lower-layer device, as well as their respective contact with the first channel region, thereby increasing the yield of the manufactured semiconductor device.

[0075] like Figure 1 As shown, the embodiment of the present invention provides a method for manufacturing a semiconductor device. Figures 2 to 32 The manufacturing process is described by using a cross-sectional view or a stereoscopic view of the operation shown. Specifically, the manufacturing method of the semiconductor device includes the following steps:

[0076] First, if Figure 2 and Figure 3 As shown, a fin structure 12 is formed on a semiconductor substrate 11. Along the thickness direction of the semiconductor substrate 11, the fin structure 12 includes an alternating first sacrificial layer 13 and a channel layer 14, and an alternating second sacrificial layer 15 and a third sacrificial layer 16. The alternating first sacrificial layer 13 and channel layer 14 are located on either side of the alternating second sacrificial layer 15 and third sacrificial layer 16 along the thickness direction. The bottom and top layers of the alternating first sacrificial layer 13 and channel layer 14 are both first sacrificial layers 13. The bottom and top layers of the alternating second sacrificial layer 15 and third sacrificial layer 16 are both second sacrificial layers 15. One of the second sacrificial layer 15 and the third sacrificial layer 16 is made of silicon or silicon germanium, and the other is made of silicon germanium or germanium. The difference in germanium content between the second sacrificial layer 15 and the third sacrificial layer 16 is less than 15%, and the second sacrificial layer 15 is doped with an etch aid.

[0077] Specifically, along the thickness direction of the semiconductor substrate, the alternating first sacrificial layers and channel layers, located below the alternating second and third sacrificial layers, are used to fabricate the lower-layer device in a three-dimensional stacked complementary transistor. Based on this, the number and materials of the alternating first sacrificial layers and channel layers, located below the alternating second and third sacrificial layers, can be determined based on the requirements for the lower-layer device in actual application scenarios.

[0078] Among them, the number of layers of the channel layer located below the alternatingly stacked second sacrificial layer and the third sacrificial layer can be one layer or multiple layers. The material of the channel layer can include any semiconductor material such as silicon, silicon germanium or germanium. In addition, since it is necessary to release the first channel region included in the lower device by removing the first sacrificial layer covered by the mask structure in the future. Moreover, when the second sacrificial layer is selectively removed, the first sacrificial layer and the third sacrificial layer need to be retained, so the material of the first sacrificial layer can be any semiconductor material that has a certain etching selectivity with the materials of the channel layer and the second sacrificial layer, respectively. For example: when the material of the channel layer is silicon and the material of the second sacrificial layer is silicon germanium, the material of the first sacrificial layer can be silicon germanium or germanium, and the germanium content in the first sacrificial layer and the second sacrificial layer is different.

[0079] Secondly, in actual applications, the material of the first sacrificial layer can be the same as that of the third sacrificial layer. In this case, after the mask structure is subsequently removed, the remaining first and third sacrificial layers can be removed simultaneously, thereby improving manufacturing efficiency while reducing the number of materials used in different film layers of the fin structure. This can further alleviate the need for epitaxial materials to consider issues such as stress distribution and stress matching between thin films, thereby reducing manufacturing difficulty. Alternatively, the materials of the first and third sacrificial layers can be different. In this case, it is convenient to release the first and third sacrificial layers separately according to different actual needs, thereby improving the applicability of the manufacturing method provided by the embodiment of the present invention in different application scenarios.

[0080] As for the aforementioned alternating second and third sacrificial layers, the second sacrificial layer will subsequently be removed to release the first dielectric fill region for forming the first central dielectric isolation layer. The alternating second and third sacrificial layers are provided, on the one hand, to form the first central dielectric isolation layer, and on the other hand, to ensure that, when forming the insulating layer used to separate the first source region and the first drain region from the second source region and the second drain region, respectively, the insulating layer has a sufficient thickness to ensure high insulation properties while also reducing the difficulty of filling the first central dielectric isolation layer. This is particularly true when the first central dielectric isolation layer is formed simultaneously with the gate sidewalls (to improve manufacturing efficiency). This prevents the insulating dielectric material used to manufacture the gate sidewalls from being unable to fully fill the thicker first dielectric fill region, thereby reducing manufacturing difficulty and improving the yield of the semiconductor device. Therefore, the thickness of a single second sacrificial layer can refer to the thickness of the gate sidewalls, and the total thickness of the alternating second and third sacrificial layers can refer to the thickness of the insulating layer required in actual application scenarios.

[0081] It should be noted that because the difference in germanium content between the second and third sacrificial layers is less than 15%, the material difference between the second and third sacrificial layers is relatively small, and the corresponding lattice difference between the two is also relatively small. This can alleviate the issues of inter-film stress distribution and stress matching that need to be considered in the prior art due to the large material difference between the second and third sacrificial layers, thereby reducing the critical thickness restrictions of epitaxy. Based on this, the specific thickness of each second and third sacrificial layer can be determined based on the number of alternating second and third sacrificial layers in actual application scenarios and the thickness requirements of the insulating layer, and is not specifically limited here.

[0082] Exemplarily, the thickness of the second sacrificial layer and / or the third sacrificial layer may be greater than or equal to 10 nm and less than or equal to 30 nm. For example, the thickness of the second sacrificial layer and / or the third sacrificial layer may be 10 nm, 12 nm, 15 nm, 18 nm, 20 nm, 25 nm, 28 nm, or 30 nm.

[0083] Furthermore, in embodiments of the present invention, the material of the second sacrificial layer may include silicon or silicon-germanium, and the material of the third sacrificial layer may include silicon-germanium or germanium; alternatively, the material of the second sacrificial layer may include silicon-germanium or germanium, and the material of the third sacrificial layer may include silicon-germanium or germanium. Furthermore, it is understood that the greater the difference in germanium content between the second and third sacrificial layers, the greater the material difference between the two, and the greater the etching selectivity. Furthermore, the type and doping concentration of the etch aid doped in the second sacrificial layer also affect the etching rate of the second sacrificial layer. Specifically, with other factors remaining the same, the greater the concentration of the etch aid doped in the second sacrificial layer, the greater the etching rate of the etch aid on the second sacrificial layer during selective etching of the second sacrificial layer, and the greater the etching selectivity between the second and third sacrificial layers. Therefore, the germanium content in each of the second and third sacrificial layers, the type and doping concentration of the etch aid in the second sacrificial layer, can be determined based on the etching selectivity requirements for the second and third sacrificial layers in actual application scenarios.

[0084] Exemplarily, the second sacrificial layer and the third sacrificial layer may be made of the same material. For example, the second sacrificial layer and the third sacrificial layer may both be made of silicon, silicon germanium, or germanium. Of course, the second sacrificial layer and the third sacrificial layer may also be made of different materials. For example, the difference in germanium content between the second sacrificial layer and the third sacrificial layer may be 1%, 1.5%, 2%, 2.5%, 3%, 3.5%, 4%, 5%, 6%, 7%, 8%, 9%, or 10%, etc.

[0085] Exemplarily, the etching auxiliary agent may be an N-type dopant, such as phosphorus or arsenic.

[0086] For example, the doping concentration of the etching auxiliary agent in the second sacrificial layer may be greater than or equal to 1E18 cm -3 , and less than or equal to 1E19cm -3 For example, the doping concentration of the etching auxiliary agent in the second sacrificial layer can be 1E18cm -3 、2E18cm -3 、3E18cm -3 、4E18cm -3 、5E18cm -3 、6E18cm -3 、8E18cm -3 or 1E19cm -3 In this case, the doping concentration of the etch assist agent in the second sacrificial layer is within the above range, which helps prevent the etch assist agent from having a weaker etch assist effect on the second sacrificial layer due to the low doping concentration, and helps further reduce the material difference between the second sacrificial layer and the third sacrificial layer. Furthermore, it can also prevent the difficulty of doping the etch assist agent in the second sacrificial layer due to the high doping concentration, thereby reducing the difficulty of manufacturing the semiconductor device.

[0087] Furthermore, along the thickness direction of the semiconductor substrate, the alternating first sacrificial layers and channel layers above the alternating second and third sacrificial layers are used to fabricate the upper-layer device of the three-dimensional stacked complementary transistor. Based on this, the number and materials of the alternating first sacrificial layers and channel layers above the alternating second and third sacrificial layers can be determined based on the requirements of the upper-layer device in the actual application scenario, and are not specifically limited here.

[0088] In the actual manufacturing process, Figure 2 As shown, epitaxial growth or other processes can be used to form material layers for manufacturing alternating first sacrificial layers and channel layers, as well as alternating second sacrificial layers and third sacrificial layers along the thickness direction of the semiconductor substrate 11. When forming the second sacrificial layer, an in-situ doping method can be used to dope an etching auxiliary agent into the second sacrificial layer to improve manufacturing efficiency. Alternatively, after forming the second sacrificial layer, the second sacrificial layer can be doped by ion implantation or diffusion. Then, photolithography and etching processes are used to pattern the above-mentioned material layer and part of the semiconductor substrate to form a fin. Next, as shown in FIG. Figure 3 As shown, a shallow trench isolation structure 17 can be formed between adjacent fins using deposition and etching processes to define an active area. The top height of the shallow trench isolation structure 17 is less than or equal to the bottom height of the first sacrificial layer 13 located at the bottom. The portion of the fin exposed outside the shallow trench isolation structure 17 is the fin-shaped structure 12.

[0089] Next, if Figure 4 As shown, a mask structure 18 is formed across the fin structure 12 .

[0090] In actual manufacturing, a deposition process can be used to form a mask material covering the semiconductor substrate. Then, processes such as photolithography and etching are used to selectively etch the mask material to form the aforementioned mask structure. The material of the mask structure can be selected based on actual needs, as long as it can subsequently provide mask protection.

[0091] Exemplarily, the mask structure may include a sacrificial gate. The sacrificial gate may be made of an easily removable material such as polysilicon. Furthermore, the mask structure may also include a gate oxide layer and a sacrificial gate located on the gate oxide layer. The gate oxide layer may be made of a material such as silicon oxide.

[0092] Next, if Figure 5 As shown, at least under the accelerated etching action of the etch assist agent, the second sacrificial layer 15 is selectively removed to form the first dielectric filling region 19. The third sacrificial layer 16 is retained.

[0093] Specifically, the second sacrificial layer can be selectively removed using wet etching or isotropic dry etching. The specific type of etchant and etching conditions used can be determined based on the type and doping concentration of the etching aid, as well as the actual application scenario, and are not specifically limited here.

[0094] For example, when a wet etching process is used to selectively remove the second sacrificial layer, the wet etching solution may include a mixed solution of hydrofluoric acid and hydrogen peroxide.

[0095] Exemplarily, when a dry etching process is used to selectively remove the second sacrificial layer, the etching gas includes a mixed gas of CF 4 , O 2 and He.

[0096] Next, if Figure 6 As shown, a first middle dielectric isolation layer 20 is formed in the first dielectric filling region.

[0097] In the actual manufacturing process, a deposition process or the like can be used to form an insulating dielectric material covering the semiconductor substrate. Then, an etching process can be used to completely remove the portion of the insulating dielectric material outside the first dielectric filling region. In this case, a first middle dielectric isolation layer can be formed based on the insulating dielectric material. Alternatively, the portion of the insulating dielectric material located in the first dielectric filling region and outside the mask structure sidewalls can be completely removed. In this case, a first middle dielectric isolation layer and gate sidewalls can be formed based on the insulating dielectric material. In other words, if Figure 6As shown, while the first middle dielectric isolation layer 20 is formed in the first dielectric filling area 19 , a gate sidewall 28 is formed at least on both sides of the mask structure 18 along the length direction of the fin structure 12 . At this time, the material of the gate sidewall 28 is the same as that of the first middle dielectric isolation layer 20 .

[0098] The material of the first middle dielectric isolation layer may include any insulating dielectric material as long as it can be applied to the manufacturing method provided in the embodiment of the present invention.

[0099] Exemplarily, the material of the first middle dielectric isolation layer includes at least one of SiN, SiCO and SiCON.

[0100] Next, if Figures 7 to 10 As shown, the first sacrificial layer 13 , the channel layer 14 , the first middle dielectric isolation layer 20 and the third sacrificial layer 16 that are not covered by the mask structure 18 are removed.

[0101] In the actual manufacturing process, Figure 6 and Figure 9 As shown, after the first middle dielectric isolation layer 20 is formed, the first sacrificial layer 13, the channel layer 14, the first middle dielectric isolation layer 20 and the third sacrificial layer 16 not covered by the mask structure 18 can be removed together to facilitate the subsequent formation of the first source region, the first drain region, the second source region and the second drain region.

[0102] Alternatively, in the case where the material of the first sacrificial layer is different from the material of the third sacrificial layer, as shown in FIG. Figure 7 As shown, the third sacrificial layer may be selectively removed first to form a third dielectric filling region 31; then, as shown Figure 8 As shown, a second middle dielectric isolation layer 32 is formed in the third dielectric filling region. Figure 10 As shown, the first sacrificial layer 13, the channel layer 14, the first middle dielectric isolation layer 20, and the second middle dielectric isolation layer 32 that are not covered by the mask structure 18 are removed. At this point, when the gate stack structure is subsequently formed, the gate stack structure will not fill the gap between the two adjacent first middle dielectric isolation layers 20, thereby reducing parasitic capacitance and further improving the operating performance of the manufactured semiconductor device.

[0103] The material of the second middle dielectric isolation layer can be the same as or different from that of the first middle dielectric isolation layer. The specific material of the second middle dielectric isolation layer can be set according to actual needs.

[0104] Illustratively, the dielectric constant of the material of the second middle dielectric isolation layer can be smaller than the dielectric constant of the material of the first middle dielectric isolation layer, so as to further reduce the parasitic capacitance between the gate stack structure included in the upper device and the gate stack structure included in the lower device in the three-dimensional stacked complementary transistor, thereby improving the operating performance of the semiconductor device.

[0105] Exemplarily, the material of the second middle dielectric isolation layer may include at least one of SiO 2 , SiN, SiCO, SiCON, and SiO 2 —SiF 4 .

[0106] Of course, when the material of the first sacrificial layer is different from that of the third sacrificial layer, after forming the first middle dielectric isolation layer, the first sacrificial layer, the channel layer, the first middle dielectric isolation layer and the third sacrificial layer not covered by the mask structure can be removed together.

[0107] In addition, after removing the first sacrificial layer, the channel layer, the first middle dielectric isolation layer and the third sacrificial layer that are not covered by the mask structure, before performing subsequent operations, the method for manufacturing the semiconductor device may further include the following steps: Figure 11 and Figure 13 As shown, along the length direction of the fin structure, wet etching or dry etching is used to remove the edge portions of both sides of each remaining first sacrificial layer 13 to form a second dielectric filling region 26. Next, as shown Figures 14 to 16 As shown, deposition and etching processes can be used to form inner sidewalls 27 within the second dielectric filling region. The inner sidewalls 27 can limit the length of the gate stack structure, thereby improving the performance of the semiconductor device. The material of the inner sidewalls 27 can include any insulating material such as silicon nitride, silicon oxynitride, or silicon oxycarbide, as long as they can be applied to the manufacturing method provided in the embodiments of the present invention.

[0108] It should be noted that if Figure 12 and Figure 14 As shown, when the material of the first sacrificial layer 13 is the same as the material of the third sacrificial layer 16 , inner sidewalls 27 are also formed on both sides of the remaining third sacrificial layer 16 .

[0109] Next, if Figure 17 and Figure 18 As shown, a process such as epitaxy can be used to form a first source region 21 and a first drain region 22 on both sides of the remaining first sacrificial layer 13 and the channel layer 14 below the remaining first middle dielectric isolation layer 20. The materials of the first source region 21 and the first drain region 22 can be set according to actual needs and are not specifically limited here.

[0110] Next, if Figure 19 and Figure 20As shown, deposition and etching processes may be used to form an insulating layer 23 on the first source region 21 and the first drain region 22. The thickness and material of the insulating layer 23 may be set according to actual needs.

[0111] Next, if Figure 21 and Figure 22 As shown, a second source region 24 and a second drain region 25 can be formed on the insulating layer 23 and on both sides of the remaining first sacrificial layer 13 and the channel layer 14 located above the remaining first middle dielectric isolation layer 20, using a process such as epitaxy. The conductivity type of the second source region 24 and the second drain region 25 is opposite to the conductivity type of the first source region 21 and the first drain region 22. The materials of the second source region 24 and the second drain region 25 can be set according to actual needs and are not specifically limited here. The materials of the second source region 24 and the second drain region 25 can be the same as or different from the materials of the first source region 21 and the first drain region 22.

[0112] In addition, after forming the second source region and the second drain region, the method for manufacturing the semiconductor device may further include: Figure 23 and Figure 24 As shown, deposition and planarization processes can be used to form an interlayer dielectric layer 29 covering the semiconductor substrate 11. This protects the second source region 24 and the second drain region 25 from etching and cleaning during subsequent operations, thereby improving the yield of the semiconductor device. The top of the interlayer dielectric layer 29 is flush with the top of the mask structure 18. The material of the interlayer dielectric layer 29 may include any dielectric material such as silicon oxide or silicon nitride.

[0113] Next, if Figure 25 and Figure 26 As shown, the mask structure can be removed by dry etching or wet etching. Specifically, the exposed structure can be determined according to the previous operation steps.

[0114] For example: Figure 9 As shown, if the second middle dielectric isolation layer is not formed, the structures exposed by removing the mask structure 18 include the remaining first sacrificial layer 13 and the remaining third sacrificial layer 16. In this case, Figure 27 As shown, dry etching or wet etching can be used to remove the remaining first sacrificial layer 13 and the remaining third sacrificial layer 16. Figure 31As shown, atomic layer deposition and other processes are used to form a gate stack structure 30 that at least surrounds the periphery of the remaining channel layer 14. At this time, if the number of layers of the second sacrificial layer 15 is at least two, the gate stack structure 30 also surrounds the periphery of the remaining first middle dielectric isolation layer 20. The gate stack structure 30 may include a gate dielectric layer and a gate located on the gate dielectric layer. The material of the gate dielectric layer may be an insulating material with a low dielectric constant such as silicon oxide or silicon nitride, or an insulating material with a high dielectric constant such as HfO2, ZrO2, TiO2 or Al2O3. The material of the gate may be a conductive material such as doped polysilicon, TiN, TaN or TiSiN. The thickness of the above-mentioned gate dielectric layer and gate can be set according to actual needs and is not specifically limited here. In addition, the material and / or thickness of the gate stack structure 30 included in the three-dimensional stacked complementary transistor may be the same or different.

[0115] Alternatively, in this case (the second middle dielectric isolation layer is not formed), when the material of the first sacrificial layer is different from the material of the third sacrificial layer, after removing the mask structure and before removing the remaining first sacrificial layer, the manufacturing method of the semiconductor device may include: Figure 28 As shown, the third sacrificial layer is removed to form a third dielectric filling region 31. Next, as shown Figure 29 As shown, a second middle dielectric isolation layer 32 is formed in the third dielectric filling region by using deposition and etching processes. Figure 32 As shown, the gate stack structure 30 only surrounds the periphery of the remaining channel layer 14 to reduce parasitic capacitance. In addition, it can provide another optional solution for reducing parasitic capacitance, improving the applicability of the manufacturing method provided by the embodiment of the present invention in different application scenarios.

[0116] For example: Figure 10 and Figure 26 As shown, if the second middle dielectric isolation layer 32 is formed before forming the first source region 21 and the first drain region 22, the structures exposed to the outside by removing the mask structure 18 include the remaining first sacrificial layer 13 and the remaining second middle dielectric isolation layer 32. At the same time, after removing the mask structure 18, the manufacturing method of the semiconductor device may further include: Figure 30 As shown in FIG, a dry etching or wet etching process is used to remove the remaining first sacrificial layer. Figure 32 As shown, a gate stack structure 30 surrounding the remaining channel layer 14 is formed by using processes such as atomic layer deposition.

[0117] It is worth noting that Figure 10As shown, in the case where the materials of the first sacrificial layer 13 and the third sacrificial layer 16 are different, if the above-mentioned second middle dielectric isolation layer 32 is formed before forming the first source region and the first drain region, then during the source / drain etching process, it is only necessary to etch the alternately stacked first sacrificial layer 13 and the channel layer 14, and to etch the alternately stacked first middle dielectric isolation layer 20 and the second middle dielectric isolation layer 32. Because the first middle dielectric isolation layer 20 and the second middle dielectric isolation layer 32 are both dielectric isolation layers, compared with the difficulty of etching the alternately stacked first middle dielectric isolation layer 20 and the third sacrificial layer 16, etching the alternately stacked first middle dielectric isolation layer 20 and the second middle dielectric isolation layer 32 is less difficult and easier to implement, which helps to reduce the manufacturing difficulty.

[0118] When the above technical solution is adopted, Figures 2 to 32As shown, in the manufacturing method provided by an embodiment of the present invention, the first sacrificial layer 13, the second sacrificial layer 15, and the third sacrificial layer 16 each have different functions. Specifically, the remaining channel layer 14 (the remaining channel layer 14 is used to form the channel region) is subsequently released by selectively removing the portion of the first sacrificial layer 13 corresponding to the gate formation region, thereby facilitating the formation of a gate stack structure 30 surrounding the remaining channel layer 14. Subsequently, the second sacrificial layer 15 is selectively etched to form a first central dielectric isolation layer 20 for isolating the gate stack structure 30 of the upper device from the gate stack structure 30 of the lower device included in the three-dimensional stacked complementary transistor. As for the third sacrificial layer 16, the portion of the third sacrificial layer 16 corresponding to the gate formation region may subsequently form a gate stack structure 30, or may form an insulating dielectric material for isolation. Based on this, the existing manufacturing method completely limits the material types of the first sacrificial layer 13, the second sacrificial layer 15, and the third sacrificial layer 16 to achieve sufficient etching selectivity among the three. In the manufacturing method provided by an embodiment of the present invention, when the material of one of the second sacrificial layer 15 and the third sacrificial layer 16 includes silicon or silicon-germanium, and the material of the other includes silicon-germanium or germanium, the difference in germanium content between the second sacrificial layer 15 and the third sacrificial layer 16 is less than 15%. In this case, the material difference between the second sacrificial layer 15 and the third sacrificial layer 16 is relatively small, and the corresponding lattice difference between the two is also relatively small. When epitaxially manufacturing the materials used for the second sacrificial layer 15 and the third sacrificial layer 16, the problems of stress distribution and stress matching between the films due to the large material difference between the second sacrificial layer 15 and the third sacrificial layer 16 in the prior art can be alleviated. The critical thickness restriction of epitaxial growth is also reduced. There is no need to form more layers of second sacrificial layers 15 and third sacrificial layers 16 with smaller layer thicknesses as in the prior art manufacturing method, or there is no need to form a fixed number of second sacrificial layers 15 and third sacrificial layers 16 due to the critical thickness restriction. As a result, the thickness of the insulating layer 23 used to isolate the first source region 21 and the first drain region 22, and the second source region 24 and the second drain region 25 is also relatively small, thereby preventing leakage.

[0119] And, as Figures 2 to 32As shown, the second sacrificial layer 15 is doped with an etchant. With this arrangement, the second sacrificial layer 15 can be selectively removed at least under the accelerated etching effect of the etchant to form the first dielectric filling region 19 while retaining the third sacrificial layer 16, thereby improving the yield of the semiconductor device. In addition, the manufacturing method provided by the embodiment of the present invention is to perform the formation operation of the first middle dielectric isolation layer 20 in advance before the source and drain etching. At this time, although the aspect ratio of the fin structure 12 may still be large, during the etching process of the insulating dielectric material used to manufacture the first middle dielectric isolation layer 20, even if the insulating dielectric material at the bottom of the gap between adjacent fin structures 12 is not completely removed, it will not affect the formation of the first source region 21 and the first drain region 22 of the subsequent lower-layer device, and will not affect the contact between the first source region 21 and the first drain region 22 of the lower-layer device and the first channel region respectively; and, the insulating dielectric material remaining at the bottom of the gap between adjacent fin structures 12 can further isolate different semiconductor devices formed based on different fin structures 12, reduce the risk of leakage, and increase the yield of the manufactured semiconductor devices while also helping to improve the working performance of the manufactured semiconductor devices.

[0120] While the above description does not provide detailed technical details regarding patterning and etching of each layer, those skilled in the art will appreciate that various technical means can be employed to form layers, regions, and the like in desired shapes. Furthermore, those skilled in the art may devise methods that differ from those described above to form the same structure. Furthermore, while each embodiment has been described separately, this does not mean that the measures in each embodiment cannot be advantageously combined.

[0121] The above describes the embodiments of the present invention. However, these embodiments are merely for illustrative purposes and are not intended to limit the scope of the present invention. The scope of the present invention is defined by the appended claims and their equivalents. Various substitutions and modifications may be made by those skilled in the art without departing from the scope of the present invention, and such substitutions and modifications are intended to fall within the scope of the present invention.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: include: forming a fin structure on a semiconductor substrate; Along the thickness direction of the semiconductor substrate, the fin structure includes an alternately stacked first sacrificial layer and a channel layer, and an alternately stacked second sacrificial layer and a third sacrificial layer; the alternately stacked first sacrificial layer and the channel layer are located on both sides of the alternately stacked second sacrificial layer and the third sacrificial layer in the thickness direction; the film layers located at the bottom and top of the alternately stacked first sacrificial layer and the channel layer are both the first sacrificial layer; the film layers located at the bottom and top of the alternately stacked second sacrificial layer and the third sacrificial layer are both the second sacrificial layer; the material of one of the second sacrificial layer and the third sacrificial layer includes silicon or silicon germanium, and the material of the other includes silicon germanium or germanium; the difference in germanium content between the second sacrificial layer and the third sacrificial layer is less than 15%, and the second sacrificial layer is doped with an etching auxiliary agent; forming a mask structure spanning over the fin structure; At least under the accelerated etching action of the etching auxiliary agent, selectively remove the second sacrificial layer to form a first dielectric filling region; retaining the third sacrificial layer; forming a first middle dielectric isolation layer in the first dielectric filling area; removing the first sacrificial layer, the channel layer, the first middle dielectric isolation layer, and the third sacrificial layer that are not covered by the mask structure; forming a first source region and a first drain region on both sides of the remaining first sacrificial layer and the channel layer below the remaining first middle dielectric isolation layer; forming an insulating layer on the first source region and the first drain region; A second source region and a second drain region are respectively formed on the insulating layer and on both sides of the remaining first sacrificial layer and the channel layer located above the remaining first middle dielectric isolation layer; the conductivity type of the second source region and the second drain region is opposite to the conductivity type of the first source region and the first drain region.

2. The method for manufacturing a semiconductor device according to claim 1, wherein: The etching auxiliary agent is an N-type dopant; and / or, selectively removing the second sacrificial layer by using a wet etching process or an isotropic dry etching process; And / or, the doping concentration of the etching auxiliary agent in the second sacrificial layer is greater than or equal to 1E18cm -3 , and less than or equal to 1E19cm -3 .

3. The method for manufacturing a semiconductor device according to claim 1 , wherein when a wet etching process is used to selectively remove the second sacrificial layer, the wet etching solution comprises a mixed solution of hydrofluoric acid and hydrogen peroxide; Alternatively, when a dry etching process is adopted to selectively remove the second sacrificial layer, the etching gas includes a mixed gas of CF 4 , O 2 and He.

4. The method for manufacturing a semiconductor device according to claim 1, wherein: The thickness of the second sacrificial layer and / or the third sacrificial layer is greater than or equal to 10 nm and less than or equal to 30 nm; and / or, The etching auxiliary agent is doped into the second sacrificial layer by an in-situ doping method.

5. The method for manufacturing a semiconductor device according to claim 1, wherein: The second sacrificial layer and the third sacrificial layer are made of the same material; And / or, the material of the first sacrificial layer is the same as the material of the third sacrificial layer.

6. The method for manufacturing a semiconductor device according to claim 1, wherein: After removing the first sacrificial layer, the channel layer, the first middle dielectric isolation layer, and the third sacrificial layer that are not covered by the mask structure, and before forming the first source region and the first drain region on both sides of the remaining first sacrificial layer and the channel layer below the remaining first middle dielectric isolation layer, respectively, the method for manufacturing the semiconductor device further includes: removing edge portions on both sides of each remaining first sacrificial layer along the length direction of the fin structure to form a second dielectric filling area; An inner sidewall is formed in the second dielectric-filled region.

7. The method for manufacturing a semiconductor device according to claim 1, wherein: The mask structure includes a sacrificial gate; And or, while forming the first middle dielectric isolation layer in the dielectric filling region, gate sidewalls are formed at least on both sides of the mask structure along the length direction of the fin structure.

8. The method for manufacturing a semiconductor device according to claim 1, wherein: The material of the first middle dielectric isolation layer includes at least one of SiN, SiCO and SiCON.

9. The method for manufacturing a semiconductor device according to claim 1, wherein: After forming the second source region and the second drain region, the method for manufacturing the semiconductor device further includes: forming an interlayer dielectric layer covering the semiconductor substrate; removing the mask structure; removing the remaining first sacrificial layer and removing the remaining third sacrificial layer; A gate stack structure is formed at least surrounding the remaining periphery of the channel layer.

10. The method for manufacturing a semiconductor device according to claim 9, wherein: In the case where the material of the first sacrificial layer is different from the material of the third sacrificial layer, After removing the mask structure and before removing the remaining first sacrificial layer, the method for manufacturing the semiconductor device includes: removing the third sacrificial layer to form a third dielectric filling region; A second middle dielectric isolation layer is formed in the third dielectric filling region.

11. The method for manufacturing a semiconductor device according to claim 1, wherein: In the case where the material of the first sacrificial layer is different from the material of the third sacrificial layer, After forming the first middle dielectric isolation layer in the first dielectric filling region, and before forming the first source region and the first drain region on both sides of the remaining first sacrificial layer and the channel layer below the remaining first middle dielectric isolation layer, the method for manufacturing the semiconductor device includes: selectively removing the third sacrificial layer to form a third dielectric filling region; forming a second middle dielectric isolation layer in the third dielectric filling region; and removing the first sacrificial layer, the channel layer, the first middle dielectric isolation layer, and the second middle dielectric isolation layer that are not covered by the mask structure; After forming the second source region and the second drain region, the manufacturing method of the semiconductor device also includes: forming an interlayer dielectric layer covering the semiconductor substrate; removing the mask structure; removing the remaining first sacrificial layer; and forming a gate stack structure surrounding the remaining periphery of the channel layer.

12. The method for manufacturing a semiconductor device according to claim 10 or 11, wherein: The material of the second middle dielectric isolation layer is the same as the material of the first middle dielectric isolation layer; or the dielectric constant of the material of the second middle dielectric isolation layer is smaller than the dielectric constant of the material of the first middle dielectric isolation layer; And / or, the material of the first middle dielectric isolation layer includes: at least one of SiO2, SiN, SiCO, SiCON and SiO2-SiF4.

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