DMA engine device in PCIE to RapidIO circuit and data transmission method

Abstract

The invention provides a DMA (direct memory access) engine device and a data transmission method in a PCIE (peripheral component interface express)-to-RapidIO circuit, a DMA engine comprises a sending engine and a receiving engine which are used for processing data processing and protocol conversion of data packets sent and received in a DMA transmission process; the cache FIFO is used for caching the data read by the DMA engine; and the DMA channel control module and the state control register are used for controlling the DMA engine to update the operation state. A descriptor is configured in a PCIe memory through a host to define detailed parameters of DMA operation; the DMA engine can support DMA data transmission and protocol conversion between the PCIe core and the RapidIO core, and high-speed and low-delay data transmission in the PCIe-to-RapidIO circuit is achieved.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuits, and in particular to a DMA engine device and a data transmission method in a PCIE to RapidIO circuit. Background Art

[0002] With the rapid development of modern computing and embedded system data transmission, the demand for high-speed, low-latency data communication is growing. PCIe, as a widely used high-speed, serial communication protocol, has very high versatility and support, and occupies a core position in personal computers and server systems, providing an efficient connection method for various devices. The RapidIO protocol is favored in some high-performance computing clusters and embedded systems due to its low latency, high bandwidth and high reliability. The PCIe to RapidIO bridge circuit is the key bridge connecting these two different high-speed bus technologies, breaking the bottleneck of data communication. The system can make full use of the respective advantages of PCIe and RapidIO to achieve efficient data transmission across platforms and protocols, which is crucial for building a highly integrated, flexible and changeable system architecture. This bridge circuit can not only realize the conversion between protocols, but also ensure that data can flow efficiently between the two buses, providing efficient and reliable data communication solutions for various application scenarios.

[0003] In the current PCIe to RapidIO bridge circuit, data transmission methods mostly rely on the intervention of the CPU. This not only increases the complexity and power consumption of the system, but also limits the efficiency and response speed of data transmission. As the central processing unit, the CPU needs to continuously process and schedule during the data transmission process, which will introduce additional delays and resource consumption, limiting the maximum throughput that the system can achieve. In addition, while the CPU is processing data transmission, it may affect the execution of other key tasks, reducing the overall performance and response speed of the system.

[0004] Therefore, how to effectively realize high-speed and large-scale data transmission between the PCIe core and the RapidIO core has become a problem that needs to be solved urgently. Summary of the invention

[0005] The present application provides a DMA engine device and a data transmission method in a PCIE to RapidIO circuit, which can be used to meet the problem of high-speed and large-scale data transmission between a PCIe core and a RapidIO core.

[0006] The present application provides a DMA engine device in a PCIE to RapidIO circuit, the engine device comprising:

[0007] The sending engine is used to package the data into PCIe TLP packets or RapidIO packets and send them out;

[0008] The receiving engine is used to unpack the received data packets and transfer the data into FIFO or registers;

[0009] Prefetch descriptor cache FIFO, used to cache the descriptor information prefetched by the DMA engine from the PCIe memory;

[0010] Data cache FIFO, used to cache data read by the DMA engine from the PCIe side or RapidIO side;

[0011] DMA channel status control register and DMA channel control module: used to control the DMA channel to enable, initialize, interrupt, pause, and terminate operations;

[0012] A host for cooperation is arranged outside the engine device.

[0013] The present application also provides a DMA data transmission method in a PCIE to RapidIO circuit, which is implemented by a DMA engine device in the PCIE to RapidIO circuit provided by the present application, and includes:

[0014] Step 1: The host configures the DMA transfer operation by writing a 32-byte descriptor including the DMA transfer type, source address, destination address, and interrupt enable to the main memory on the PCIe side, and updates the base address and quantity of the descriptor to the register on the PCIe side;

[0015] Step 2, the DMA channel control module in the DMA engine device polls and reads the PCIe side register. When the number of descriptors stored in the PCIe side main memory is read to be greater than 0, the receiving engine starts to read the descriptors from the corresponding address of the PCIe side main memory and caches them into the pre-fetch descriptor cache FIFO of the DMA engine device. The descriptor information stored in the pre-fetch descriptor cache FIFO can be read by the DMA channel control module in the DMA engine.

[0016] Step 3, the DMA channel control module parses the cached descriptor content, configures the interrupt enable information after the DMA transmission is completed into the DMA channel status control register, and writes 1 to the initialization bit of the DMA channel status control register to initialize the DMA transmission channel;

[0017] Step 4, each component in the DMA engine starts to start the DMA transmission task between the PCIe domain and the RapidIO domain according to the information and status of the descriptor and register;

[0018] Step 5, after the DMA data transmission configured by a descriptor is completed, the status bit of the DMA channel status control register is updated to the DONE (completed) state; if there are still uninterpreted descriptors in the prefetch descriptor cache FIFO at this time, return to execute step 3 and perform a new round of parsing and transmission; if all written descriptors have been processed, the DMA engine device returns to the idle state.

[0019] Further, in step 4, each component in the DMA engine starts to start the DMA transmission task between the PCIe domain and the RapidIO domain according to the information and status of the descriptor and the register; including:

[0020] Step 41, determining whether the current DMA transfer type is write or read: the DMA channel control module reads the current transfer type from the descriptor, and if the current transfer type is RapidIO NWRITE / SWRITE / NWRITE_R / maintenance write, that is, data is transferred from the PCIe domain main memory to the RapidIO domain by DMA, then the current DMA transfer is WDMA write, and the WDMA operation is started;

[0021] If the transmission type is RapidIO NREAD / maintenance read transmission, that is, data is transmitted from the RapidIO domain memory to the PCIe main memory domain by DMA, then this DMA transmission is read RDMA, and the RDMA operation is started.

[0022] Step 42, start DMA transfer:

[0023] If the DMA channel control module reads the current transmission type as RapidIO NWRITE / SWRITE / NWRITE_R / maintenance write from the descriptor and determines that the current DMA transmission type is WDMA, the sending engine inside the DMA engine initiates an MRd data read request to the PCIe core, and the receiving engine obtains the data at the specified address of the PCIe domain main memory, stores it in the data cache FIFO, and then packages the data in the FIFO, and writes the data to the specified memory location of the RapidIO domain through the sending engine according to the corresponding transmission type (RapidIO NWRITE / SWRITE / NWRITE_R / maintenance write);

[0024] If the DMA engine module reads from the descriptor that the current transmission type is RapidIO NREAD / maintenance read transmission and determines that the current DMA transmission type is RDMA, the sending engine of the DMA engine will initiate a corresponding type of read data request to the RapidIO core, and the receiving engine will obtain the data in the RapidIO domain memory and store it in the data cache FIFO. The sending engine will then package the returned data and write it to the specified location of the PCIe memory through MWr, thereby realizing the data DMA transmission function between the PCIe domain and the RapidIO domain;

[0025] Step 43, the transfer is completed, and it is determined whether to trigger an interrupt after the transfer is completed according to the configuration: after the DMA transfer process is completed, the DMA engine writes a processing end signal to the PCIe side to update the processing status of the descriptor in the PCIe side register; if the descriptor contains an interrupt enable bit, then after the current DMA transfer process is completed, the DMA engine writes 1 to the interrupt bit in the DMA channel status control register to trigger an interrupt, and the host writes 1 to the corresponding bit and clears the interrupt status.

[0026] Furthermore, the method further includes: step 6, DMA exception handling:

[0027] The host controls the pause, resume and stop of the DMA engine during the transmission process by writing and reading the DMA channel status control register in the DMA engine;

[0028] When the pause bit in the DMA channel status control register is written as 1, the DMA engine stops prefetching descriptors, and after processing all prefetched descriptors, the DMA engine will be suspended until the pause bit is reset to 0 and the DMA engine resumes normal operation; when the stop bit in the DMA channel status control register is written as 1, the DMA engine stops prefetching descriptors, sets the ERROR bit in the register, and discards all unfinished PCIe and RapidIO packet requests, completion signals, and response signals, and the DMA engine stops working;

[0029] The host needs to reinitialize the DMA engine to resume the DMA engine from the stopped state.

[0030] Furthermore, the DMA channel status control register is as follows:

[0031] Table 1: DMA channel status control register table

[0032]

[0033] Among them, bit [0] is the initialization and DMA channel enable bit;

[0034] [1] bit is interrupt enable;

[0035] [2] bit is DMA transfer paused when the host writes;

[0036] [3] bit is written by the host when DMA transfer is terminated;

[0037] [11:8] is the interrupt status bit. When an interrupt is triggered, the corresponding status bit will be set to 1 according to the triggering reason. The reasons for triggering the interrupt include:

[0038] [8] bit: A DMA transfer described by the descriptor is completed;

[0039] [9] bit: DMA transfer error occurs, the error cause is obtained by reading [20:16] bits;

[0040]

[10] bit: DMA transfer is suspended by the host;

[0041]

[11] bit: the buffer FIFO in the DMA engine is full;

[0042] [20:16] bits: When the [9] bit ERROR bit is set to 1, the error cause of the DMA channel is displayed, including PCIe and RapidIO response timeouts;

[0043]

[21] Bit: Set to 1 to indicate that the DMA engine is operating normally.

[0044] Further, the descriptor is shown in the following table:

[0045] Table 2: Descriptor table

[0046]

[0047] The descriptor is 32 bytes, which contains the PCIe address of the DMA data transfer, the RapidIO address, the number of bytes of data to be transferred, the type of transfer transaction, the interrupt enable upon completion, and the address pointer of the next descriptor;

[0048] The transaction types in the descriptor include NREAD, NWRITE, NWRITE_R, SWRITE, maintenance read, and maintenance write

[0049] The present invention provides a DMA engine device in a PCIe to RapidIO circuit, which can directly access the system memory in the application of the PCIe to RapidIO circuit, avoid frequent CPU calls, bypass the CPU to reduce data transmission delay, and improve the throughput and efficiency of data transmission. The DMA engine device can release system resources, reduce energy consumption, and improve system stability and reliability, and realize low-latency, high-throughput data transmission. It is particularly suitable for high-speed communication systems that require real-time performance and large data volume transmission, and provides important support for the performance improvement of the entire circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] Figure 1 A schematic diagram of the DMA engine design structure in the PCIe to RapidIO circuit provided in an embodiment of the present application;

[0051] Figure 2 A schematic diagram of the overall workflow of the DMA engine provided in the embodiment of the present application;

[0052] Figure 3 A flowchart of the WDMA implementation of the DMA engine provided in the embodiment of the present application;

[0053] Figure 4 This is a flowchart of the DMA engine RDMA related implementation provided in the embodiment of the present application. DETAILED DESCRIPTION

[0054] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below in conjunction with the accompanying drawings.

[0055] A DMA engine is a hardware module that can directly read and write system memory and perform data transmission. In a PCIe to RapidIO circuit, the use of a DMA engine can directly control the data transmission process without CPU intervention, eliminating the CPU scheduling delay problem, making data movement faster, and making full use of the high bandwidth potential of PCIe and RapidIO, thereby greatly reducing the delay in data transmission and providing a more stable and reliable data communication solution for applications. Therefore, in order to further achieve the goal of low data latency and high throughput, this application provides a DMA engine in a PCIe to RapidIO circuit based on this.

[0056] like Figure 1 , Figure 2 As shown, the present invention provides a DMA engine design method in a PCIe to RapidIO circuit, the PCIe to RapidIO circuit mainly includes: a PCIe core, a RapidIO core and a DMA engine module; the DMA engine module is used to process DMA data transmission between a PCIe domain and a RapidIO domain in the PCIe to RapidIO circuit. The DMA engine module mainly includes:

[0057] The sending engine is used to package the data into PCIe TLP packets or RapidIO packets and send them out;

[0058] The receiving engine is used to unpack the received data packets and transfer the information into FIFO or registers;

[0059] Prefetch descriptor cache FIFO: used to cache the descriptor information prefetched by the DMA engine from the PCIe memory;

[0060] Data cache FIFO: used to cache data read by the DMA engine from the PCIe side or RapidIO side;

[0061] DMA channel status control register and DMA channel control module: used to control the DMA channel to enable, initialize, interrupt, pause, resume, stop and other operations.

[0062] Table 1: DMA channel status control register format

[0063]

[0064] Among them, bit [0] is the initialization and DMA channel enable bit;

[0065] [1] bit is interrupt enable;

[0066] [2] bit is DMA transfer paused when the host writes;

[0067] [3] bit is written by the host when DMA transfer is terminated;

[0068] [11:8] is the interrupt status bit. When an interrupt is triggered, the corresponding status bit will be set to 1 according to the triggering reason. The reasons for triggering the interrupt include:

[0069] [8] bit: A DMA transfer described by the descriptor is completed;

[0070] [9] bit: DMA transfer error (the specific cause of the error can be obtained by reading bits [20:16]);

[0071]

[10] bit: DMA transfer is suspended by the host;

[0072]

[11] bit: the buffer FIFO in the DMA engine is full;

[0073] [20:16] bits: When the [9] bit ERROR bit is set to 1, the error cause of the DMA channel is displayed (including errors such as PCIe and RapidIO response timeout);

[0074]

[21] Bit: Set to 1 to indicate that the DMA engine is operating normally.

[0075] The present application also provides a DMA data transmission method in a PCIE to RapidIO circuit. The method is implemented by the device provided by the present application. The method provided by the present application is described in detail below.

[0076] The host controls the operation of DMA data transfer by configuring descriptors and descriptor status registers in the PCIe side memory; the descriptor is 32 bytes, which contains the PCIe address of DMA data transfer, RapidIO address, number of transferred data bytes, transfer transaction type, interrupt enable upon completion, and address pointer of the next descriptor, as shown in Table 1. The transaction types in the descriptor include NREAD, NWRITE, NWRITE_R, SWRITE, maintenance read, and maintenance write.

[0077] Table 2: Descriptor format

[0078]

[0079] When the host configures the descriptor in the PCIe memory, the descriptor status register notifies the DMA channel control module in the DMA engine that there is an unprocessed descriptor write and transmits the base address information of the descriptor. The DMA channel control module initializes and enables the channel through the DMA channel status control register, and DMA transmission begins.

[0080] First, the sending engine sends a PCIe MRd request to the base address of the descriptor, and the DMA engine starts to prefetch the descriptors stored in the memory in advance; if the number of descriptors does not exceed the maximum depth of the FIFO in the DMA engine, the DMA engine will prefetch all the descriptors and store them in the FIFO; if the number of descriptors in the memory exceeds the maximum storage number of the FIFO, the DMA engine will prefetch the descriptors until the FIFO status is full. The DMA channel control module analyzes the information in the descriptor. If the interrupt enable bit read from the descriptor is 1, the DMA channel control module will pull up the interrupt enable in the DMA channel status control register, and after the descriptor processing is completed, the interrupt bit of the DMA channel status control register will be set to 1 to trigger an interrupt, which can be cleared by the host writing 1 to the bit; if the current transmission type read from the descriptor is RapidIO NWRITE / SWRITE / NWRITE_R / maintenance write type, the current DMA transmission is WDMA, and the WDMA operation is started; if the current transmission type read from the descriptor is RapidIO NREAD / maintenance read transmission, the current DMA transmission is RDMA, and the RDMA operation is started.

[0081] like Figure 3As shown in the figure, when in WDMA operation, the DMA engine works as follows: the sending engine initiates an MRd read data request to the PCIe core according to the PCIe memory address in the descriptor, the receiving engine receives the CplD packet replied by the PCIe core, writes the read data into the data cache FIFO, and then the sending engine packages the data into RapidIO packets and writes them to the RapidIO core according to the RapidIO address and transmission type (NWRITE / SWRITE / NWRITE_R / maintenance write) in the descriptor. When all RapidIO responses have been received, this WDMA operation is considered to be over, the channel control module updates the status bit of the DMA channel status control register, the sending engine writes the update status to the descriptor status register of the PCIe core, and attempts to analyze the next descriptor.

[0082] like Figure 4 As shown in the figure, when in RDMA operation, the DMA engine works as follows: the sending engine initiates a data read request to the RapidIO core according to the RapidIO memory address and transmission type (NREAD / maintenance read) in the descriptor, the receiving engine receives the data packet replied by the RapidIO core, writes the read data into the data cache FIFO, and then initiates MWr to write data to the address specified by the PCIe core. After this RDMA operation is completed, the channel control module updates the status bit of the DMA channel status control register, and the sending engine writes the update status to the descriptor status register of the PCIe core and attempts to analyze the next descriptor.

[0083] In addition, the steps provided in the present application also include exception handling: the host can also control the pause, resume and stop of the DMA engine during the transmission process by writing and reading the DMA channel status control register in the DMA engine. When the [2] bit in the DMA channel status control register, i.e. the pause bit, is written as 1, the DMA engine stops prefetching descriptors, and after processing all prefetched descriptors in the cache FIFO, the DMA engine will be paused; after the DMA transmission is paused, the software will poll the pause bit in the DMA channel status control register until the pause bit is rewritten as 0, and the normal operation of the DMA engine is restored. When the [3] bit in the DMA channel status control register, i.e. the stop bit, is written as 1, the DMA engine stops prefetching descriptors, sets the ERROR position in the register to 1, and discards all currently unfinished PCIe and RapidIO packet requests, completion signals and response signals, and the DMA engine stops working; once the DMA engine is stopped, the host needs to reinitialize the DMA engine to restore it from the stopped state.

[0084] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes and modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

[0085] The above-described embodiments of the present application do not constitute a limitation on the protection scope of the present application.

Claims

1. A DMA engine device in a PCIE to RapidIO circuit, characterized in that: The engine device comprises: The sending engine is used to package the data into PCIe TLP packets or RapidIO packets and send them out; The receiving engine is used to unpack the received data packets and transfer the data into FIFO or registers; Prefetch descriptor cache FIFO, used to cache the descriptor information prefetched by the DMA engine from the PCIe memory; Data cache FIFO, used to cache data read by the DMA engine from the PCIe side or RapidIO side; DMA channel status control register and DMA channel control module: used to control the DMA channel to enable, initialize, interrupt, pause, and terminate operations; A host for cooperation is arranged outside the engine device.

2. A DMA data transmission method in a PCIE to RapidIO circuit, the method being implemented by the DMA engine device in the PCIE to RapidIO circuit according to claim 1, characterized in that: The method comprises: Step 1: The host configures the DMA transfer operation by writing a 32-byte descriptor including the DMA transfer type, source address, destination address, and interrupt enable to the main memory on the PCIe side, and updates the base address and quantity of the descriptor to the register on the PCIe side; Step 2, the DMA channel control module in the DMA engine device polls and reads the PCIe side register. When the number of descriptors stored in the PCIe side main memory is read to be greater than 0, the receiving engine starts to read the descriptors from the corresponding address of the PCIe side main memory and caches them into the pre-fetch descriptor cache FIFO of the DMA engine device. The descriptor information stored in the pre-fetch descriptor cache FIFO can be read by the DMA channel control module in the DMA engine. Step 3, the DMA channel control module parses the cached descriptor content, configures the interrupt enable information after the DMA transmission is completed into the DMA channel status control register, and writes 1 to the initialization bit of the DMA channel status control register to initialize the DMA transmission channel; Step 4, each component in the DMA engine starts to start the DMA transmission task between the PCIe domain and the RapidIO domain according to the information and status of the descriptor and register; Step 5, after the DMA data transmission configured by a descriptor is completed, the status bit of the DMA channel status control register is updated to the completed DONE state; if there are still uninterpreted descriptors in the prefetch descriptor cache FIFO at this time, return to execute step 3 and perform a new round of parsing and transmission; if all written descriptors have been processed, the DMA engine device returns to the idle state.

3. The DMA data transmission method in a PCIe to RapidIO circuit according to claim 2, characterized in that: Step 4, each component in the DMA engine starts to start the DMA transmission task between the PCIe domain and the RapidIO domain according to the information and status of the descriptor and register; including: Step 41, determining whether the current DMA transfer type is write or read: the DMA channel control module reads the current transfer type from the descriptor, and if the current transfer type is RapidIO NWRITE / SWRITE / NWRITE_R / maintenance write, that is, data is transferred from the PCIe domain main memory to the RapidIO domain by DMA, then the current DMA transfer is WDMA write, and the WDMA operation is started; If the data transmission type is RapidIO NREAD / maintenance read transmission, that is, data is transmitted from the RapidIO domain memory to the PCIe main memory domain by DMA, then this DMA transmission is read RDMA, and the RDMA operation is started; Step 42, start DMA transfer: If the DMA channel control module reads the current transmission type as RapidIO NWRITE / SWRITE / NWRITE_R / maintenance write from the descriptor and determines that the current DMA transmission type is WDMA, the sending engine inside the DMA engine initiates an MRd data read request to the PCIe core, and the receiving engine obtains the data at the specified address of the PCIe domain main memory, stores it in the data cache FIFO, and then packages the data in the FIFO, and writes the data to the specified memory location of the RapidIO domain through the sending engine according to the corresponding transmission type; If the DMA engine module reads from the descriptor that the current transmission type is RapidIO NREAD / maintenance read transmission and determines that the current DMA transmission type is RDMA, the sending engine of the DMA engine will initiate a corresponding type of read data request to the RapidIO core, and the receiving engine will obtain the data in the RapidIO domain memory and store it in the data cache FIFO. The sending engine will then package the returned data and write it to the specified location of the PCIe memory through MWr, thereby realizing the data DMA transmission function between the PCIe domain and the RapidIO domain; Step 43, the transfer is completed, and it is determined whether to trigger an interrupt after the transfer is completed according to the configuration: after the DMA transfer process is completed, the DMA engine writes a processing end signal to the PCIe side to update the processing status of the descriptor in the PCIe side register; if the descriptor contains an interrupt enable bit, then after the current DMA transfer process is completed, the DMA engine writes 1 to the interrupt bit in the DMA channel status control register to trigger an interrupt, and the host writes 1 to the corresponding bit and clears the interrupt status.

4. The DMA data transmission method in a PCIe to RapidIO bridge system according to claim 2, characterized in that: The method further includes: step 6, DMA exception handling: The host controls the pause, resume and stop of the DMA engine during the transmission process by writing and reading the DMA channel status control register in the DMA engine; When the pause bit in the DMA channel status control register is written as 1, the DMA engine stops prefetching descriptors, and after processing all prefetched descriptors, the DMA engine will be suspended until the pause bit is reset to 0 and the DMA engine resumes normal operation; when the stop bit in the DMA channel status control register is written as 1, the DMA engine stops prefetching descriptors, sets the ERROR bit in the register, and discards all unfinished PCIe and RapidIO packet requests, completion signals, and response signals, and the DMA engine stops working; The host needs to reinitialize the DMA engine to resume the DMA engine from the stopped state.

5. The DMA data transmission method in a PCIe to RapidIO bridge system according to claim 2, characterized in that: The DMA channel status control register is as follows: Table 1: DMA channel status control register table Among them, bit [0] is the initialization and DMA channel enable bit; [1] bit is interrupt enable; [2] bit is DMA transfer paused when the host writes; [3] bit is written by the host when DMA transfer is terminated; [11:8] is the interrupt status bit. When an interrupt is triggered, the corresponding status bit will be set to 1 according to the triggering reason. The reasons for triggering the interrupt include: [8] bit: A DMA transfer described by the descriptor is completed; [9] bit: DMA transfer error occurs, the error cause is obtained by reading [20:16] bits; [10] bit: DMA transfer is suspended by the host; [11] bit: the buffer FIFO in the DMA engine is full; [20:16] bits: When the [9] bit ERROR bit is set to 1, the error cause of the DMA channel is displayed, including PCIe and RapidIO response timeouts; [21] Bit: Set to 1 to indicate that the DMA engine is operating normally.

6. The DMA data transmission method in a PCIe to RapidIO bridge system according to claim 2, characterized in that: The descriptors are shown in the following table: Table 2: Descriptor table The descriptor is 32 bytes, which contains the PCIe address of the DMA data transfer, the RapidIO address, the number of bytes of data to be transferred, the type of transfer transaction, the interrupt enable upon completion, and the address pointer of the next descriptor; The transaction types in the descriptor include NREAD, NWRITE, NWRITE_R, SWRITE, maintenance read, and maintenance write.

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