Memory management method and device, computer equipment and storage medium

Abstract

The invention relates to the technical field of memory management, and discloses a memory management method and device, computer equipment and a storage medium, and the method comprises the steps: generating a state information matrix according to the use state of each atomic memory block in physical memory information; each element in the state information matrix is used for indicating whether each atomic memory block is used or not, generating an index table array based on the state information matrix, determining a target memory block corresponding to the memory application request based on the index table array, and updating the state information matrix and the index table array based on the target memory block. According to the method and the device, the memory management operation is restrained in a smaller local range through the state information matrix and the index table array, and the whole memory information linked list does not need to be traversed, so that the time overhead of memory search is effectively reduced, and the memory management efficiency is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of memory management, and in particular to a memory management method, device, computer equipment and storage medium. Background Art

[0002] The types of computer services are increasing day by day, and the memory sizes required to run various services are also different. As the number of memory application and release operations increases, the memory is increasingly fragmented, resulting in a situation where there is a lot of free memory but a continuous block of memory cannot be allocated.

[0003] At present, the memory buddy algorithm is usually used for memory management to avoid the above-mentioned memory fragmentation as much as possible. The algorithm realizes fine management of memory by dividing all free memory blocks into multiple block lists, each of which contains continuous memory blocks of a specific size. Specifically, when applying for memory, the memory buddy algorithm allocates free pages in the memory block list of the same size as the application and deletes them from the list. If there is no memory block of the same size, the previous level is checked and the unallocated remaining part is added to the next level free list. Memory release is the reverse process of application.

[0004] However, in the above memory management method, during the memory application and release process, the iterative splitting / merging operations of the memory and the traversal of the linked list will generate a lot of time overhead, which not only affects the efficiency and performance of the memory application / release, but also the memory merging operation of the above method has the limitation that the address of the first memory block must be an integer multiple of 2. Summary of the invention

[0005] In view of this, the present invention provides a memory management method, apparatus, computer device and storage medium to solve the problem of low efficiency of the current memory management method based on the buddy algorithm.

[0006] In a first aspect, the present invention provides a memory management method, the method comprising:

[0007] Generate a state information matrix according to the use status of each atomic memory block in the physical memory information; each element in the state information matrix is ​​used to indicate whether each atomic memory block is used;

[0008] Generate an index table array based on the state information matrix; the index table array includes an intra-row index table array and an inter-row index table array; the index table array is used to indicate the usage of memory blocks of different specifications; memory blocks of different specifications are used to indicate continuous unused atomic memory blocks of different lengths in the state information matrix;

[0009] Determine a target memory block corresponding to the memory application request based on the index table array;

[0010] Based on the target memory block, update the state information matrix and index table array.

[0011] The memory management method provided by the embodiment of the present invention forms a state information matrix corresponding to the usage status of each atomic memory block, and generates an index table array based on the information state matrix. The design of the index table array enables rapid finding and allocation of continuous unused memory blocks, reduces memory fragmentation, and thus improves overall memory utilization. That is, through the index table, the system can quickly locate memory blocks of appropriate specifications without traversing the entire memory space, which greatly shortens the time for memory allocation and recovery and improves system performance.

[0012] In an optional implementation, generating an index table array based on the state information matrix includes:

[0013] An intra-row index table array and an inter-row index table array are generated based on the state information matrix; the number of columns of the intra-row index table array and the inter-row index table array are both the number of memory block specifications, the number of rows of the intra-row index table array is equal to the number of rows of the state information matrix, and the number of rows of the inter-row index table array is 1 less than the number of rows of the intra-row index table array.

[0014] The memory management method provided by the embodiment of the present invention can quickly locate memory blocks of appropriate specifications by converting the state information matrix into an index table array, including an intra-row index table array and an inter-row index table array. The index table array not only records the usage of the memory blocks, but also classifies the memory blocks according to their specifications, thereby reducing the time for searching for unused memory blocks in the entire state information matrix. This indexing method speeds up the memory allocation process and improves the response speed and overall performance of the system. At the same time, by simplifying complex memory state information into a structured index table array, the logic of memory management is also made clearer and easier to maintain.

[0015] In an optional implementation, determining a target memory block corresponding to a memory application request based on an index table array includes:

[0016] Based on the memory application request, determining a target area in the state information matrix in the index table array;

[0017] A target memory block of a size corresponding to the memory application request is selected in the target area.

[0018] The memory management method provided by the embodiment of the present invention can quickly locate the area of ​​the state information matrix that may contain continuous unused memory blocks that meet the requested size, that is, the target memory blocks, by setting the intra-row index table array and the cross-row index table array. This fast positioning mechanism avoids aimless or linear searches in the entire physical memory space, thereby significantly improving the efficiency of memory allocation.

[0019] In an optional implementation, based on the memory application request, determining the target area in the state information matrix in the index table array includes:

[0020] If there is an idle memory block with the same size as the memory application request in the index table array, the area in the state information matrix corresponding to the idle memory block is confirmed as the target area;

[0021] If there is no idle memory block with the same size as the memory application request in the index table array, the area in the state information matrix corresponding to the idle memory block larger than the minimum size of the memory application request is confirmed as the target area.

[0022] The memory management method provided by the embodiment of the present invention first checks whether there is a free memory block with the same size as the memory application request in the index table array. If so, the target area is directly determined to allocate the memory block, so that the needs of the memory request can be met to the maximum extent while reducing the generation of memory fragments. If there is no completely matching memory block, a memory block with the smallest specification larger than the requested size is selected to determine the target area. This strategy ensures the effective use of memory and avoids unnecessary memory waste.

[0023] In an optional implementation, selecting a target memory block of a size corresponding to the memory application request in the target area includes:

[0024] Select the target memory block with the smallest address in the target area and the size corresponding to the memory application request.

[0025] The memory management method provided by the embodiment of the present invention selects the memory block with the smallest address for allocation, which helps to maintain the continuity of the memory space. At the same time, selecting the memory block with the smallest address for allocation can simplify the complexity of memory management.

[0026] In an optional embodiment, the method further includes:

[0027] If the memory application request is successful, the business layer will be responded with a memory application success message and the address of the target memory block. Otherwise, the business layer will be responded with a memory application failure message.

[0028] The memory management method provided by the embodiment of the present invention can immediately know the processing result of the memory request by responding to the business layer with the success or failure information of the memory application. If the memory application is successful, the business layer can obtain the address of the target memory block and continue to perform subsequent operations; if the memory application fails, the business layer can take remedial measures in time, such as releasing some memory that is no longer needed, trying a smaller memory request, or notifying the user that the memory resources are insufficient. This instant feedback helps to enhance the stability of the program and the user experience.

[0029] In an optional embodiment, the method further includes:

[0030] In response to the memory release request, the state information matrix and the index table array are updated.

[0031] The memory management method provided by the embodiment of the present invention timely updates the state information matrix and the index table array when the memory blocks are released, which can ensure that the memory blocks are correctly marked as idle and reused in subsequent memory allocation requests. This helps to improve the reuse rate of memory resources and reduce memory waste.

[0032] In an optional embodiment, the method further includes:

[0033] If the memory release request is successful, a memory release success message is sent to the business layer; otherwise, a memory release failure message is sent to the business layer.

[0034] The memory management method provided by the embodiment of the present invention can release related resources more quickly when the business layer receives a response of successful memory release. If the memory release fails, the business layer can take corresponding remedial measures, such as retrying the release operation, recording an error log, or notifying the user, which helps to enhance the stability of the program and the user experience.

[0035] In a second aspect, the present invention provides a memory management device, the device comprising:

[0036] A matrix generation module is used to generate a state information matrix according to the use status of each atomic memory block in the physical memory information; each element in the state information matrix is ​​used to indicate whether each atomic memory block is used;

[0037] An array generation module is used to generate an index table array based on a state information matrix; the index table array includes an intra-row index table array and an inter-row index table array; the index table array is used to indicate the usage of memory blocks of different specifications; memory blocks of different specifications are used to indicate continuous unused atomic memory blocks of different lengths in the state information matrix;

[0038] A determination module, used for determining a target memory block corresponding to a memory application request based on an index table array;

[0039] The update module is used to update the state information matrix and the index table array based on the target memory block.

[0040] In a third aspect, the present invention provides a computer device, comprising: a memory and a processor, the memory and the processor being communicatively connected to each other, the memory storing computer instructions, and the processor executing the memory management method of the first aspect or any corresponding embodiment thereof by executing the computer instructions.

[0041] In a fourth aspect, the present invention provides a computer-readable storage medium having computer instructions stored thereon, the computer instructions being used to enable a computer to execute the memory management method of the first aspect or any corresponding embodiment thereof.

[0042] In a fifth aspect, the present invention provides a computer program product, comprising computer instructions for causing a computer to execute the memory management method of the first aspect or any corresponding embodiment thereof. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0044] Figure 1 is a flowchart of a memory management method according to an embodiment of the present invention;

[0045] Figure 2 is a schematic diagram of a conversion process between a state information matrix and an intra-row index table array according to an embodiment of the present invention;

[0046] Figure 3 is a flowchart of another memory management method according to an embodiment of the present invention;

[0047] Figure 4 is a flowchart of another memory management method according to an embodiment of the present invention;

[0048] Figure 5 is a structural block diagram of a memory management device according to an embodiment of the present invention;

[0049] Figure 6 It is a schematic diagram of the hardware structure of a computer device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0050] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0051] At present, the memory buddy algorithm is usually used to meet various memory size requirements and avoid memory fragmentation as much as possible. This algorithm achieves fine memory management by dividing all free memory blocks into multiple block linked lists, each of which contains continuous memory blocks of a specific size. However, according to the above memory management method, according to the process of memory application and release, the memory iterative split / merge operation and traversal of the linked list will generate a lot of time overhead, which will affect the performance of memory application / release.

[0052] According to an embodiment of the present invention, a memory management method embodiment is provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and although a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0053] In this embodiment, a memory management method is provided. Figure 1 is a flowchart of a memory management method according to an embodiment of the present invention. Figure 1 As shown, the process includes the following steps:

[0054] Step S101, generating a state information matrix according to the usage status of each atomic memory block in the physical memory information.

[0055] Specifically, first, obtain all the information of the current physical memory, including total capacity, available capacity, allocated capacity, etc., then divide the physical memory into multiple atomic memory blocks of equal size. The size of the atomic memory block can be customized in advance, for example, it can be 4KB. These atomic memory blocks are the basic units of memory allocation and recovery.

[0056] Furthermore, the entire memory is divided into several smaller atomic memory blocks. The status information of each atomic memory block is mapped to 1 bit to represent its current status information, so as to create a two-dimensional matrix status information matrix with M rows and N columns. Each element in the status information matrix is ​​used to indicate whether each atomic memory block is used. The atomic memory block has two states: idle and used. Specifically, the idle state refers to the state after the memory block management module is initialized, or the memory block has been released by the business layer, and the used state refers to the state after the memory block has been applied by the business layer and has not been released.

[0057] Optionally, 0 is used to indicate that the usage status of the atomic memory block is "unused", and 1 is used to indicate that the usage status of the atomic memory block is "used".

[0058] Step S102: Generate an index table array based on the state information matrix.

[0059] Specifically, the index table array includes an intra-row index table array and an inter-row index table array. The index table array is used to indicate the distribution of continuous elements of different lengths and the same state in the state information matrix. Memory blocks of different sizes are used to indicate continuous unused atomic memory blocks of different lengths in the state information matrix, where the minimum size is 1 free atomic memory block and the maximum size is K continuous free atomic memory blocks, and K can be customized in advance.

[0060] Furthermore, the higher the memory block specification, the longer the continuous length of the free atomic memory blocks. A free atomic memory block can only belong to one memory block specification.

[0061] In some optional implementations, the above step S102 includes:

[0062] An intra-row index table array and an inter-row index table array are generated based on the state information matrix; the number of columns of the intra-row index table array and the inter-row index table array are both the number of memory block specifications, the number of rows of the intra-row index table array is equal to the number of rows of the state information matrix, and the number of rows of the inter-row index table array is 1 less than the number of rows of the intra-row index table array.

[0063] Specifically, for the in-row index table, the number of rows of the in-row index table array is determined according to the number of rows of the state information matrix, that is, when the information state matrix is ​​M rows and N columns, the in-row index table is also M rows. At the same time, the number of memory block specifications is determined, that is, the number of continuous lengths of unused atomic memory blocks is determined to determine the number of columns of the in-row index table array.

[0064] Furthermore, in order to ensure the continuity of the boundaries between M rows, that is, between two adjacent rows in the state matrix, a cross-row index table is designed as a supplement to the intra-row index table. Its number of rows is one row less than that of the intra-row index table array, so the cross-row index table matrix corresponding to the M-row state information matrix should be M-1 rows, and the number of columns of the cross-row index table is also equal to the number of memory block specifications.

[0065] Furthermore, through the above-mentioned intra-row index table array and cross-row index table array, the entire memory is divided into 2M-1 local memories. Each memory management only needs to select one or two local memories for operation, and the global continuity of the entire memory is guaranteed.

[0066] Step S103: determining a target memory block corresponding to the memory application request based on the index table array.

[0067] Specifically, first, the memory block size required by the request is obtained by parsing the memory application request. Then, according to the memory block size of the application request, the available free state memory block is searched in the column of the corresponding specification, and the first row with available free state memory block is confirmed as a valid row. Since each row of the index table array corresponds to a row in the state information matrix, the specific position of the target memory block can be determined in the information state matrix based on this.

[0068] Furthermore, if no available free-state memory block is found in the row index table array, the search continues for the next row until all columns and rows of the index table array are traversed.

[0069] In some optional implementations, the above step S103 includes:

[0070] Step S1031, based on the memory application request, determining a target area in the state information matrix in the index table array;

[0071] Step S1032: Select a target memory block of a size corresponding to the memory application request in the target area.

[0072] Specifically, according to the memory application request, the intra-row index table array and the cross-row index table array are searched in parallel. If an idle memory block that can satisfy the current memory application is found through the index table array, the precise position of the memory block is detected in the local state information matrix according to the index value obtained in the index table to determine the corresponding target area in the state information matrix. Then, according to the memory application request, a memory block of the required size is selected as the target memory block in the target area in the information state matrix, and the address of the memory block is obtained.

[0073] Step S104: based on the target memory block, update the state information matrix and the index table array.

[0074] Specifically, after the target memory block is determined through step S103, the starting position and length of the target memory block are found in the state information matrix, and the element at the corresponding position is changed from the "free" state (usually represented by 0 or False) to the "used" state (usually represented by 1 or True).

[0075] Further, the intra-row index table array and the inter-row index table array are updated based on the updated state information matrix.

[0076] In summary, the memory management method provided by the embodiment of the present invention, in order to facilitate memory management, divides the entire physical memory into several smaller atomic memory blocks, and maps the state information of each atomic memory block to 1 bit to represent its current state information, and the mapping is aggregated into a state information matrix (bitmap matrix) with M rows and N columns, and the continuous bitmap matrix represents that the physical address in the memory is continuous, and the continuous division is continuous within the row and continuous across the row. If the free atomic memory blocks are continuous within the row, a possible state information matrix is ​​shown in Table 1:

[0077] Table 1: Example of a status information matrix

[0078] 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1

[0079] If the free atomic memory blocks are continuous across rows, a possible state information matrix is ​​shown in Table 2:

[0080] Table 2: Example of status information matrix table

[0081] 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1

[0082] Therefore, corresponding to the two possible distribution situations of continuous free atomic blocks, an in-row index table array and a cross-row index table array are generated respectively, wherein the in-row index table array is as follows: Figure 2 As shown, the memory is divided into M local memories, and the status of each intra-row local memory is represented by an intra-row index table. The cross-row index table array is used as a supplement to the intra-row index table array to ensure the boundary continuity between the M intra-row local memories. Therefore, a group of M-1 rows of cross-row index table arrays are formed to represent the status of these M-1 cross-row local memories. The number of columns of the cross-row index table array is the same as that of the intra-row index table.

[0083] When memory is requested, the intra-row index table array and the cross-row index table array are searched in parallel according to the size of the requested memory block. Specifically, according to the size of the requested memory, the corresponding column in the index table array is searched, and the first valid row in the column of the index table array is selected, and the area of ​​the state information matrix corresponding to the row is used as the target area, and then the target memory block is selected according to the memory application request; if the search fails in a column of the index table array, and the specification of the memory block currently being searched is not the maximum memory specification, the memory specification is upgraded and the search is performed again in the index table until the target memory block is determined according to the above process; if the search fails in a column of the index table array, and the specification of the memory block currently being searched is the maximum memory specification, it indicates that the memory block required by the business layer cannot be allocated at present, and a direct response is given.

[0084] After the target memory block is determined, the state information corresponding to the target memory block in the state information matrix is ​​changed from "free" to "used", and the index table array is updated based on the updated state information matrix.

[0085] In some optional implementations, determining a target area in a state information matrix in an index table array includes:

[0086] If there is an idle memory block with the same size as the memory application request in the index table array, the area in the state information matrix corresponding to the idle memory block is confirmed as the target area;

[0087] If there is no idle memory block with the same size as the memory application request in the index table array, the area in the state information matrix corresponding to the idle memory block larger than the minimum size of the memory application request is confirmed as the target area.

[0088] First, search in parallel in the intra-row index table array and the cross-row index table array for the column where the memory block specification completely matches the memory application request size, find the first valid row in the column of the index table array, and use the row in the information status matrix corresponding to the row of the column as the target area. If optional free memory blocks are found in both the intra-row index table and the cross-row index table, the free memory blocks in the intra-row index table are used first to determine the corresponding row of the status information matrix as the target area.

[0089] If there is no free memory block with the same size as the memory application request, and the memory block specification currently being searched is not the maximum memory specification, the memory specification is upgraded and searched again in the index table. If the memory block specification at this time is already the maximum memory block specification in the index table array, it indicates that the memory block required by the business layer cannot be allocated at present, and the memory application request fails.

[0090] In some optional implementations, selecting a target memory block of a size corresponding to the memory application request in the target area includes:

[0091] Select the target memory block with the smallest address in the target area and the size corresponding to the memory application request.

[0092] When a row in the state information matrix is ​​determined as the target area according to the index table array, if there is more than one optional target memory block corresponding to the memory application request in the row in the state information matrix, as shown in Table 3, assuming that the atomic memory block is 4KB and the memory application request is 12KB, the third row of the state information matrix is ​​located as the target area according to the index table array, but there are two optional target memory blocks in the target area, then the memory block with the smaller memory address is selected as the target memory block.

[0093] Table 3: Example table of target areas

[0094]

[0095]

[0096] In some optional embodiments, the method further comprises:

[0097] If the memory application request is successful, the business layer will be responded with a memory application success message and the address of the target memory block. Otherwise, the business layer will be responded with a memory application failure message.

[0098] Please refer to Figure 3 The memory application process also includes a response to the business layer. If the target memory block is found according to the index table array and the state information matrix, and the state information matrix and the index table array are updated based on the target memory block, the business layer is responded with a memory application success message and the address of the target memory block; if the target memory block corresponding to the memory application request is not found, the business layer is responded with a memory application failure message.

[0099] In some optional embodiments, the method further comprises:

[0100] In response to the memory release request, the state information matrix and the index table array are updated.

[0101] Please refer to Figure 4 After receiving the memory release operation sent by the business layer, the row of the memory block in the status information matrix is ​​obtained according to the address decoding of the released memory, the status information of the corresponding atomic memory block position in the corresponding row of the released atomic memory block in the status information matrix is ​​updated, and the index information in the index table array is updated based on the updated status information matrix.

[0102] In some optional embodiments, the method further comprises:

[0103] If the memory release request is successful, a memory release success message is sent to the business layer; otherwise, a memory release failure message is sent to the business layer.

[0104] In this embodiment, a memory management device is also provided, which is used to implement the above-mentioned embodiments and preferred implementation modes, and the descriptions that have been made will not be repeated. As used below, the term "module" can be a combination of software and / or hardware that implements a predetermined function. Although the devices described in the following embodiments are preferably implemented in software, the implementation of hardware, or a combination of software and hardware, is also possible and conceivable.

[0105] This embodiment provides a memory management device, such as Figure 5 As shown, including:

[0106] A matrix generation module 501 is used to generate a state information matrix according to the use status of each atomic memory block in the physical memory information; each element in the state information matrix is ​​used to indicate whether each atomic memory block is used;

[0107] Generate array module 502, used to generate index table array based on state information matrix; the index table array includes intra-row index table array and inter-row index table array; the index table array is used to indicate the usage of memory blocks of different specifications; memory blocks of different specifications are used to indicate continuous unused atomic memory blocks of different lengths in the state information matrix;

[0108] A determination module 503, configured to determine a target memory block corresponding to the memory application request based on the index table array;

[0109] The updating module 504 is used to update the state information matrix and the index table array based on the target memory block.

[0110] In some optional implementations, the array generation module 502 includes:

[0111] Generate an index table sub-unit, which is used to generate an intra-row index table array and an inter-row index table array based on the state information matrix; the number of columns of the intra-row index table array and the inter-row index table array are both the number of memory block specifications, the number of rows of the intra-row index table array is equal to the number of rows of the state information matrix, and the number of rows of the inter-row index table array is 1 less than the number of rows of the intra-row index table array.

[0112] In some optional implementations, the determining module 503 includes:

[0113] The target region determination submodule is used to determine the target region in the state information matrix in the index table array based on the memory application request.

[0114] The selection submodule is used to select a target memory block of a size corresponding to the memory application request in the target area.

[0115] In some optional implementations, the target region determination submodule includes:

[0116] A first unit for determining a target area is used to identify an area in a state information matrix corresponding to an idle memory block as a target area when an idle memory block having the same size as the memory application request exists in the index table array;

[0117] Determine the second unit of the target area. When there is no idle memory block with the same size as the memory application request in the index table array, the area in the state information matrix corresponding to the idle memory block with a minimum size larger than the memory application request is confirmed as the target area.

[0118] In some optional implementations, selecting a submodule includes:

[0119] The minimum address unit is selected to select a target memory block with the smallest address in the target area and a size corresponding to the memory application request.

[0120] In some optional embodiments, the device further comprises:

[0121] The response module is used to respond to the business layer with memory application success information and the address of the target memory block when the memory application request is successful, and to respond to the business layer with memory application failure information otherwise.

[0122] In some optional embodiments, the device further comprises:

[0123] The release update module is used to update the state information matrix and the index table array in response to the memory release request.

[0124] The further functional description of each of the above modules and units is the same as that of the above corresponding embodiments and will not be repeated here.

[0125] The memory management device in this embodiment is presented in the form of a functional unit, where the unit refers to an ASIC (Application Specific Integrated Circuit) circuit, a processor and memory that executes one or more software or fixed programs, and / or other devices that can provide the above functions.

[0126] The embodiment of the present invention also provides a computer device having the above Figure 5 The memory management device shown.

[0127] See also Figure 6 , Figure 6 is a schematic diagram of the structure of a computer device provided by an optional embodiment of the present invention, such as Figure 6 As shown, the computer device includes: one or more processors 10, a memory 20, and interfaces for connecting various components, including high-speed interfaces and low-speed interfaces. Various components are connected to each other using different buses for communication, and can be installed on a common mainboard or installed in other ways as needed. The processor can process the instructions executed in the computer device, including instructions stored in or on the memory to display the graphical information of the GUI on an external input / output device (such as, a display device coupled to the interface). In some optional embodiments, if necessary, multiple processors and / or multiple buses can be used together with multiple memories and multiple memories. Similarly, multiple computer devices can be connected, and each device provides some necessary operations (for example, as a server array, a group of blade servers, or a multi-processor system). Figure 6A processor 10 is taken as an example.

[0128] The processor 10 may be a central processing unit, a network processor or a combination thereof. The processor 10 may further include a hardware chip. The hardware chip may be a dedicated integrated circuit, a programmable logic device or a combination thereof. The programmable logic device may be a complex programmable logic device, a field programmable gate array, a general purpose array logic or any combination thereof.

[0129] The memory 20 stores instructions executable by at least one processor 10, so that the at least one processor 10 executes the method shown in the above embodiment.

[0130] The memory 20 may include a program storage area and a data storage area, wherein the program storage area may store an operating system, an application required for at least one function; the data storage area may store data created according to the use of the computer device, etc. In addition, the memory 20 may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some optional embodiments, the memory 20 may optionally include a memory remotely arranged relative to the processor 10, and these remote memories may be connected to the computer device via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0131] The memory 20 may include a volatile memory, such as a random access memory; the memory may also include a non-volatile memory, such as a flash memory, a hard disk or a solid state drive; the memory 20 may also include a combination of the above types of memory.

[0132] The computer device also includes an input device 30 and an output device 40. The processor 10, the memory 20, the input device 30 and the output device 40 may be connected via a bus or other means. Figure 6 The example of connecting through bus is taken in the following.

[0133] The input device 30 can receive input digital or character information, and generate key signal input related to the user settings and function control of the computer device, such as a touch screen, a keypad, a mouse, a track pad, a touch pad, an indicator bar, one or more mouse buttons, a trackball, a joystick, etc. The output device 40 may include a display device, an auxiliary lighting device (e.g., an LED) and a tactile feedback device (e.g., a vibration motor), etc. The above-mentioned display device includes but is not limited to a liquid crystal display, a light emitting diode, a display and a plasma display. In some optional embodiments, the display device can be a touch screen.

[0134] The embodiment of the present invention also provides a computer-readable storage medium. The method according to the embodiment of the present invention can be implemented in hardware, firmware, or can be implemented as a computer code that can be recorded in a storage medium, or can be implemented as a computer code that is originally stored in a remote storage medium or a non-temporary machine-readable storage medium and will be stored in a local storage medium through a network download, so that the method described herein can be stored in such software processing on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. Among them, the storage medium can be a magnetic disk, an optical disk, a read-only storage memory, a random access memory, a flash memory, a hard disk or a solid-state hard disk, etc.; further, the storage medium can also include a combination of the above types of memories. It can be understood that a computer, a processor, a microprocessor controller, or programmable hardware includes a storage component that can store or receive software or computer code. When the software or computer code is accessed and executed by a computer, a processor, or hardware, the method shown in the above embodiment is implemented.

[0135] A part of the present invention may be applied as a computer program product, such as a computer program instruction, which, when executed by a computer, can call or provide the method and / or technical solution according to the present invention through the operation of the computer. Those skilled in the art should understand that the existence of the computer program instruction in a computer-readable medium includes, but is not limited to, a source file, an executable file, an installation package file, etc., and accordingly, the way in which the computer program instruction is executed by the computer includes, but is not limited to: the computer directly executes the instruction, or the computer compiles the instruction and then executes the corresponding compiled program, or the computer reads and executes the instruction, or the computer reads and installs the instruction and then executes the corresponding installed program. Here, the computer-readable medium may be any available computer-readable storage medium or communication medium accessible to the computer.

[0136] Although the embodiments of the present invention have been described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present invention, and such modifications and variations are all within the scope defined by the appended claims.

Claims

1. A memory management method, characterized in that: The method comprises: Generate a state information matrix according to the usage status of each atomic memory block in the physical memory information; each element in the state information matrix is ​​used to indicate whether each atomic memory block is used; Generate an index table array based on the state information matrix; the index table array includes an intra-row index table array and an inter-row index table array; the index table array is used to indicate the usage of memory blocks of different specifications; the memory blocks of different specifications are used to indicate the continuous unused atomic memory blocks of different lengths in the state information matrix; Based on the index table array, determining a target memory block corresponding to the memory application request; Based on the target memory block, the state information matrix and the index table array are updated.

2. The method according to claim 1, characterized in that The step of generating an index table array based on the state information matrix comprises: An in-row index table array and an inter-row index table array are generated based on the state information matrix; the number of columns of the in-row index table array and the inter-row index table array are both the number of memory block specifications, the number of rows of the in-row index table array is equal to the number of rows of the state information matrix, and the number of rows of the inter-row index table array is 1 less than the number of rows of the in-row index table array.

3. The method according to claim 2, characterized in that The step of determining a target memory block corresponding to a memory application request based on the index table array includes: Based on the memory application request, determining a target area in the state information matrix in the index table array; A target memory block having a size corresponding to the memory application request is selected in the target area.

4. The method according to claim 3, characterized in that The step of determining a target area in a state information matrix in an index table array based on a memory application request includes: If there is an idle memory block with the same size as the memory application request in the index table array, confirming the area in the state information matrix corresponding to the idle memory block as the target area; If there is no idle memory block with the same size as the memory application request in the index table array, the area in the state information matrix corresponding to the idle memory block larger than the minimum size of the memory application request is confirmed as the target area.

5. The method according to claim 4, characterized in that The step of selecting a target memory block having a size corresponding to the memory application request in the target area includes: The target memory block with the smallest address in the target area and a size corresponding to the memory application request is selected.

6. The method according to any one of claims 1 to 5, characterized in that: The method further comprises: If the memory application request is successful, a memory application success message and the address of the target memory block are responded to the business layer; otherwise, a memory application failure message is responded to the business layer.

7. The method according to claim 6, characterized in that The method further comprises: In response to a memory release request, the state information matrix and the index table array are updated.

8. A memory management device, characterized in that: The device comprises: A matrix generation module, used to generate a state information matrix according to the use status of each atomic memory block in the physical memory information; each element in the state information matrix is ​​used to indicate whether each atomic memory block is used; A generation array module, used for generating an index table array based on the state information matrix; the index table array includes an intra-row index table array and an inter-row index table array; the index table array is used for indicating the usage of memory blocks of different specifications; the memory blocks of different specifications are used for indicating the continuous unused atomic memory blocks of different lengths in the state information matrix; A determination module, configured to determine a target memory block corresponding to a memory application request based on the index table array; An update module is used to update the state information matrix and the index table array based on the target memory block.

9. A computer device, characterized in that: include: A memory and a processor, wherein the memory and the processor are communicatively connected to each other, the memory stores computer instructions, and the processor executes the memory management method according to any one of claims 1 to 7 by executing the computer instructions.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a computer to execute the memory management method according to any one of claims 1 to 7.

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