Display panel and display device

Abstract

The invention provides a display panel and a display device. Specifically, the display panel comprises a substrate layer, a first metal shielding layer, a second metal shielding layer and a driving layer, the first metal shielding layer, the second metal shielding layer and the driving layer are sequentially arranged on the substrate layer, and the first metal shielding layer is in conduction connection with the second metal shielding layer; wherein the driving layer comprises a first electrode layer; the second metal shielding layer is conducted and connected with the first electrode layer; the orthographic projection of the second metal shielding layer on the substrate layer and the orthographic projection of the first metal shielding layer on the substrate layer are at least partially overlapped and completely cover the substrate layer; the driving layer comprises a plurality of thin film transistors; the second metal shielding layer comprises a plurality of first shielding parts which are arranged at intervals; the orthographic projection of at least one thin film transistor on the substrate layer is located in the orthographic projection of the first shielding part on the substrate layer. According to the technical scheme, the influence of charges of the substrate layer on the thin film transistor is greatly reduced, and the technical effect of improving poor display such as residual images is achieved.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] Organic Light Emitting Diode (OLED) display devices have the advantages of low energy consumption, high brightness, fast response time, wide viewing angle, light weight, etc., and are widely used in mobile phones, tablet computers and other devices. In related technologies, thin film transistors (TFT) are used to drive organic light emitting diodes. However, the charges in the substrate layer of the display device have an adverse effect on the performance of the thin film transistor, thereby affecting the display effect. Summary of the invention

[0003] In view of this, an object of the present disclosure is to provide a display panel and a display device.

[0004] Based on the above purpose, the present disclosure provides a display panel, comprising: a substrate layer, and a first metal shielding layer, a second metal shielding layer and a driving layer sequentially arranged on the substrate layer, wherein the first metal shielding layer is conductively connected to the second metal shielding layer; wherein:

[0005] The driving layer includes a first electrode layer; the second metal shielding layer is conductively connected to the first electrode layer;

[0006] The orthographic projection of the second metal shielding layer on the substrate layer and the orthographic projection of the first metal shielding layer on the substrate layer at least partially overlap and completely cover the substrate layer;

[0007] The driving layer includes a plurality of thin film transistors; the second metal shielding layer includes a plurality of first shielding portions spaced apart from each other; the orthographic projection of at least one of the thin film transistors on the substrate layer is located within the orthographic projection of the first shielding portion on the substrate layer.

[0008] Based on the same inventive concept, an embodiment of the present disclosure further provides a display device, comprising any of the display panels described above.

[0009] From the above description, it can be seen that the present disclosure provides a display panel and a display device provided by an embodiment, in which a first metal blocking layer and a second metal blocking layer are arranged between a substrate layer and a driving layer; the orthographic projection of the second metal blocking layer on the substrate layer and the orthographic projection of the first metal blocking layer on the substrate layer at least partially overlap and completely cover the substrate layer; the second metal blocking layer includes a plurality of first blocking portions spaced from each other; the orthographic projection of at least one thin film transistor on the substrate layer is located within the orthographic projection of the first blocking portion on the substrate layer; such a technical solution greatly reduces the influence of the charge of the substrate layer on the thin film transistor, thereby achieving the technical effect of improving display defects such as afterimages. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In order to more clearly illustrate the technical solutions in the present disclosure or related technologies, the drawings required for use in the embodiments or related technical descriptions are briefly introduced below. Obviously, the drawings described below are only embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0011] Figure 1 A schematic diagram showing the structure of a display panel provided by an embodiment of the present disclosure is shown;

[0012] Figure 2 A top view showing a partial structure of a display panel provided by an embodiment of the present disclosure;

[0013] Figure 3 A top view showing a partial structure of another display panel provided by an embodiment of the present disclosure;

[0014] Figure 4 A structural schematic diagram of another display panel provided by an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0015] In order to make the purpose, technical solution and advantages of the present disclosure more clear, the present disclosure is further described in detail below in combination with specific embodiments and with reference to the accompanying drawings. In the accompanying drawings, the thickness and shape of some layers and regions may be exaggerated for better understanding and ease of description.

[0016] It should be noted that, unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the embodiments of the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. "Including" or "comprising" and similar words mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0017] When terms such as "on", "above", "below", and "beside" are used to describe the positional relationship between two components, one or more components may be located between the two components unless these terms are used together with the terms "immediately" or "directly". When an element or layer is disposed "on" another element or layer, another layer or element may be directly inserted on the other element or between them.

[0018] As described in the background art section, the charges in the substrate layer of the display device have an adverse effect on the performance of the thin film transistor, thereby affecting the display effect, such as afterimage.

[0019] In view of this, the present disclosure provides a display panel and a display device provided by an embodiment, in which a first metal blocking layer and a second metal blocking layer are arranged between a substrate layer and a driving layer; the orthographic projection of the second metal blocking layer on the substrate layer and the orthographic projection of the first metal blocking layer on the substrate layer at least partially overlap and completely cover the substrate layer; the second metal blocking layer includes a plurality of first blocking portions spaced from each other; the orthographic projection of at least one thin film transistor on the substrate layer is located within the orthographic projection of the first blocking portion on the substrate layer; such a technical solution greatly reduces the influence of the charge of the substrate layer on the thin film transistor, thereby achieving the technical effect of improving display defects such as afterimages.

[0020] Figure 1 FIG. 1 is a schematic diagram showing the structure of a display panel 100 provided in an embodiment of the present disclosure. Figure 1As shown, the display panel 100 includes a photoresist layer 112, a substrate layer 101, a first metal shielding layer 102, a first anti-reflection layer 103, a second metal shielding layer 105, a second anti-reflection layer 106, a driving layer 107, a first dielectric layer 109, a flat layer 110 and a light-emitting layer 111. The material of the substrate layer 101 can be polyimide (PI), polycarbonate, acrylic glass, etc. It should be noted that the material of the substrate layer 101 is only an example, and the embodiment of the present disclosure does not limit the material of the substrate layer 101.

[0021] In some embodiments, a first metal blocking layer 102 , a first anti-reflection layer 103 , a second metal blocking layer 105 , a second anti-reflection layer 106 , a driving layer 107 , a first dielectric layer 109 , a planarization layer 110 and a light-emitting layer 111 are sequentially disposed on the substrate layer 101 .

[0022] Optionally, the materials of the first metal shielding layer 102 and the second metal shielding layer 105 are independently selected from at least one of Mo, Al, Ti, and Cu. For example, the material of the first metal shielding layer 102 is Al, and the material of the second metal shielding layer 105 is Cu. For another example, the materials of the first metal shielding layer 102 are Mo and Ti, and the materials of the second metal shielding layer 105 are Mo and Ti. In other words, the materials of the first metal shielding layer 102 and the second metal shielding layer 105 can be the same or different, and the present disclosure does not specifically limit this.

[0023] Furthermore, the driving layer 107 includes a plurality of thin film transistors 108. The first metal shielding layer 102 and the second metal shielding layer 105 can reduce the interference of charges in the substrate layer 101 on the thin film transistors 108, and enhance the anti-interference capability of the thin film transistors 108 to charges.

[0024] Figure 2 A top view showing a partial structure of a display panel provided by an embodiment of the present disclosure; Figure 3 A top view of a partial structure of another display panel provided by the embodiment of the present disclosure is shown. Figure 2 and Figure 3 The specific structures of the first metal blocking layer 102 and the second metal blocking layer 105 are exemplarily described.

[0025] like Figure 2 As shown, the orthographic projection of the first metal shielding layer 102 on the substrate layer 101 covers the entire substrate layer 101, which can completely isolate the substrate layer 101 and the thin film transistor 108, greatly reducing the interference of the charge in the substrate layer 101 on the thin film transistor 108. Figure 2 The second metal shielding layer 105 includes a plurality of first light shielding portions 1051 spaced apart from each other. Figure 2As shown, the orthographic projection of any thin film transistor 108 on the substrate layer is located within the orthographic projection of the first light shielding portion 1051. The first light shielding portion 1051 is used to shield the area where each thin film transistor 108 is located again, further enhancing the anti-interference ability of the thin film transistor 108 to charges.

[0026] It should be noted that the number of thin film transistors 108 corresponding to the first light shielding portion 1051 can be flexibly set. For example, one first light shielding portion 1051 corresponds to two thin film transistors 108 (eg, Figure 2 As shown); For example, one first light shielding portion 1051 corresponds to one thin film transistor 108 (as shown Figure 3 It should be understood that, since the orthographic projection of the first metal shielding layer 102 on the substrate layer 101 covers the entire substrate layer 101, the orthographic projections of the plurality of first light shielding portions 1051 on the substrate layer 101 are completely within the orthographic projection of the first metal shielding layer 102 on the substrate layer 101.

[0027] In some alternative embodiments, the first metal shielding layer 102 includes a mesh shielding portion. Figure 3 As shown on the left, the first metal shielding layer 102 forms a grid shielding portion by providing openings 1021. Optionally, the distance between adjacent openings can be H 1 . Figure 3 The right side shows the positional relationship of the first metal shielding layer 102, the first shielding portion 1051 and the thin film transistor 108 in orthographic projection. Figure 3 As shown on the right side, the gap between the orthographic projections of adjacent first shielding portions 1051 on the substrate layer 101 (the size of the gap H 2 ) is located within the orthographic projection of the grid shielding portion on the substrate layer, i.e., H 1 >H 2 In other words, the orthographic projection of the first shielding portion 1051 on the substrate layer 101 and the orthographic projection of the grid shielding portion on the substrate layer 101 at least partially overlap and cover the entire substrate layer 101. In such a technical solution, the first shielding portion 1051 completely shields the area of ​​the thin film transistor 108, and the cooperation of the grid shielding portion and the first shielding portion 1051 reduces the interference of the charge of the substrate layer 101 on the thin film transistor 108, thereby achieving the technical effect of improving the display effect.

[0028] Figure 4 A schematic diagram of the structure of another display panel 200 provided by the embodiment of the present disclosure is shown. Figure 1 and Figure 4 , the driving layer 107 and the light-emitting layer 111 are introduced in detail.

[0029] like Figure 1 and Figure 4As shown, the driving layer 107 includes an active layer 1071, a first insulating layer 1072, a second electrode layer 1073, a second insulating layer 1074 and a first electrode 1077 to form a plurality of thin film transistors 108. The active layer 1071 is disposed on a side of the second metal blocking layer 105 away from the substrate layer 101; the first insulating layer 1072, the second electrode layer 1073, the second insulating layer 1074 and the first electrode 1077 are sequentially disposed on a side of the active layer 1071 away from the substrate layer 101.

[0030] In some embodiments, the second electrode layer 1073 may be a gate layer, and the first electrode layer 1077 may be a source-drain layer. The first electrode layer 1077 includes a source electrode 1075 and a drain electrode 1076, and the source electrode 1075 and the drain electrode 1076 are respectively conductively connected to the active layer 1071.

[0031] Optionally, the driving layer 107 further includes a second dielectric layer ( Figure 1 and Figure 4 The second dielectric layer is located between the first insulating layer 1072 and the second electrode layer 1073. The second dielectric layer can increase the insulation performance between the second electrode layer 1073 and the active layer 1071, which helps to improve the stability of the thin film transistor 108.

[0032] Furthermore, if Figure 4 As shown, the light emitting layer 111 includes a third electrode layer 1111 , where the third electrode layer 1111 may be an anode layer.

[0033] Combination Figure 1 and Figure 4 As shown, the first metal shielding layer 102 can be conductively connected to the second metal shielding layer 105 by means of the first connecting line 1041; the second metal shielding layer 105 is conductively connected to the first electrode layer 1077 by means of the second connecting line 1042 (refer to Figure 1 ) or the third electrode layer 1111 (reference Figure 4 ). The first connecting line 1041 and the second connecting line 1042 are connected to realize the conduction between the first metal shielding layer 102, the second metal shielding layer 105 and the first electrode layer 1077 or the third electrode layer 1111, so that the first electrode layer 1077 or the third electrode layer 1111 can provide a certain voltage value to the first metal shielding layer 102 and the second metal shielding layer 105, which is more conducive to the first metal shielding layer 102 and the second metal shielding layer 105 shielding the charges in the substrate layer 101, thereby increasing the stability of the thin film transistor 108.

[0034] The inventors of the present disclosure also noticed that the light irradiated from the light-emitting side or the backlight side of the display panel will produce reflected light or refracted light, and these light rays have a photoexcitation effect on the thin-film transistor 108, increasing the leakage current of the thin-film transistor 108, causing the problem of redness and pinkness of the displayed image. The photoblocking layer 112, the first anti-reflection layer 103 and the second anti-reflection layer 106 help to reduce the photoexcitation effect of various reflected light or refracted light on the thin-film transistor 108, reduce the leakage current, and improve the redness of the displayed image. It should be noted that the photoblocking layer 112, the first anti-reflection layer 103 and the second anti-reflection layer 106 can be optionally set, for example, only the photoblocking layer 112 and the first anti-reflection layer 103 are set, and only the first anti-reflection layer 103 and the second anti-reflection layer 106 are set, and the present disclosure does not limit this.

[0035] In some embodiments, Figure 1 As shown, the photoresist layer 112 is disposed on the side of the substrate layer 101 away from the light emitting side of the display panel. Optionally, the material of the photoresist layer 112 is black ink, and the photoresist layer 112 can be formed on the substrate layer 101 by evaporation.

[0036] By using the photoresist layer 112 to absorb the ambient light on the light-emitting side of the substrate layer 101 away from the display panel 100 and the light irradiating from the light-emitting side, the effects of various reflected light and refracted light on the light excitation of the thin film transistor can be reduced, the leakage current can be reduced, and the problem of red display screen can be improved.

[0037] In some embodiments, the first anti-reflection layer 103 is disposed on the side of the first metal shielding layer 102 away from the substrate layer 101, which can reduce the reflection and refraction of ambient light irradiated from the gaps between the thin film transistors 108. In some embodiments, the second anti-reflection layer 106 is disposed on the side of the second metal shielding layer 105 away from the substrate layer 101, which can reduce the light reflection and refraction in the area of ​​the second metal shielding layer 105. The anti-reflection layer can greatly reduce the reflected light and refracted light of the ambient light, the light emitting layer and other light in the display panel, reduce the impact on the thin film transistors, reduce the generation of leakage current, and improve the problem of red display screen.

[0038] In some embodiments, the materials of the first anti-reflection layer 103 and the second anti-reflection layer 106 include at least one of magnesium fluoride and silicon nitride. For example, the material of the first anti-reflection layer 103 is magnesium fluoride, and the material of the second anti-reflection layer 106 is silicon nitride; for another example, the materials of the first anti-reflection layer 103 and the second anti-reflection layer 106 are both magnesium fluoride. It should be noted that the first anti-reflection layer 103 and the second anti-reflection layer 106 can be prepared based on magnesium fluoride and silicon nitride by controlling the thickness of the film layer, and the present disclosure does not specifically limit this.

[0039] It should be noted that the first anti-reflection layer 103 and the second anti-reflection layer 106 have insulating properties and function as insulating layers. In some embodiments, the first anti-reflection layer 103 and the second anti-reflection layer 106 may be replaced by an insulating layer.

[0040] In some embodiments, the display panel 100 further includes a third insulating layer or a third dielectric layer ( Figure 1 and Figure 4 (not shown in the figure), the third insulating layer or the third dielectric layer is disposed on the side of the second anti-reflection layer 105 away from the substrate layer 101. By adding the third insulating layer or the third dielectric layer, it is helpful to improve the insulation performance between the second metal blocking layer 105 and the remote side 1071, and improve the stability of the thin film transistor 108.

[0041] Optionally, the materials of the first dielectric layer 109, the second dielectric layer, and the third dielectric layer can be respectively resin materials that do not contain glass fiber, such as one selected from the group consisting of liquid crystal polymer, BT (bismaleimide triazine) resin, semi-cured prepreg, ABF (Ajinomoto Build-up) film, epoxy resin and polyimide resin, but the present disclosure is not limited to this.

[0042] Based on the same inventive concept, the present disclosure provides a display panel. Specifically, Figure 1 and Figure 4 As shown, the display panel includes: a substrate layer 101 and a first metal shielding layer 102, a second metal shielding layer 105 and a driving layer 107 sequentially arranged on the substrate layer 101, and the first metal shielding layer 102 is conductively connected to the second metal shielding layer 105; wherein,

[0043] The driving layer 107 includes a first electrode layer 1077; the second metal shielding layer 105 is conductively connected to the first electrode layer 1077;

[0044] The orthographic projection of the second metal shielding layer 105 on the substrate layer 101 and the orthographic projection of the first metal shielding layer 102 on the substrate layer 101 at least partially overlap and completely cover the substrate layer 101;

[0045] like Figure 2 and Figure 3 As shown, the driving layer 107 includes multiple thin film transistors 108; the second metal blocking layer 105 includes multiple first blocking portions 1051 spaced apart from each other; the orthographic projection of at least one thin film transistor 108 on the substrate layer 101 is located within the orthographic projection of the first blocking portion 1051 on the substrate layer 101.

[0046] The first metal blocking layer 102 and the second metal blocking layer 105 are used to reduce the influence of the charges of the substrate layer 101 on the thin film transistor 108 , thereby improving the stability of the thin film transistor 108 .

[0047] In some embodiments, Figure 3 As shown on the right side, the first shielding portion 1051 corresponds to the thin film transistor 108 one by one; Figure 2 As shown, the orthographic projection of the first metal blocking layer 102 on the substrate layer 101 completely covers the substrate layer 101 .

[0048] In some embodiments, Figure 3 As shown on the left side, the first metal shielding layer 102 includes a grid shielding portion; Figure 3 As shown on the right side, the gap between the orthographic projections of adjacent first shielding portions 1051 on the substrate layer 101 is located within the orthographic projection of the grid shielding portion on the substrate layer 101 .

[0049] In some embodiments, Figure 1 and Figure 4 As shown, at least one anti-reflection layer 103 , 106 is further included; the at least one anti-reflection layer 103 , 106 is disposed on a side of at least one of the first metal blocking layer 102 and the second metal blocking layer 105 away from the substrate layer 101 .

[0050] In some embodiments, at least one anti-reflection layer includes a first anti-reflection layer 103 and a second anti-reflection layer 106; wherein the first anti-reflection layer 103 is disposed on a side of the first metal blocking layer 102 away from the substrate layer 101; and the second anti-reflection layer 106 is disposed on a side of the second metal blocking layer 105 away from the substrate layer 101.

[0051] In some embodiments, a third insulating layer or a third dielectric layer is further included. The third insulating layer or the third dielectric layer is disposed on a side of the second anti-reflection layer 106 away from the substrate layer 101 .

[0052] In some embodiments, the material of the anti-reflection layer includes at least one of magnesium fluoride and silicon nitride.

[0053] In some embodiments, a photoresist layer 112 is further included; the photoresist layer 112 is disposed on a side of the substrate layer 101 away from the first metal shielding layer 102 .

[0054] In some embodiments, the material of the substrate layer 101 is selected from at least one of polyimide, polycarbonate, and acrylic glass.

[0055] In some embodiments, Figure 4 As shown, it also includes a light-emitting layer 111; the light-emitting layer 111 is arranged on a side of the driving layer 107 away from the substrate layer 101; wherein,

[0056] The light emitting layer 111 includes a third electrode layer 1111 ; the third electrode layer 1111 replaces the first electrode layer 1077 and is conductively connected to the second metal shielding layer 105 .

[0057] In some embodiments, a first dielectric layer 109 and a planar layer 110 are further included. The first dielectric layer 109 and the planar layer 110 are disposed between the light emitting layer 111 and the driving layer 107 , and the first dielectric layer 109 is located on a side of the planar layer 110 away from the light emitting layer 111 .

[0058] In some embodiments, the driving layer 107 further includes an active layer 1071 , a second electrode layer 1073 , a first insulating layer 1072 , and a second insulating layer 1074 ; wherein,

[0059] The active layer 1071 is arranged on the side of the second metal blocking layer 105 away from the substrate layer 101; the first insulating layer 1072, the second electrode layer 1073, and the second insulating layer 1074 are arranged in sequence on the side of the active layer 1071 away from the substrate layer 101; the first electrode layer 1077 is arranged on the side of the second insulating layer 1074 away from the active layer 1071 and is connected to the active layer 1071.

[0060] In some embodiments, the driving layer 107 further includes a second dielectric layer, and the second dielectric layer is located between the first insulating layer 1072 and the second electrode layer 1073 .

[0061] In some embodiments, the materials of the first metal blocking layer 102 and the second metal blocking layer 105 are independently selected from at least one of Mo, Al, Ti, and Cu.

[0062] Based on the same inventive concept, the present embodiment also provides a display device, comprising any of the aforementioned display panels.

[0063] The device of the above embodiment has the corresponding display panel in any of the above embodiments, and has the beneficial effects of the corresponding display panel embodiment, which will not be described in detail here.

[0064] Those skilled in the art should understand that the discussion of any of the above embodiments is merely illustrative and is not intended to imply that the scope of the present disclosure (including the claims) is limited to these examples. Based on the concept of the present disclosure, the technical features in the above embodiments or different embodiments may be combined, the steps may be implemented in any order, and there are many other variations of the different aspects of the embodiments of the present disclosure as described above, which are not provided in detail for the sake of simplicity.

[0065] The embodiments of the present disclosure are intended to cover all such substitutions, modifications and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the embodiments of the present disclosure should be included in the scope of protection of the present disclosure.

Claims

1. A display panel, characterized in that: include: A substrate layer and a first metal shielding layer, a second metal shielding layer and a driving layer sequentially arranged on the substrate layer, wherein the first metal shielding layer is conductively connected to the second metal shielding layer; wherein: The driving layer includes a first electrode layer; the second metal shielding layer is conductively connected to the first electrode layer; The orthographic projection of the second metal shielding layer on the substrate layer and the orthographic projection of the first metal shielding layer on the substrate layer at least partially overlap and completely cover the substrate layer; The driving layer includes a plurality of thin film transistors; the second metal shielding layer includes a plurality of first shielding portions spaced apart from each other; the orthographic projection of at least one of the thin film transistors on the substrate layer is located within the orthographic projection of the first shielding portion on the substrate layer.

2. The display panel according to claim 1, characterized in that: The first shielding portion corresponds to the thin film transistor in a one-to-one manner; the orthographic projection of the first metal shielding layer on the substrate layer completely covers the substrate layer.

3. The display panel according to claim 1, characterized in that: The first metal shielding layer includes a grid shielding portion; wherein, The gap between the orthographic projections of adjacent first shielding parts on the substrate layer is located within the orthographic projection of the grid shielding part on the substrate layer.

4. The display panel according to claim 1, characterized in that: It also includes at least one anti-reflection layer; the at least one anti-reflection layer is arranged on a side of at least one of the first metal blocking layer and the second metal blocking layer away from the substrate layer.

5. The display panel according to claim 4, characterized in that: The at least one anti-reflection layer includes a first anti-reflection layer and a second anti-reflection layer; wherein the first anti-reflection layer is arranged on a side of the first metal blocking layer away from the substrate layer; and the second anti-reflection layer is arranged on a side of the second metal blocking layer away from the substrate layer.

6. The display panel according to claim 5, characterized in that: The invention also includes a third insulating layer or a third dielectric layer, wherein the third insulating layer or the third dielectric layer is arranged on a side of the second anti-reflection layer away from the substrate layer.

7. The display panel according to claim 4, characterized in that: The material of the anti-reflection layer includes at least one of magnesium fluoride and silicon nitride.

8. The display panel according to claim 1, characterized in that: It also includes a photoresist layer; the photoresist layer is arranged on a side of the substrate layer away from the first metal shielding layer.

9. The display panel according to claim 1, characterized in that: The material of the substrate layer is selected from at least one of polyimide, polycarbonate and acrylic glass.

10. The display panel according to claim 1, characterized in that: It also includes a light-emitting layer; the light-emitting layer is arranged on a side of the driving layer away from the substrate layer; wherein, The light-emitting layer includes a third electrode layer; the third electrode layer replaces the first electrode layer and is conductively connected to the second metal shielding layer.

11. The display panel according to claim 10, characterized in that: It also includes a first dielectric layer and a planar layer, wherein the first dielectric layer and the planar layer are arranged between the light-emitting layer and the driving layer, and the first dielectric layer is located on a side of the planar layer away from the light-emitting layer.

12. The display panel according to claim 1, characterized in that: The driving layer further includes an active layer, a second electrode layer, a first insulating layer and a second insulating layer; wherein, The active layer is arranged on a side of the second metal blocking layer away from the substrate layer; the first insulating layer, the second electrode layer, and the second insulating layer are arranged in sequence on a side of the active layer away from the substrate layer; the first electrode layer is arranged on a side of the second insulating layer away from the active layer and is connected to the active layer.

13. The display panel according to claim 12, characterized in that: The driving layer further includes a second dielectric layer, and the second dielectric layer is located between the first insulating layer and the second electrode layer.

14. The display panel according to claim 1, characterized in that: The materials of the first metal blocking layer and the second metal blocking layer are independently selected from at least one of Mo, Al, Ti, and Cu.

15. A display device, characterized in that: The display panel comprises the display panel according to any one of claims 1 to 14.

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