VDMOS semiconductor power device and preparation method thereof

Abstract

The invention relates to the technical field of semiconductors, in particular to a VDMOS semiconductor power device and a preparation method thereof, and the VDMOS semiconductor power device comprises a semiconductor substrate and a semiconductor epitaxial layer. The well region is positioned in the semiconductor epitaxial layer; the source region is positioned in the well region; the local thick oxygen layer is positioned below the grid electrode between the adjacent well regions on the semiconductor epitaxial layer; the gate dielectric layer is positioned below the gate between the adjacent source regions on the semiconductor epitaxial layer; the grid electrode is positioned above the grid dielectric layer and the local thick oxygen layer; wherein the local thick oxygen layer is formed before diffusion of the well region. The VDMOS semiconductor power device adopts a gate-last oxide process and is provided with a local thick oxygen layer structure, and the local thick oxygen layer structure is formed before well region diffusion, so that the LOCOS boron absorption and phosphorus discharge effect is effectively avoided, and the reliability and the electrical property of the device are improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a VDMOS semiconductor power device and a preparation method thereof. Background Art

[0002] In the field of power semiconductors, the metal-oxide-semiconductor field-effect transistor with longitudinal conductivity prepared by vertical double diffusion process is called VDMOS. VDMOS has a wide range of applications in the field of power electronics due to its unique advantages such as fast switching speed, high input impedance, good frequency characteristics, and good thermal stability.

[0003] Typical VDMOS device structure is as follows: Figure 1 As shown. A semiconductor epitaxial layer such as a silicon epitaxial layer is formed on a semiconductor substrate such as a silicon substrate; a well region and a source region are formed in sequence on the surface of the epitaxial layer; a plurality of gate structures such as polysilicon are formed on the surface of the epitaxial layer, which are the gates of the device; a gate dielectric layer is formed between the epitaxial layer and the gate; an isolation dielectric layer is formed on the surface of the epitaxial layer; a front metal layer is formed on the surface and side of the isolation dielectric layer, wherein the metal on the surface of the isolation dielectric layer is called the source metal, which is the source of the device, and the metal on the side of the isolation dielectric layer is called a contact hole, which passes through the isolation dielectric layer and is connected to the source region and the well region; a passivation layer is formed on the surface of the front metal layer; a back metal layer is formed on the back of the substrate, which is the drain of the device.

[0004] In order to improve the gate-drain withstand voltage and reduce the gate charge, the currently commonly used process is to grow a layer of local thick oxide (LOCOS) under the polycrystalline gate. The LOCOS preparation needs to have a certain thickness and width before the gate oxide growth. On the one hand, it can reduce the electric field strength between the gate and the drain to improve the withstand voltage, and on the other hand, it can reduce the gate charge and improve the frequency characteristics.

[0005] Traditional VDMOS devices use a gate-oxide-first process, that is, gate oxide growth and polycrystalline gate etching are performed first, and then well and source region injection and diffusion processes are performed. With the gate-oxide-first process, after the gate oxide layer is grown, it will undergo a subsequent high-temperature diffusion process in the well region, which will eventually reduce the quality of the gate oxide and increase the interface state at the interface between the gate oxide and silicon, causing the electrical parameters of the device to drift and affect the stability of the device. In order to ensure the reliability of the gate oxide, a gate-oxide-last process is currently commonly used, that is, well and source region injection and diffusion are performed first, and then gate oxide growth and polycrystalline gate etching are performed. With this process, the gate oxide grows after high-temperature diffusion, thereby ensuring that the gate oxide does not undergo a high-temperature process, reducing the silicon-silicon dioxide interface state density, and its reliability is guaranteed. Therefore, in some high-reliability application fields, the gate-oxide-last process is currently commonly used.

[0006] At the solid-solid interface of different types of materials, there is a phenomenon of impurity segregation, and the concentration of impurities in the materials on both sides of the interface is different. The magnitude of the impurity segregation effect is described by the segregation coefficient, which is the ratio of the solubility of the impurity in the two materials. For the silicon-silicon dioxide interface, the segregation coefficient of boron is about 3 / 10, and the segregation coefficient of phosphorus is about 10 / 1. It can be seen that the solubility of boron in silicon dioxide is much greater than that in silicon, while the solubility of phosphorus in silicon is much greater than that in silicon dioxide. Therefore, the LOCOS thermal oxidation process will redistribute the concentration of boron and phosphorus impurities in the silicon matrix. Near the LOCOS position, the boron concentration decreases and the phosphorus concentration increases, showing a "boron absorption and phosphorus expulsion" effect.

[0007] In the gate-last oxide process, LOCOS is formed after the well region is diffused, and the LOCOS growth process shows a "boron absorption and phosphorus expulsion" effect. For N-channel VDMOS, the boron on the side of the boron-doped P-type well region close to LOCOS is absorbed, and the boron concentration is reduced, which eventually leads to a shorter channel and easy leakage of the device; for P-channel VDMOS, the phosphorus concentration on the side of the phosphorus-doped N-type well region close to LOCOS increases, which eventually leads to a longer channel and affects the device performance.

[0008] The larger the LOCOS size, the lower the electric field between the gate and the drain, the stronger the voltage resistance, and the smaller the gate charge. The better the reliability and electrical characteristics of the VDMOS device, but the more obvious the "boron absorption and phosphorus discharge" effect. It can be seen that the "boron absorption and phosphorus discharge" effect of LOCOS has a certain limit on the increase of its size, which seriously restricts the improvement of device performance. Therefore, in the last gate oxide process, improving the LOCOS preparation method is of great significance to improving device performance.

[0009] In view of this, the present invention is proposed. Summary of the invention

[0010] The object of the present invention is to provide a VDMOS semiconductor power device and a preparation method thereof, which significantly improves the reliability and electrical characteristics of the device.

[0011] In a first aspect, the present invention provides a VDMOS semiconductor power device, comprising

[0012] Semiconductor substrate;

[0013] Semiconductor epitaxial layer;

[0014] A well region, wherein the well region is located inside the semiconductor epitaxial layer;

[0015] A source region, the source region being located inside the well region;

[0016] A local thick oxygen layer, wherein the local thick oxygen layer is located below the gate between adjacent well regions on the semiconductor epitaxial layer;

[0017] A gate dielectric layer, the gate dielectric layer being located below the gate between adjacent source regions on the semiconductor epitaxial layer;

[0018] A gate, the gate being located above the gate dielectric layer and the local thick oxygen layer;

[0019] Wherein, the local thick oxygen layer is formed before the well region is diffused.

[0020] As a preferred embodiment of the present technical solution, the thickness of the local thick oxygen layer is 0.2-0.3 μm.

[0021] As a preferred embodiment of the present technical solution, it further comprises a source and a drain, wherein the source is located above the gate and contacts with both the source region and the well region; and the drain is located below the semiconductor substrate.

[0022] As a preferred embodiment of the present technical solution, it further comprises an isolation dielectric layer and a passivation layer, wherein the isolation dielectric layer is located between the gate and the source, and the passivation layer is located on the surface of the source.

[0023] As a preferred embodiment of the present technical solution, the semiconductor epitaxial layer and the source region are N-type doped, and the well region is P-type doped;

[0024] Or the semiconductor epitaxial layer and the source region are P-type doped, and the well region is N-type doped.

[0025] In a second aspect, the present invention further discloses a method for preparing the above-mentioned VDMOS semiconductor power device, which specifically comprises the following steps:

[0026] S101, growing a first pad oxide layer on the semiconductor epitaxial layer, and depositing a first hard mask layer;

[0027] S102, etching the first hard mask layer to form a window for growing a local thick oxygen layer on the first hard mask layer;

[0028] S103, using a thermal oxidation growth process to grow a local thick oxide layer, and removing the first hard mask layer and the first pad oxide layer;

[0029] S104, using ion implantation and high temperature diffusion processes to sequentially form a well region and a source region;

[0030] S105, growing a second pad oxide layer on the well region, the source region and the local thick oxide layer, and depositing a second hard mask layer;

[0031] S106, etching the second hard mask layer to form a window in the terminal region, and removing the second pad oxide layer in the window position in the terminal region;

[0032] S107, depositing a pressure-resistant dielectric layer, and selectively corroding the pressure-resistant dielectric layer;

[0033] S108, removing the remaining second hard mask layer and the second pad oxide layer;

[0034] S109, growing a gate dielectric layer, and sequentially forming a gate, a source, and a drain.

[0035] As a preferred embodiment of the present technical solution, when preparing the well region and the source region, impurity ions are injected into the semiconductor epitaxial layer and high-temperature diffusion is performed to form the well region and the source region.

[0036] As a preferred embodiment of the present technical solution, when preparing the gate, polysilicon is deposited on the surface of the gate dielectric layer and selective anisotropic etching is performed to form the gate.

[0037] As a preferred embodiment of the present technical solution, when preparing the source electrode, an isolation dielectric layer is deposited above the gate and selectively wet-etched, and a front metal layer is deposited above the isolation dielectric layer and selectively etched to form the source electrode.

[0038] As a preferred embodiment of the present technical solution, when preparing the drain electrode, a back metal layer is prepared below the semiconductor substrate to form the drain electrode.

[0039] The VDMOS semiconductor power device and the preparation method thereof of the present invention have at least the following beneficial effects:

[0040] The VDMOS semiconductor power device of the present invention comprises a semiconductor substrate epitaxial layer, a well region, a source region, a local thick oxygen layer, a gate dielectric layer and a gate, wherein the local thick oxygen layer is formed before the diffusion of the well region, thereby effectively avoiding the "boron absorption and phosphorus removal" effect of the local thick oxygen layer (LOCOS) and improving the reliability and electrical characteristics of the device.

[0041] In the preparation method of the VDMOS semiconductor power device of the present invention, the LOCOS in the cell area can be protected by the masking effect of the second hard mask layer, avoiding the consumption of LOCOS by the subsequent wet etching of the voltage-resistant dielectric layer, and realizing that the preparation of LOCOS can be controlled before the diffusion of the well area under the premise of the last gate oxide process, avoiding the influence of the "boron absorption and phosphorus discharge" effect of the LOCOS thermal growth process on the device channel. At the same time, the preparation of LOCOS and the voltage-resistant dielectric layer in the terminal area are carried out step by step, and the thickness of LOCOS can be adjusted by process separately, breaking through the limitation of the size of LOCOS in the traditional last gate oxide process, and maximizing the reliability and electrical characteristics of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0043] Figure 1 This is the structure of a typical VDMOS device;

[0044] Figure 2 The structure of the VDMOS semiconductor power device of the present invention;

[0045] Figure 3 The figure is a schematic flow chart of a method for preparing a VDMOS semiconductor power device according to the present invention;

[0046] Figure 4-16 It is a schematic diagram of the hierarchical structure during the preparation process of the VDMOS semiconductor power device of the present invention.

[0047] Description of reference numerals:

[0048] 200: semiconductor substrate; 201: semiconductor epitaxial layer; 202: well region; 203: source region; 204: gate dielectric layer; 205: gate; 206: isolation dielectric layer; 207: front metal layer; 208: passivation layer; 209: back metal layer; 210: local thick oxygen layer; 211: first pad oxide layer; 212: first hard mask layer; 213: second pad oxide layer; 214: second hard mask layer; 215: voltage-resistant dielectric layer. DETAILED DESCRIPTION

[0049] The technical solution of the present invention will be clearly and completely described below in conjunction with the embodiments. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0050] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0051] In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, "multiple" means two or more, unless otherwise clearly and specifically defined. In addition, the terms "installed", "connected" and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal connection of two components. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0052] Example 1

[0053] The present embodiment provides a structure of a VDMOS semiconductor power device, including a semiconductor substrate 200, a semiconductor epitaxial layer 201, a well region 202, a source region 203, a local thick oxygen layer 210, a gate dielectric layer 204, a gate 205, a source, a drain, an isolation dielectric layer 206 and a passivation layer 208, etc.

[0054] like Figure 2 As shown, a semiconductor epitaxial layer 201 such as a silicon epitaxial layer is formed on a semiconductor substrate 200 such as a silicon substrate, that is, the semiconductor epitaxial layer 201 covers the semiconductor substrate 200; a well region 202 and a source region 203 are sequentially formed on the surface of the semiconductor epitaxial layer 201, specifically, the well region 202 is located inside the semiconductor epitaxial layer 201; the source region 203 is located inside the well region 202; a local thick oxygen layer 210 is located below the polysilicon gate 205 between adjacent well regions 202 on the semiconductor epitaxial layer 201, and the setting of the local thick oxygen layer 210 can reduce the electric field strength between the gate and the drain to improve the withstand voltage on the one hand, and can reduce the gate charge and improve the frequency characteristics on the other hand; the gate dielectric layer 204 is located in the semiconductor epitaxial layer 2 01 is below the polysilicon gate 205 between adjacent source regions 203; the gate 205 is located above the gate dielectric layer 204 and the local thick oxygen layer 210; the isolation dielectric layer 206 is located between the gate 205 and the source, specifically, a front metal layer 207 is formed on the surface and side of the isolation dielectric layer 206, wherein the metal on the surface of the isolation dielectric layer 206 is called the source metal, which is the source of the device, and the metal on the side of the isolation dielectric layer 206 is called the contact hole, which passes through the isolation dielectric layer 206 and is connected to the source region 203 and the well region 202; a passivation layer 208 such as silicon nitride is formed above the front metal layer 207; a back metal layer 209 is formed on the back side of the semiconductor substrate 200, which is the drain of the device.

[0055] The VDMOS semiconductor power device of this embodiment adopts the last gate oxide process and has a local thick oxygen layer 210 structure, and the local thick oxygen layer 210 structure is formed before the well region 202 diffuses, which effectively avoids the LOCOS "boron absorption and phosphorus removal" effect and improves the reliability and electrical characteristics of the device.

[0056] In another specific embodiment of the present invention, the semiconductor substrate 200, the semiconductor epitaxial layer 201 and the source region 203 are of the first conductivity type, and the well region 202 is of the second conductivity type. For example, the semiconductor substrate 200, the semiconductor epitaxial layer 201 and the source region 203 are N-type doped, and the well region 202 is P-type doped. In this case, the resulting device is an N-type VDMOS semiconductor power device; or the semiconductor substrate 200, the semiconductor epitaxial layer 201 and the source region 203 are P-type doped, and the well region 202 is N-type doped. In this case, the resulting device is a P-type VDMOS semiconductor power device.

[0057] Example 2

[0058] like Figure 3-16 As shown, this embodiment provides a method for preparing a VDMOS semiconductor power device, which specifically includes the following steps:

[0059] S101, forming a semiconductor epitaxial layer 201 on a semiconductor substrate 200, growing a first pad oxide layer 211 on the semiconductor epitaxial layer 201, and depositing a first hard mask layer 212, such as Figure 4 As shown;

[0060] The material of the first pad oxide layer 211 is mainly silicon oxide, which can be realized by a thermal oxidation process, that is, the semiconductor substrate 200 (such as silicon) reacts with oxygen at a high temperature to form a dense silicon oxide layer;

[0061] The material of the first hard mask layer 212 can be titanium nitride, silicon nitride, silicon oxide, etc. These materials have good chemical stability and mechanical strength, and can effectively protect the semiconductor material underneath during the subsequent etching process to ensure the accuracy and integrity of the pattern.

[0062] S102, selectively anisotropically etching the first hard mask layer 212, etching a window on the first hard mask layer 212 to form a growth window for the local thick oxygen layer 210, such as Figure 5 As shown;

[0063] S103, using a thermal oxidation growth process to grow a local thick oxide layer 210, and then using a wet etching or dry etching process to remove the first hard mask layer 212 and the first pad oxide layer 211, such as Figure 6 As shown;

[0064] The local thick oxide layer 210 is grown by thermal oxidation, which has the advantages of stable growth rate, high quality of oxide layer, and close combination with semiconductor materials. In addition, due to the presence of the first hard mask layer 212, the oxidation reaction only occurs on the surface of the semiconductor epitaxial layer 201 below the window, achieving the precise growth of the local thick oxide layer 210. Therefore, by precisely controlling the oxidation time, temperature and other parameters, the thickness of the local thick oxide layer 210 can be precisely controlled to meet the use requirements of the device design.

[0065] S104, using ion implantation and high temperature diffusion process, forming the well region 202 and the source region 203 in sequence, such as Figure 7 As shown;

[0066] Specifically, the formation of the well region 202 and the source region 203 is usually achieved by ion implantation and high temperature diffusion. For example, an ion implanter may be used to implant specific types of impurity ions (for the well region, impurity ions such as boron ions B + For P-type wells, phosphorus ions P + For N-type wells; for source regions, impurity ions such as BF2 + For P type, As + For N-type ions, ions are accelerated under a high voltage electric field and implanted into the semiconductor epitaxy 201. The ion implantation process can damage the semiconductor lattice, so an annealing process (usually heating at a high temperature for several minutes) is required to repair the lattice and activate the implanted impurity ions.

[0067] After ion implantation, high-temperature diffusion is further performed. For example, after the well region 202 and the source region 203 are implanted, the semiconductor wafer coated with the impurity source can be placed in a high-temperature furnace for heating. At high temperatures, the impurity elements diffuse from the high-concentration region (surface) to the low-concentration region (inside the semiconductor) to form the desired well region 202 and source region 203. During the diffusion process, parameters such as temperature, time, and impurity concentration need to be precisely controlled to ensure the quality and position accuracy of the well region 202 and the source region 203.

[0068] S105, using a thermal oxidation process to grow a second pad oxide layer 213 on the well region 202, the source region 203 and the local thick oxide layer 210, and deposit a second hard mask layer 214, such as Figure 8 As shown;

[0069] The specific materials and growth methods used for the second pad oxide layer 213 and the second hard mask layer 214 are the same as those in step S101 , and reference may also be made to the prior art, which will not be described in detail in the present invention.

[0070] S106, selectively anisotropically etching the second hard mask layer 214 to etch out a window position for forming a terminal region, and removing the second pad oxide layer 213 in the window position of the terminal region by wet etching or other methods, such as Fig. 9 As shown;

[0071] S107, depositing a voltage-resistant dielectric layer 215 in the cell region and the terminal region, such as Fig.10 As shown, the voltage-resistant dielectric layer 215 is selectively wet-etched, as shown in FIG. Fig.11 As shown;

[0072] It can be seen that the preparation of LOCOS of the present invention and the voltage-resistant dielectric layer 215 in the terminal area are carried out in steps, and the thickness of LOCOS can be adjusted by the process separately, for example, it can be controlled at 0.2-0.3μm, which can not only meet the improvement of device reliability and electrical characteristics, but also allow the device to develop in the direction of small size.

[0073] S108, removing the remaining second hard mask layer 214 and the second pad oxide layer 213 by wet etching, such as Fig.12 As shown;

[0074] S109, growing a gate dielectric layer 204, and sequentially forming a gate 205, a source electrode and a drain electrode, such as Figure 13-16 As shown;

[0075] The material of the gate dielectric layer 204 is usually silicon dioxide, which can be grown by thermal oxidation or chemical vapor deposition.

[0076] The material of the gate 205 is usually polysilicon. During the preparation of the gate 205, first, a layer of polysilicon is deposited on the grown gate dielectric layer 204 by chemical vapor deposition (CVD) or physical vapor deposition (PVD), and then the polysilicon portion not protected by the photoresist is removed by anisotropic etching technology (such as reactive ion etching (RIE)) to form the gate 205 structure.

[0077] After the gate 205 and the source and drain regions are formed, an isolation dielectric layer 206 (such as silicon oxide or silicon nitride) needs to be deposited to isolate different parts of the device to prevent current leakage. Then, a portion of the isolation dielectric layer 206 is removed by a wet etching process to expose the contact area of ​​the source and drain regions.

[0078] Furthermore, a front metal layer 207 (such as aluminum, copper, etc.) is deposited on the contact area of ​​the source and drain regions, and then the front metal layer 207 is etched into a desired source pattern through photolithography and selective etching processes.

[0079] Furthermore, a passivation layer 208 (such as silicon oxide, silicon nitride or polymer) is deposited on the entire device surface to protect the device from the influence of the external environment and provide a flat surface for subsequent processes; then, through lithography and selective etching processes, through holes or openings are formed on the passivation layer 208 to expose the contact area of ​​the front metal layer 207.

[0080] Finally, a back metal layer 209 (such as titanium nickel silver, etc.) is prepared on the back side of the semiconductor substrate 200 .

[0081] Specifically, when the semiconductor substrate 200, the semiconductor epitaxial layer 201 and the source region 203 are N-type doped, and the well region 202 is P-type doped, the resulting device is an N-type VDMOS semiconductor power device; when the semiconductor substrate 200, the semiconductor epitaxial layer 201 and the source region 203 are P-type doped, and the well region 202 is N-type doped, the resulting device is a P-type VDMOS semiconductor power device.

[0082] It can be seen that in the preparation method of the VDMOS semiconductor power device using the last gate oxide process and having a local thick oxygen layer 210 structure (LOCOS), the masking effect of the second hard mask layer 214 can protect the LOCOS in the cell area, avoiding the consumption of LOCOS by the subsequent wet etching of the voltage-resistant dielectric layer 215, and realizing that under the premise of the last gate oxide process, the preparation of LOCOS can be controlled before the diffusion of the well area 202, which not only effectively avoids the "boron absorption and phosphorus discharge" effect of LOCOS, but also solves the leakage problem that affects the life of the device, and improves the reliability and electrical characteristics of the device. At the same time, LOCOS and the terminal area voltage-resistant dielectric layer 215 are prepared in steps, and the thickness of LOCOS can be adjusted by process separately, which is controlled at 0.2-0.3μm, breaking through the size limitation of LOCOS in the traditional last gate oxide process, and maximally improving the reliability and electrical characteristics of the device.

[0083] In the above description, the technical details of patterning and etching of each layer are not described in detail. However, those skilled in the art should understand that various technical means can be used to form layers, regions, etc. of desired shapes. In addition, in order to form the same structure, those skilled in the art can also design methods that are not completely the same as the methods described above.

[0084] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A VDMOS semiconductor power device, characterized in that: include A semiconductor substrate (200); Semiconductor epitaxial layer (201); A well region (202), the well region (202) being located inside the semiconductor epitaxial layer (201); A source region (203), the source region (203) being located inside the well region (202); A local thick oxygen layer (210), the local thick oxygen layer (210) being located below the gate (205) between adjacent well regions (202) on the semiconductor epitaxial layer (201); A gate dielectric layer (204), the gate dielectric layer (204) being located below the gate electrode (205) between adjacent source regions (203) on the semiconductor epitaxial layer (201); A gate (205), the gate (205) being located above the gate dielectric layer (204) and the local thick oxygen layer (210); The local thick oxygen layer (210) is formed before the well region (202) is diffused.

2. The VDMOS semiconductor power device according to claim 1, characterized in that: The thickness of the local thick oxygen layer (210) is 0.2-0.3 μm.

3. The VDMOS semiconductor power device according to claim 1, characterized in that: It also includes a source and a drain, wherein the source is located above the gate (205) and is in contact with both the source region (203) and the well region (202); and the drain is located below the semiconductor substrate (200).

4. The VDMOS semiconductor power device according to claim 1, characterized in that: It also includes an isolation dielectric layer (206) and a passivation layer (208), wherein the isolation dielectric layer (206) is located between the gate (205) and the source, and the passivation layer (208) is located on the surface of the source.

5. The VDMOS semiconductor power device according to claim 1, characterized in that: The semiconductor epitaxial layer (201) and the source region (203) are N-type doped, and the well region (202) is P-type doped; Or the semiconductor epitaxial layer (201) and the source region (203) are P-type doped, and the well region (202) is N-type doped.

6. A method for preparing a VDMOS semiconductor power device, characterized in that: The following steps are involved: S101, growing a first pad oxide layer (211) above the semiconductor epitaxial layer (201), and depositing a first hard mask layer (212); S102, etching the first hard mask layer (212) to form a window for growing a local thick oxygen layer (210) on the first hard mask layer (212); S103, using a thermal oxidation growth process to grow a local thick oxide layer (210), and removing the first hard mask layer (212) and the first pad oxide layer (211); S104, using ion implantation and high temperature diffusion processes to sequentially form a well region (202) and a source region (203); S105, growing a second pad oxide layer (213) above the well region (202), the source region (203) and the local thick oxide layer (210), and depositing a second hard mask layer (214); S106, etching the second hard mask layer (214) to form a window in the terminal region, and removing the second pad oxide layer (213) in the position of the window in the terminal region; S107, depositing a pressure-resistant dielectric layer (215), and selectively etching the pressure-resistant dielectric layer (215); S108, removing the remaining second hard mask layer (214) and the second pad oxide layer (213); S109, growing a gate dielectric layer (204), and sequentially forming a gate (205), a source electrode, and a drain electrode.

7. The preparation method according to claim 6, characterized in that: When preparing the well region (202) and the source region (203), impurity ions are injected into the semiconductor epitaxial layer (201), and high-temperature diffusion is performed to form the well region (202) and the source region (203).

8. The preparation method according to claim 6, characterized in that: When preparing the gate (205), polysilicon is deposited on the surface of the gate dielectric layer (204) and selective anisotropic etching is performed to form the gate (205).

9. The preparation method according to claim 6, characterized in that: When preparing the source electrode, an isolation dielectric layer (206) is deposited on the gate electrode (205) and selectively wet-etched, and a front metal layer (207) is deposited on the isolation dielectric layer (206) and selectively etched to form the source electrode.

10. The preparation method according to claim 6, characterized in that: When preparing the drain electrode, a back metal layer (209) is prepared below the semiconductor substrate (200) to form the drain electrode.

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