Integrated circuit winding optimization method and device, electronic equipment and storage medium

Abstract

The invention provides an integrated circuit winding optimization method and device, electronic equipment and a storage medium, and belongs to the technical field of integrated circuits. The method comprises the following steps: acquiring time sequence path index threshold information and winding index threshold information; performing static time sequence analysis on the wound integrated circuit to obtain static time sequence information; determining key path information according to the static time sequence information and time sequence path index threshold information; determining a driving position of the interconnection line to be optimized according to the key path information and the winding index threshold information; the winding attribute corresponding to the driving position of the to-be-optimized interconnection line is reset to be the through hole column winding attribute, so that parasitic parameters of the interconnection line in key path information can be reduced, the part with large delay of the interconnection line is effectively reduced, the proportion of the delay of the interconnection line to the delay of the whole circuit is reduced accordingly, the time sequence requirement can be met, and the optimization efficiency of the interconnection line is improved. The area and the number of the driving units are saved, and the power consumption, the performance and the area of the integrated circuit can be more accurately optimized.

Description

Technical Field

[0001] The present application belongs to the field of integrated circuit technology, and in particular, relates to an integrated circuit winding optimization method, device, electronic device and storage medium. Background Art

[0002] Integrated Circuit (IC) is a microelectronic device or component. Through a series of complex processes, integrated circuits integrate electronic components such as transistors, resistors, capacitors, inductors, and the wiring between them to form a circuit with specific functions. Among them, integrated circuit winding refers to the process of laying out and planning the metal wires connecting various electronic components (such as transistors, resistors, capacitors, etc.) during the design and manufacturing of integrated circuits.

[0003] As the process size of advanced processes shrinks, the width of the interconnection lines between various logic units in the integrated circuit decreases, which in turn causes the parasitic parameters of each interconnection line to increase, making the proportion of the interconnection line delay in the overall circuit delay increasingly higher, thereby affecting the power consumption, performance and area of ​​the integrated circuit. Summary of the invention

[0004] The purpose of the present application is to provide an integrated circuit routing optimization method, device, electronic device and storage medium, aiming to solve the problem of high interconnect delay ratio existing in traditional methods.

[0005] The present application provides an integrated circuit winding optimization method, comprising:

[0006] Obtaining timing path indicator threshold information and winding indicator threshold information;

[0007] Perform static timing analysis on the wound integrated circuit to obtain static timing information;

[0008] Determining critical path information according to the static timing information and the timing path indicator threshold information;

[0009] Determining a driving position of an interconnection line to be optimized according to the critical path information and the winding index threshold information;

[0010] The winding attributes corresponding to the driving position of the interconnect line to be optimized are reset to the through-hole column winding attributes.

[0011] The present application provides an integrated circuit winding optimization device, comprising:

[0012] A threshold information acquisition module, used to acquire timing path indicator threshold information and winding indicator threshold information;

[0013] A timing analysis module is used to perform static timing analysis on the integrated circuit after winding to obtain static timing information;

[0014] A critical path determination module, used to determine critical path information according to the static timing information and the timing path indicator threshold information;

[0015] An optimization position determination module, used to determine a driving position of an interconnection line to be optimized according to the critical path information and the winding index threshold information;

[0016] The winding attribute resetting module is used to reset the winding attributes corresponding to the driving position of the interconnection line to be optimized to the through-hole column winding attributes.

[0017] The present application provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps of the method described in any one of the above embodiments when executing the computer program.

[0018] The present application provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the method described in any one of the above embodiments are implemented.

[0019] Compared with the prior art, the embodiments of the present invention have the following beneficial effects:

[0020] Through the integrated circuit winding optimization method provided by the present application, based on the information after the static timing analysis of the integrated circuit after winding, the timing path indicator threshold information is used as the screening basis to screen out the critical path information with large delay, so as to optimize the critical path with large delay. Based on the critical path information, the winding indicator threshold information is used as the screening basis to screen out the position of the interconnection line with large delay in the critical path information, and then determine the driving position of the interconnection line to be optimized. The winding properties corresponding to the driving position of the interconnection line to be optimized are reset to the through-hole column winding properties, and the original winding is replaced with the through-hole column winding.

[0021] For long-distance interconnects, viapillar winding is used to connect different layers of metal wiring, which can greatly reduce the parasitic resistance and parasitic capacitance of long-distance interconnects and reduce line delay. Compared with the stacked via winding of traditional technology in advanced process, the present application is equivalent to connecting multiple metal wires in parallel in the same layer of metal by setting via pillar winding (also known as winding with viapillar) at the driving position of different interconnects to be optimized in the same layer of metal, which can effectively reduce coupling capacitance, parasitic capacitance and resistance value, so that the parasitic parameters of the interconnect are reduced. The parasitic parameters of the interconnect are reduced, which can reduce the delay of the interconnect in the critical path information, so that the excessive delay of the interconnect in the critical path information is effectively reduced. Thus, the delay of the interconnect in the critical path information is reduced, which can reduce the proportion of the interconnect delay in the overall circuit delay, which helps to meet the timing requirements, can provide more space for the circuit structure optimization of the integrated circuit, save the area size and number of the driving unit, and can more accurately optimize the power consumption, performance and area of ​​the integrated circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 A schematic diagram of the steps of an integrated circuit wiring optimization method in an embodiment provided in the present application;

[0023] Figure 2 A schematic diagram of the steps of an integrated circuit wiring optimization method in an embodiment provided in the present application;

[0024] Figure 3 A schematic flow chart of the determination steps of line delay in one embodiment provided by the present application;

[0025] Figure 4 A schematic diagram of a flow chart of the steps for determining line load in an embodiment provided by the present application;

[0026] Figure 5 A schematic diagram of a flow chart of the steps for determining the line length in an embodiment provided by the present application;

[0027] Figure 6 A schematic flow chart of the determination steps of line delay, line load and line length in one embodiment provided by the present application;

[0028] Figure 7 A schematic diagram of the steps of an integrated circuit wiring optimization method in an embodiment provided in the present application;

[0029] Figure 8 It is a schematic diagram of a timing path of a module in an integrated circuit after winding in an embodiment provided by the present application;

[0030] Fig. 9is a schematic structural diagram of an integrated circuit winding optimization device in an embodiment provided by the present application;

[0031] Fig.10 It is a schematic diagram of the structure of an electronic device in an embodiment provided by the present application. DETAILED DESCRIPTION

[0032] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0033] It should be noted that when an element is referred to as being "fixed to" or "disposed on" another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element.

[0034] It should be understood that the orientation or position relationship indicated by terms such as "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside" and "outside" are based on the orientation or position relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0035] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0036] See also Figure 1 , the present application provides an integrated circuit winding optimization method, comprising:

[0037] Step S10, obtaining timing path index threshold information and winding index threshold information;

[0038] Step S20, performing static timing analysis on the wound integrated circuit to obtain static timing information;

[0039] Step S30, determining critical path information according to static timing information and timing path indicator threshold information;

[0040] Step S40, determining the driving position of the interconnection line to be optimized according to the critical path information and the winding index threshold information;

[0041] Step S50, resetting the winding attributes corresponding to the driving position of the interconnection line to be optimized to the through-hole column winding attributes.

[0042] In this embodiment, in step S10, the timing path indicator threshold information can be understood as an indicator threshold related to the timing path in the integrated circuit. The timing path indicator threshold information can include threshold information such as the establishment time margin threshold and the retention time margin threshold that can characterize the timing path. The winding indicator threshold information can be understood as an indicator threshold related to the interconnection line in the integrated circuit. The winding indicator threshold information includes the line delay threshold, the line load threshold, the line length threshold, etc., which can characterize the threshold information related to the interconnection line. The timing path indicator threshold information and the winding indicator threshold information can be different according to the process node, power supply voltage and design density in the actual application scenario, and the specific value can be adjusted according to the actual application scenario.

[0043] In step S20, static timing analysis (STA) is a process of determining whether the timing requirements are met by analyzing the delays and timing constraints of each timing path in the integrated circuit. Static timing information can be understood as the static timing analysis result formed after static timing analysis is performed on the wound integrated circuit.

[0044] Static timing information includes the delay time of each timing path, the starting point and end point of each timing path, the type of each timing path, setup time violation, hold time violation, clock cycle violation, setup time margin, hold time margin, clock cycle time margin, input and output delays, line load, line delay, line length, and timing report summary, etc., which can characterize the integrated circuit.

[0045] The timing path can be understood as the signal propagation path that the signal passes through from the clock edge of one component in the integrated circuit to the clock edge of another component. The starting point of the timing path can be a clock source, an input port, or the output of a storage element (such as a register). The end point of the timing path can be the input end, output port, or another clock source of a storage element. The timing path includes a series of logic units (such as AND gates, OR gates, NOT gates, etc.) and interconnects. The signal performs logical operations in the logic unit and propagates in the interconnect. The delay of the logic unit and the interconnect jointly determines the total delay of the timing path.

[0046] In step S30, the static timing information includes multiple timing paths, each of which has corresponding path parameters, such as setup time margin, hold time margin, clock cycle time margin and other information. The critical path information can be understood as the information corresponding to the timing path with long delay time that the signal passes through during the transmission process, starting from the clock edge of one component to the clock edge of another component. Based on the timing path indicator threshold information as the screening basis, the timing path information with long delay time is screened out in the static timing information as the critical path information. Then, the routing optimization is performed for the critical path with long delay.

[0047] In step S40, each critical path includes a plurality of interconnects. The interconnect is a part of the critical path and can be understood as a signal transmission link. The winding index threshold information is used as the screening basis, and the line characteristic values ​​of each interconnect in the critical path information are compared with the winding index threshold respectively, and the interconnects that need to be optimized are screened out, and the driving ports of the interconnects to be optimized are obtained, and then the driving positions of the interconnects to be optimized are determined. The driving positions of the interconnects can be understood as the positions corresponding to the driving ports of the interconnects during the signal transmission process, and can also be understood as the ports that provide signal drive to the interconnects. In one embodiment, when the buffer buffer1 outputs the signal to the interconnect, and transmits it to the buffer buffer2 for reception through the interconnect, if the interconnect between the buffer buffer1 and the buffer buffer2 is the interconnect to be optimized, then the output port of the buffer buffer1 is the driving port of the interconnect to be optimized, that is, the driving position of the interconnect to be optimized.

[0048] Through the timing path indicator threshold information and the routing indicator threshold information, the interconnect lines that need to be optimized are screened in the static timing information and the critical path information respectively. From the physical routing design level of the signal line network, the line network load formed by the interconnect lines in the critical path information can be reduced, which can save more area and power consumption, thereby more effectively improving the power consumption, performance and area of ​​the integrated circuit without over-design.

[0049] In step S50, after obtaining the driving position of the interconnection line to be optimized, the original winding properties at the driving position of the interconnection line to be optimized are deleted and reset to viapillar winding. A viapillar is a vertical conductive structure for connecting different layers of metal wiring, which can play a role in conducting current and transmitting signals in a multi-layer integrated circuit. For long-distance interconnections, using viapillar winding to connect different layers of metal wiring can greatly reduce the parasitic resistance and parasitic capacitance of long-distance interconnections and reduce line delay.

[0050] In the traditional stacked via wiring in advanced process, there is only a single via and current path for each metal layer, which leads to a large impedance problem. Compared with the traditional stacked via wiring in advanced process, the via pillar wiring (also understood as a wiring with a viapillar) provided in the present application is arranged at the driving position of the interconnection line to be optimized, which can increase the number of vias, increase the current path, reduce the resistance and capacitance of the signal during transmission, and reduce signal delay and power consumption.

[0051] The present application sets via pillar windings (which can also be understood as windings with viapillars) at different driving positions of interconnects to be optimized in the same layer of metal, which is equivalent to connecting multiple metal wires in parallel in the same layer of metal, which can effectively reduce coupling capacitance, parasitic capacitance and resistance, reduce parasitic parameters of interconnects, and further effectively reduce the delay of interconnects, thereby reducing the voltage drop and power loss of signals during transmission. The reduced delay of interconnects allows integrated circuits to integrate fewer large drive units and low threshold units, and can more accurately optimize the power consumption (Power), performance (Performance) and area (Area) of integrated circuits.

[0052] Therefore, through the integrated circuit winding optimization method provided by the present application, based on the information after the static timing analysis of the integrated circuit after winding, the timing path index threshold information is used as the screening basis to screen out the critical path information with large delay, so as to optimize the critical path with large delay. Based on the critical path information, the winding index threshold information is used as the screening basis to screen out the position where the interconnection delay is large in the critical path information, and then determine the driving position of the interconnection to be optimized. The winding properties corresponding to the driving position of the interconnection to be optimized are reset to the through-hole column winding properties, and the original winding is replaced by the through-hole column winding, which reduces the parasitic parameters of the interconnection, and then can reduce the delay of the interconnection in the critical path information, so that the part of the interconnection delay that is too large in the critical path information is effectively reduced. Thus, the delay of the interconnection in the critical path information is reduced, and the proportion of the interconnection delay in the overall circuit delay can also be reduced, which helps to meet the timing requirements, can provide more space for the circuit structure optimization of the integrated circuit, save the area size and number of the driving unit, and can more accurately optimize the power consumption, performance and area of ​​the integrated circuit.

[0053] See also Figure 2 In one embodiment, step S10, the step of obtaining timing path indicator threshold information and winding indicator threshold information, includes:

[0054] Step S110, obtaining process node, power supply voltage and design density;

[0055] Step S120 , based on the adaptive threshold setting mechanism, determining the timing path index threshold information and the winding index threshold information according to the process node, the power supply voltage and the design density.

[0056] In this embodiment, the process node is a symbol of the technical level used in the integrated circuit manufacturing process, indicating the minimum size of semiconductor devices such as transistors. The power supply voltage is the voltage value that provides power to the integrated circuit. The power supply voltage is provided by an external power supply and distributed to each circuit module through the power supply network on the integrated circuit. The design density is the number of logic gates or transistors that can be realized per unit area on the integrated circuit, reflecting the degree of integration of the integrated circuit at the design level. The process node, power supply voltage and design density influence each other and determine the performance, power consumption and area of ​​the integrated circuit. In the design of integrated circuits, the reasonable selection of process nodes, power supply voltage and design density can more accurately optimize the power consumption, performance and area of ​​the integrated circuit.

[0057] Process nodes, power supply voltage and design density are design parameters of integrated circuits and can be set according to actual application scenarios. The adaptive threshold setting mechanism can adopt a statistical method or a machine learning method. Through the adaptive threshold setting mechanism, the relationship between process nodes, power supply voltage, design density, timing path indicator threshold information, and winding indicator threshold information is established. Process nodes, power supply voltage and design density serve as input parameters of the adaptive threshold setting mechanism. Timing path indicator threshold information and winding indicator threshold information serve as output parameters of the adaptive threshold setting mechanism. The adaptive threshold setting mechanism performs adaptive adjustments according to different application scenarios of process nodes, power supply voltages and design densities to obtain timing path indicator threshold information and winding indicator threshold information.

[0058] Through the adaptive threshold setting mechanism, parameters such as process nodes, power supply voltage, and design density are input to generate adaptive thresholds, and then the timing path indicator threshold information and the winding indicator threshold information are determined. Through the adaptive threshold setting mechanism, it is possible to adapt to the dynamic changes of process nodes, power supply voltage, and design density, so that the corresponding timing path indicator threshold information and winding indicator threshold information are also dynamically adjusted. Therefore, through the adaptive threshold setting mechanism, the characteristics and change trends of the data can be automatically learned, and the threshold can be adjusted without manual intervention. It can be applied to different input parameters, which improves the accuracy and reliability of the timing path indicator threshold information and the winding indicator threshold information.

[0059] In one embodiment, step S120, based on the adaptive threshold setting mechanism, determines the timing path index threshold information and the winding index threshold information according to the process node, the power supply voltage and the design density, including:

[0060] Step a, using the power consumption, performance and area of ​​the integrated circuit as the reward mechanism, based on the machine reinforcement learning algorithm, according to the process node, power supply voltage and design density, determine the timing path indicator threshold information and the winding indicator threshold information.

[0061] In this embodiment, the machine reinforcement learning algorithm may be a Q-learning algorithm, a policy gradient algorithm, a deep Q network algorithm (Deep Q Network, DQN) or a dynamic programming algorithm (Dynamic Programming), etc. The power consumption (Power), performance (Performance) and area (Area) of the integrated circuit are used as the reward mechanism. Power consumption, performance and area are key indicators for evaluating the quality of integrated circuit design. By using the power consumption, performance and area of ​​the integrated circuit as the reward mechanism, trade-offs and optimizations can be made between the three indicators to meet the design requirements. Using the degree of improvement in power consumption, performance and area as the reward mechanism, the timing path indicator threshold and the winding indicator threshold are dynamically adjusted during the design process through the reinforcement learning algorithm in machine learning. The threshold for achieving the best power consumption, performance and area (ie, PPA) optimization effect is used as the threshold output by the machine reinforcement learning algorithm, that is, the timing path indicator threshold information and the winding indicator threshold information. For different process nodes, power supply voltages, and design densities, the machine reinforcement learning algorithm can adapt to the dynamic changes of different design requirements, dynamically adjust the adaptive threshold in a timely manner, obtain the timing path indicator threshold information and the winding indicator threshold information, and more accurately optimize the power consumption, performance, and area of ​​the integrated circuit. Therefore, based on the timing path indicator threshold information and the winding indicator threshold information, it is determined whether to reset the winding properties of the interconnect to be optimized to the through-hole column winding properties, which can optimize the winding of the integrated circuit and reduce the proportion of interconnect delay in the integrated circuit.

[0062] In one embodiment, step S20, performing static timing analysis on the wound integrated circuit, and obtaining static timing information includes:

[0063] Step S210, extracting parasitic parameters of the integrated circuit after winding;

[0064] Step S220 , based on the parasitic parameters, a static timing analysis tool is used to perform a static timing analysis on the wound integrated circuit to obtain static timing information.

[0065] In this embodiment, parasitic parameters can be understood as some electrical parameters that are not intentionally added or designed by the designer in the integrated circuit, but are inevitably present due to the physical structure and manufacturing process of the integrated circuit. Parasitic parameters include parasitic capacitance, parasitic resistance, parasitic inductance, etc. The various logic units in the integrated circuit are connected by interconnection lines. The interconnection lines are made of conductive materials, such as metal, which will produce parasitic parameters (such as line resistance, line capacitance, line inductance, etc.). The line resistance, line capacitance, and line inductance of the interconnection lines form the line load of the interconnection lines, which will affect the signal transmission and circuit performance of the integrated circuit.

[0066] In step S210, parasitic parameters are extracted from the integrated circuit after winding, and the parasitic parameters can be incorporated into the static timing analysis, so that the performance of the integrated circuit can be analyzed more accurately, and more accurate static timing analysis results, i.e., static timing information, can be obtained. In one embodiment, parasitic parameter extraction tools such as Cadence's Assura and Synopsys's StarRC can be used to automatically extract parasitic parameters from the circuit layout and generate corresponding parasitic parameter files for circuit simulation and analysis. In step S220, the static timing analysis tool can be a static timing analysis tool such as PrimeTime, Design Compiler, TimeQuest, etc., which performs static timing analysis on the integrated circuit after winding.

[0067] In one embodiment, step S30, the step of determining critical path information according to static timing information and timing path indicator threshold information, includes:

[0068] Step S310, traversing each setup time violation path in the static timing information;

[0069] Step S320, determining whether the absolute value of the setup time margin of the current setup time violation path is greater than the setup time margin threshold in the timing path indicator threshold information;

[0070] Step S330: If yes, the current setup time violation path is determined as critical path information;

[0071] Step S340: If not, skip the current setup time violation path and continue to execute step S310 to traverse each setup time violation path in the static timing information.

[0072] In this embodiment, in the integrated circuit, the static timing information is the static timing analysis result formed after the integrated circuit after the wiring is subjected to static timing analysis. The static timing information includes the delay time of each timing path, the starting point and end point of each timing path, the type of each timing path, the setup time violation path, the hold time violation path, the clock cycle violation path, the setup time margin path, the hold time timing margin, the clock cycle timing margin, the input and output delays, and the timing report summary. The setup time violation path existing in the timing path and the corresponding setup time margin form the setup time violation path in step S310.

[0073] The setup time violation path can be understood as a setup time violation path that occurs when there is not enough time to stabilize before the effective edge of the clock signal arrives, or it can be understood as a timing violation path. In one embodiment, a register requires data to be stable 500ps before the rising edge of the clock arrives, but the actual data is stable at 450ps, then a setup time violation path occurs. The setup time violation path will cause the data to be unable to be correctly sampled and stored, thereby affecting the function of the integrated circuit.

[0074] The setup time margin can be understood as the amount of time left after the data meets the setup time requirement. If the setup time margin is a positive value, it indicates that the data has enough time to stabilize, and the integrated circuit is safe and reliable in terms of setup time. If the setup time margin is a negative value, it indicates that there is a corresponding setup time violation path. Furthermore, the setup time margin corresponding to the setup time violation path is a negative value. In one embodiment, if the setup time requirement of a timing path is 500ps and the actual data stabilization time is 550ps, the setup time margin is 50ps, which is a positive value. In one embodiment, if the setup time requirement of a timing path is 500ps and the actual data stabilization time is 450ps, the setup time margin is -50ps, which is a negative value. The setup time margin can be used to evaluate the reliability of the integrated circuit in terms of setup time and determine whether optimization is needed.

[0075] Since the setup time margin corresponding to the setup time violation path is a negative value, when searching for each setup time violation path in the static timing information, it is determined whether the absolute value of the setup time margin corresponding to the setup time violation path is greater than the setup time margin threshold. In this embodiment, the setup time margin threshold is set to a positive value, which can be obtained by the method provided in step a. Based on the setup time margin threshold, multiple setup time violation paths in the static timing information are screened. In the case where the absolute value of the setup time margin of the current setup time violation path is greater than the setup time margin threshold, the current setup time violation path is used as the critical path information. In the case where the absolute value of the setup time margin of the current setup time violation path is less than or equal to the setup time margin threshold, the current setup time violation path is skipped, and the subsequent step S40 is not performed, but step S310 is continued to be performed to determine the next setup time violation path until the traversal of multiple setup time violation paths in the static timing information is completed.

[0076] The setting of the establishment time margin threshold in the timing path indicator threshold information provided in step a can more accurately optimize the power consumption, performance and area of ​​the integrated circuit. Taking the establishment time margin threshold as the screening basis, through steps S310 to S340, each establishment time violation path in the static timing information is traversed, and the critical path information is screened out as the timing path that needs to be further optimized. Therefore, through steps S310 to S340, the establishment time margin threshold is used as the screening basis, and the critical path information can be screened out from the static timing information, and the timing path information that needs to be optimized can be accurately determined, reducing the time for routing optimization.

[0077] In one embodiment, step S40, the step of determining the driving position of the interconnection line to be optimized according to the critical path information and the winding index threshold information, includes:

[0078] Step S410, traversing each interconnection line in the critical path information;

[0079] Step S420, determining whether the line characteristic value of the current interconnection line is greater than the line threshold in the winding index threshold information;

[0080] Step S430: If yes, the driving position corresponding to the current interconnection line is determined as the driving position of the interconnection line to be optimized;

[0081] Step S440: If not, skip the current interconnection line and continue to execute step S410, traversing the steps of each interconnection line in the critical path information.

[0082] In this embodiment, each critical path includes multiple interconnects. The interconnect is a part of the critical path and can be understood as a signal transmission link. An interconnect corresponds to a timing arc. It can also be understood that each critical path includes multiple timing arcs. The interconnect will form line characteristic values ​​such as line load, line delay, and line length, which will affect the delay of the interconnect. The line threshold in the winding index threshold information can be obtained by the method provided in step a. The line threshold can be a line load threshold, a line delay threshold, or a line length threshold, which can characterize the characteristics of the interconnect.

[0083] Based on the line threshold, multiple interconnects in the critical path are screened. When the line characteristic value of the current interconnect is greater than the line threshold, the line driving position of the current interconnect is used as the driving position of the interconnect to be optimized. When the line characteristic value corresponding to the current interconnect is less than or equal to the line threshold, the current interconnect is skipped, and the subsequent step S50 is not performed, but step S410 is continued to be performed to judge the next interconnect until the traversal of multiple interconnects in the critical path is completed. In this embodiment, the driving position of the interconnect to be optimized can also be understood as the driving port of the interconnect to be optimized.

[0084] The setting of the line threshold in the winding index threshold information provided in step a can more accurately optimize the power consumption, performance and area of ​​the integrated circuit. Taking the line threshold as the screening basis, through steps S410 to S440, traverse each interconnection in the critical path, and screen out the line drive position as the driving position of the interconnection to be optimized. Thus, through steps S410 to S440, the driving position of the interconnection to be optimized can be screened out from the critical path with the line threshold as the screening basis, and the driving position of the winding that needs to be optimized can be accurately determined, which can reduce the time of winding optimization and improve the accuracy and optimization efficiency of winding optimization. After determining the driving position of the interconnection to be optimized, step S50 is executed to reset the winding attribute corresponding to the driving position of the interconnection to be optimized to the through-hole column winding attribute. Therefore, after the time margin threshold and the line threshold are established in steps S310 to S340 and steps S410 to S440, the screened interconnection is used as a line that needs to be optimized by a through-hole column (viapillar). Thus, the winding properties corresponding to the driving position of the interconnection line to be optimized are reset to the through-hole column winding properties, and rewinding is performed, so that the parasitic parameters generated by the interconnection line are reduced, thereby reducing the delay of the interconnection line, and more accurately optimizing the power consumption, performance and area of ​​the integrated circuit.

[0085] See also Figure 3 In one embodiment, step S420, the step of determining whether the line characteristic value of the current interconnection line is greater than the line threshold in the winding index threshold information, includes:

[0086] Step S421 , determining whether the line delay of the current interconnection line is greater than the line delay threshold in the winding index threshold information.

[0087] In this embodiment, the line characteristic values ​​include line load, line delay, line length, etc., which can characterize the characteristic information of the interconnection line. The line load includes line resistance, line capacitance, and line inductance. The line load can also be understood as a parasitic parameter generated by the interconnection line. The line delay threshold can be understood as a limit value set by the maximum delay time allowed for the transmission of the signal by the interconnection line (which can also be understood as the signal line) in the integrated circuit. The line delay threshold is obtained by the method provided in step a, which can more accurately optimize the power consumption, performance, and area of ​​the integrated circuit.

[0088] Based on the line delay threshold, if the line delay corresponding to the current interconnection line is greater than the line delay threshold, it indicates that the current interconnection line needs to be optimized, and step S430 is executed to determine the driving position corresponding to the current interconnection line as the driving position of the interconnection line to be optimized. If the line delay corresponding to the current interconnection line is less than or equal to the line delay threshold, it indicates that the current interconnection line does not need to be optimized, and then step S440 is executed to skip the current interconnection line and continue to perform the threshold judgment of the next interconnection line in the critical path information.

[0089] By determining the line delay threshold of the interconnection line in step S421, the interconnection line to be optimized can be accurately located in the critical path information, and then the driving position of the interconnection line to be optimized can be accurately found. Therefore, the winding properties corresponding to the driving position of the interconnection line to be optimized are reset to the through-hole column winding properties, and re-winding is performed to reduce the delay of the interconnection line, which can more accurately optimize the power consumption, performance and area of ​​the integrated circuit.

[0090] See also Figure 4 In one embodiment, step S420, the step of determining whether the line characteristic value of the current interconnection line is greater than the line threshold in the winding index threshold information, further includes:

[0091] Step S422, determining whether the current line load of the interconnection line is greater than the line load threshold in the winding index threshold information.

[0092] In this embodiment, the line load threshold can be understood as a limit value set by the maximum line load allowed for the interconnection line (also understood as the signal line) in the integrated circuit to transmit the signal. The line load threshold is obtained by the method provided in step a, which can more accurately optimize the power consumption, performance and area of ​​the integrated circuit.

[0093] Based on the line load threshold, if the line load corresponding to the current interconnection line is greater than the line load threshold, it indicates that the current interconnection line needs to be optimized, and step S430 is executed to determine the driving position corresponding to the current interconnection line as the driving position of the interconnection line to be optimized. If the line load corresponding to the current interconnection line is less than or equal to the line load threshold, it indicates that the current interconnection line does not need to be optimized, and then step S440 is executed to skip the current interconnection line and continue to perform the threshold judgment of the next interconnection line in the critical path information. By judging the line load threshold of the line load of the interconnection line in step S422, the interconnection line that needs to be optimized can be accurately located in the critical path information, and then the driving position of the interconnection line to be optimized can be accurately found. Thus, the winding properties corresponding to the driving position of the interconnection line to be optimized are reset to the through-hole column winding properties, and the winding is rewound to reduce the delay of the interconnection line, which can more accurately optimize the power consumption, performance and area of ​​the integrated circuit.

[0094] See also Figure 5 In one embodiment, step S420, the step of determining whether the line characteristic value of the current interconnection line is greater than the line threshold in the winding index threshold information, further includes:

[0095] Step S423, determining whether the current length of the interconnection line is greater than the line length threshold in the winding index threshold information.

[0096] In this embodiment, the line length can be understood as the winding length of the interconnection line, and can also be understood as the length of the interconnection line. In an integrated circuit, as the length of the interconnection line increases, the line resistance, line capacitance, and line inductance will also increase accordingly, which can also be understood as parasitic resistance, parasitic capacitance, and parasitic inductance will also increase accordingly. The line length of the interconnection line has an important influence on parasitic parameters (such as resistance, capacitance, and inductance), and thus it is necessary to reasonably control the length of the interconnection line to reduce the adverse effects of parasitic parameters on the performance of the integrated circuit. The line length and line load of the interconnection line will affect the line delay of the interconnection line. The line load and line length are interrelated and jointly affect the line delay. Increasing the line length will increase the line load, thereby further increasing the line delay.

[0097] The line length threshold can be understood as a limit value set by the maximum line length allowed for the transmission of signals by the interconnection line (which can also be understood as the signal line) in the integrated circuit. The line length threshold is obtained by the method provided in step a, which can more accurately optimize the power consumption, performance and area of ​​the integrated circuit. Based on the line length threshold, if the line length corresponding to the current interconnection line is greater than the line length threshold, it indicates that the current interconnection line needs to be optimized, and step S430 is executed to determine the driving position corresponding to the current interconnection line as the driving position of the interconnection line to be optimized. If the line length corresponding to the current interconnection line is less than or equal to the line length threshold, it indicates that the current interconnection line does not need to be optimized, and then step S440 is executed to skip the current interconnection line and continue to judge the threshold of the next interconnection line in the critical path information.

[0098] By determining the line length threshold of the interconnection line in step S423, the interconnection line to be optimized can be accurately located in the critical path information, and then the driving position of the interconnection line to be optimized can be accurately found. Thus, the winding properties corresponding to the driving position of the interconnection line to be optimized are reset to the through-hole column winding properties, and rewinding is performed to reduce the delay of the interconnection line, which can more accurately optimize the power consumption, performance and area of ​​the integrated circuit.

[0099] In one embodiment, in step S420, through step S421 or step S422 or step S423, it is possible to accurately locate the interconnection line that needs to be optimized in the critical path information, and then determine the driving position of the interconnection line to be optimized. In one embodiment, in step S420, through the continuous judgment of step S421 and step S422, or the continuous judgment of step S421 and step S423, or the continuous judgment of step S422 and step S423, it is also possible to accurately locate the interconnection line that needs to be optimized in the critical path information, and then determine the driving position of the interconnection line to be optimized.

[0100] See also Figure 6 In one embodiment, in step S420, through steps S421, S422 and S423, it is possible to accurately locate the interconnection line to be optimized in the critical path information, and then determine the driving position of the interconnection line to be optimized.

[0101] In this embodiment, in step S421, it is determined whether the line delay of the current interconnection line is greater than the line delay threshold in the winding index threshold information. If so, step S422 is executed. If not, step S440 is executed. In step S422, it is determined whether the line load of the current interconnection line is greater than the line load threshold in the winding index threshold information. If so, step S423 is executed. If not, step S440 is executed. In step S423, it is determined whether the line length of the current interconnection line is greater than the line length threshold in the winding index threshold information. If so, step S430 is executed. If not, step S440 is executed. Through the multi-layer threshold judgment of step S421, step S422 and step S423, the threshold judgment of the line delay, line load and line length of the interconnection line in the critical path information is realized in turn, and the interconnection line that needs to be optimized can be accurately located from multiple angles to avoid blind optimization. Therefore, through the multi-layer threshold judgment of step S421, step S422 and step S423, the optimization accuracy and optimization efficiency of the integrated circuit winding optimization method can be further improved.

[0102] Therefore, by performing line threshold judgment in one or more judgment steps of step S421, step S422 and step S423 in step S420 of the present application, the driving position of the interconnection line to be optimized can be determined, and then the interconnection line to be optimized can be accurately located in the critical path information, and the winding properties corresponding to the driving position of the interconnection line to be optimized can be reset to the through-hole column winding properties, and re-winding can be performed to reduce the delay of the interconnection line, so as to more accurately optimize the power consumption, performance and area of ​​the integrated circuit.

[0103] See also Figure 7 In one embodiment, after step S430, determining the driving position corresponding to the current interconnection line as the driving position of the interconnection line to be optimized, the method further includes:

[0104] Step S450, determining whether the winding density at the driving position of the interconnection line to be optimized is less than a winding density threshold;

[0105] If yes, then executing step S50, a step of resetting the winding properties corresponding to the driving position of the interconnect line to be optimized to the winding properties of the through-hole column;

[0106] If not, step S440 is executed to skip the current interconnection line, and step S410 is continued to traverse the steps of each interconnection line in the critical path information.

[0107] In this embodiment, the winding density can be understood as the length or number of metal interconnects per unit area in the integrated circuit, which reflects the compactness of the integrated circuit at the wiring level. The winding density can reflect whether the winding resources are sufficient or whether the winding area is tight. The design rules of the integrated circuit have restrictions on the winding density. In one embodiment, the winding density can be obtained by design tool analysis, physical measurement and observation, or theoretical calculation and model prediction. Too high a winding density will increase the delay of the interconnect, thereby affecting the performance of the integrated circuit. The winding density threshold can be understood as a limit value set by the maximum winding density allowed for the interconnect (also understood as the signal line) in the integrated circuit to transmit signals. Taking the winding density threshold as the judgment basis, if the winding density at the driving position of the interconnection to be optimized is less than the winding density threshold, it indicates that there are sufficient winding resources at the driving position of the interconnection to be optimized, and it also indicates that the winding area at the driving position of the interconnection to be optimized is not tight, and then the original winding can be deleted and the via pillar can be rewound at the driving position of the interconnection to be optimized, which can make more efficient use of the winding resources, reduce the delay of the interconnection, and more accurately optimize the power consumption, performance and area of ​​the integrated circuit.

[0108] Based on the winding density threshold, if the winding density at the driving position of the interconnection to be optimized is greater than the winding density threshold, it indicates that there are not enough winding resources at the driving position of the interconnection to be optimized, and it also indicates that the winding area at the driving position of the interconnection to be optimized is tight, so the current interconnection is skipped and the threshold judgment of the next interconnection in the critical path information is continued. By judging the winding density at the driving position of the interconnection to be optimized in step S450, it can be known whether the via pillar can be rewound at this position, so as to avoid the problem of increased delay of the interconnection caused by too high winding density.

[0109] In one embodiment, after step S50, resetting the winding properties corresponding to the driving position of the interconnect line to be optimized to the winding properties of the through-hole column, the integrated circuit winding optimization method further includes:

[0110] Step S60, rewinding the driving position of the interconnection line to be optimized according to the winding properties of the through-hole column to obtain the rewound integrated circuit, and executing steps S20 to S50 on the rewound integrated circuit, and looping in sequence until there are no interconnections that need to be optimized in the integrated circuit.

[0111] In this embodiment, through step S60, the original winding at the driving position of the interconnection line to be optimized is deleted, and the via pillar is rewound to obtain the rewound integrated circuit, that is, the rewound integrated circuit. The rewound integrated circuit can continue to be optimized for winding, and the timing iteration convergence can continue. The relevant optimization steps can refer to the relevant description in the above embodiment, which can more accurately optimize the power consumption, performance and area of ​​the integrated circuit.

[0112] In one embodiment, after the step S60 of rewinding the driving position of the interconnect line to be optimized according to the via pillar winding properties to obtain the rewound integrated circuit, the integrated circuit winding optimization method further comprises:

[0113] Step S70, according to the design rule check criteria, the integrated circuit after rewinding is checked and corrected. In this embodiment, the integrated circuit after the via pillar is rewound is checked and corrected by the winding design rule, and the interconnection lines after some forced winding optimization can be checked and corrected to avoid optimization errors, so that the power consumption, performance and area of ​​the integrated circuit can be optimized more accurately. In this embodiment, through step S70, the integrated circuit winding optimization method can be made without the judgment of the winding density in step S450 (which can also be understood as the judgment of whether the winding resources are sufficient, and can also be understood as the judgment of whether the winding area is tight) and directly rewinding the via pillar, and it can still ensure that the design of the integrated circuit after rewinding meets the manufacturing requirements, so that the power consumption, performance and area of ​​the integrated circuit can be optimized more accurately.

[0114] In one embodiment, the integrated circuit after rewinding is checked and corrected by the Design Rule Check (DRC), thereby ensuring that the design of the integrated circuit after rewinding meets the manufacturing requirements, so as to ensure that the integrated circuit can be correctly produced during the manufacturing process. The design rule check criteria are used to check whether the parameters such as the size of the transistor, the width and spacing of the metal wire, the size of the via hole, etc. in the integrated circuit after the via pillar is rewound meet the corresponding rules. The design rule check criteria can be used to discover and correct in advance. In one embodiment, the integrated circuit after rewinding is subjected to DRC inspection by the Electronic Design Automation (EDA) tool.

[0115] Therefore, by checking and correcting the rewound integrated circuit through step S70, when the winding resource priority is higher or when the performance timing priority is higher, after forcing the viapillar winding properties to be set for part of the winding, it can still be ensured that the design of the rewound integrated circuit meets the manufacturing requirements, thereby more accurately optimizing the power consumption, performance and area of ​​the integrated circuit. Thus, by checking and correcting the rewound integrated circuit through step S70, it can be ensured that in areas where the winding density is greater than the winding density threshold (which can also be understood as a winding tight area or an area where winding resources are insufficient) or areas where adding viapillars is prohibited, even if the viapillar winding properties are added, it will not affect the integrated circuit, further improving the optimization efficiency of the integrated circuit winding optimization method.

[0116] In one embodiment, after the step S20 of performing static timing analysis on the wound integrated circuit to obtain static timing information, the integrated circuit winding optimization method further includes:

[0117] Step S30', outside the forbidden adding area, execute step S30, and determine the critical path information according to the static timing information and the timing path indicator threshold information.

[0118] In this embodiment, the forbidden adding area can be understood as an area where congestion is more serious due to some areas with tight winding resources, or an area in the integrated circuit with relatively high winding requirements, such as a high-speed signal transmission area, a key logic module area, or an analog signal processing area. In the forbidden adding area, the area where the via pillar is added will have a problem of winding congestion. Therefore, through step S30', outside the forbidden adding area, the subsequent steps S30 to S50 are executed to ensure that the winding optimization of the area to be optimized can be more accurately performed without affecting the normal winding of the forbidden adding area, thereby more accurately optimizing the power consumption, performance and area of ​​the integrated circuit. In one embodiment, the forbidden adding area can be set according to the actual application scenario, and can be set before steps S30 to S50, further reducing the winding optimization area, improving the efficiency of the integrated circuit winding optimization, more accurately screening out the interconnects that need to be optimized, and reducing the delay of the interconnects in the critical path information.

[0119] See also Figure 8In one embodiment, the setup time margin threshold is 30ps, and in this embodiment, the setup time margin threshold is set to a positive value. The setup time margin corresponding to the setup time violation path is a negative value. Therefore, the absolute value of the setup time margin of the setup time violation path is compared with the setup time margin threshold. If the absolute value of the setup time margin of the setup time violation path is greater than 30ps, the setup time violation path is defined as a critical path. The line delay threshold is set to 80ps, and the line load threshold is set to 80pf.

[0120] In a module where both clock and data lines are routed, after parasitic parameter extraction, static timing analysis is performed. There is a set of synchronization registers in the synchronous clock domain CLKA. There is a setup time violation path from register FF1 to register FF2, and the absolute value of the setup time margin of the setup time violation path is greater than 30ps. The setup time violation path from register FF1 to register FF2 is defined as a critical path.

[0121] Start screening each interconnection line in the critical path to see if there is an interconnection line whose line delay is greater than the line delay threshold and whose line load is greater than the line load threshold. Among them, the line delay of interconnection line b is 100ps, which is greater than the line delay threshold of 80ps. And the line load of interconnection line b is 90pf, which is greater than the line load threshold of 80pf, then the interconnection line b can be optimized by the integrated circuit winding optimization method provided by the present application, and the winding properties corresponding to the driving position of interconnection line b are reset to the through-hole column winding properties. Among them, the driving position of interconnection line b can also be understood as a driving port, that is, the output port of buffer buffer1. Then, locate the physical position of the driving end of the output port of buffer buffer1, and obtain the winding density of the corresponding position. If the winding density is less than the winding density threshold, it means that the winding resources are sufficient, and the physical position of the driving end of the output port of buffer buffer1 can be set to the through-hole column (viapillar) winding mode, and delete the original ordinary winding, and re-wind the through-hole column (viapillar). If the winding density is greater than or equal to the winding density threshold, it indicates that the winding resources are insufficient, and the interconnection line b is skipped, and the next cycle is performed, and step S410 is continued. Therefore, through the integrated circuit wiring optimization method provided by the present application, the data path delay on the critical path can be accurately reduced, and the establishment time violation path can be effectively repaired, so that the delay of the interconnection line in the critical path is reduced, which helps to meet the timing requirements and can more accurately optimize the power consumption, performance and area of ​​the integrated circuit.

[0122] It should be understood that the size of the serial numbers of the steps in the above embodiments does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0123] See also Fig. 9 , the present application provides an integrated circuit winding optimization device 100. The integrated circuit winding optimization device 100 includes a threshold information acquisition module 10, a timing analysis module 20, a critical path determination module 30, an optimization position determination module 40 and a winding attribute reset module 50. The threshold information acquisition module 10 is used to obtain the timing path indicator threshold information and the winding indicator threshold information. The timing analysis module 20 is used to perform static timing analysis on the integrated circuit after winding to obtain static timing information. The critical path determination module 30 is used to determine the critical path information based on the static timing information and the timing path indicator threshold information. The optimization position determination module 40 is used to determine the driving position of the interconnection line to be optimized based on the critical path information and the winding indicator threshold information. The winding attribute reset module 50 is used to reset the winding attribute corresponding to the driving position of the interconnection line to be optimized to the through-hole column winding attribute.

[0124] In this embodiment, the description of the threshold information acquisition module 10 can refer to the description of step S10 in the above embodiment. The description of the timing analysis module 20 can refer to the description of step S20 in the above embodiment. The description of the critical path determination module 30 can refer to the description of step S30 in the above embodiment. The description of the optimized position determination module 40 can refer to the description of step S40 in the above embodiment. The description of the winding attribute reset module 50 can refer to the description of step S50 in the above embodiment.

[0125] See also Fig.10 The present application provides an electronic device 200, including a memory 210, a processor 220, and a computer program 230 stored in the memory and executable on the processor. When the processor 220 executes the computer program 230, the steps of the integrated circuit routing optimization method in any of the above-mentioned embodiments are implemented. In this embodiment, the electronic device 200 can be a computing device such as a desktop computer, a notebook, a PDA, and a cloud server. The electronic device 200 can include, but is not limited to, a processor 220 and a memory 210. Those skilled in the art can understand that Fig.10It is only an example of the electronic device 200 and does not constitute a limitation on the electronic device 200. It may include more or less components than shown in the figure, or combine certain components, or different components. The processor 220 may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc. The memory 210 may be an internal storage unit of the electronic device 200, or an external storage device of the electronic device 200, or may include both an internal storage unit of the electronic device 200 and an external storage device. The memory 210 is used to store the computer program 230 and other programs and data required by the electronic device 200. The memory 210 may also be used to temporarily store data that has been output or is to be output.

[0126] The present application provides a computer-readable storage medium, which stores a computer program 230. When the computer program 230 is executed by the processor 220, the steps of the integrated circuit winding optimization method in any of the above embodiments are implemented. Those skilled in the art can clearly understand that for the convenience and simplicity of description, only the division of the above-mentioned functional units and modules is used as an example. In practical applications, the above-mentioned function allocation can be completed by different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiments can be integrated in one processing unit, or each unit can exist physically separately, or two or more units can be integrated in one unit. The above-mentioned integrated unit can be implemented in the form of hardware or in the form of software functional units. In addition, the specific names of the functional units and modules are only for the convenience of distinguishing each other, and are not used to limit the scope of protection of the present application. The specific working process of the units and modules in the above-mentioned system can refer to the corresponding process in the above-mentioned method embodiment, which will not be repeated here. In the above embodiments, the description of each embodiment has its own emphasis. For the part that is not described or recorded in detail in a certain embodiment, please refer to the relevant description of other embodiments. Those of ordinary skill in the art can appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented with electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0127] In the embodiments provided in the present application, it should be understood that the disclosed devices / terminal equipment and methods can be implemented in other ways. For example, the device / terminal equipment embodiments described above are only schematic, for example, the division of the modules or units is only a logical function division, and there may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms. The units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the scheme of this embodiment.

[0128] In addition, each functional unit in each embodiment of the present application can be integrated into a processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The above-mentioned integrated unit can be implemented in the form of hardware or in the form of a software functional unit. If the integrated module / unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the present application implements all or part of the process in the above-mentioned embodiment method, and can also be completed by instructing the relevant hardware through a computer program. The computer program can be stored in a computer-readable storage medium, and the computer program can implement the steps of the above-mentioned various method embodiments when executed by the processor. Among them, the computer program includes computer program code, and the computer program code can be in source code form, object code form, executable file or some intermediate form, etc. The computer-readable medium may include: any entity or device capable of carrying the computer program code, recording medium, USB flash drive, mobile hard disk, magnetic disk, optical disk, computer memory, read-only memory (ROM), random access memory (RAM), electric carrier signal, telecommunication signal, and software distribution medium, etc. It should be noted that the content contained in the computer-readable medium may be appropriately increased or decreased according to the requirements of legislation and patent practice in the jurisdiction. For example, in some jurisdictions, according to legislation and patent practice, computer-readable media do not include electric carrier signals and telecommunication signals.

[0129] The embodiments described above are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, a person skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.

Claims

1. A method for optimizing integrated circuit winding, characterized in that: include: Obtaining timing path indicator threshold information and winding indicator threshold information; Perform static timing analysis on the wound integrated circuit to obtain static timing information; Determining critical path information according to the static timing information and the timing path indicator threshold information; Determining a driving position of an interconnection line to be optimized according to the critical path information and the winding index threshold information; The winding attributes corresponding to the driving position of the interconnect line to be optimized are reset to the through-hole column winding attributes.

2. The integrated circuit wiring optimization method according to claim 1, characterized in that: The step of obtaining the timing path indicator threshold information and the winding indicator threshold information includes: Obtain process node, supply voltage, and design density; Based on an adaptive threshold setting mechanism, the timing path indicator threshold information and the winding indicator threshold information are determined according to the process node, the power supply voltage and the design density.

3. The integrated circuit wiring optimization method according to claim 1, characterized in that: The step of determining the critical path information according to the static timing information and the timing path indicator threshold information comprises: Traversing each setup time violation path in the static timing information; If the absolute value of the setup time margin of the current setup time violation path is greater than the setup time margin threshold in the timing path indicator threshold information, the current setup time violation path is determined as the critical path information.

4. The integrated circuit wiring optimization method according to claim 1, characterized in that: The step of determining the driving position of the interconnection line to be optimized according to the critical path information and the winding index threshold information comprises: traversing each interconnection line in the critical path information; If the current line characteristic value of the interconnection line is greater than the line threshold in the winding index threshold information, the driving position corresponding to the current interconnection line is determined as the driving position of the interconnection line to be optimized.

5. The integrated circuit wiring optimization method according to claim 4, characterized in that: The step of determining the driving position corresponding to the current interconnection line as the driving position of the interconnection line to be optimized if the line characteristic value of the current interconnection line is greater than the line threshold in the winding index threshold information comprises: If the current line delay of the interconnection line is greater than the line delay threshold in the winding index threshold information, the driving position corresponding to the current interconnection line is determined as the driving position of the interconnection line to be optimized.

6. The integrated circuit wiring optimization method according to claim 4, characterized in that: The step of determining the driving position corresponding to the current interconnection line as the driving position of the interconnection line to be optimized if the line characteristic value of the current interconnection line is greater than the line threshold in the winding index threshold information further includes: If the current line load of the interconnection line is greater than the line load threshold in the winding index threshold information, the driving position corresponding to the current interconnection line is determined as the driving position of the interconnection line to be optimized.

7. The integrated circuit wiring optimization method according to claim 4, characterized in that: The step of determining the driving position corresponding to the current interconnection line as the driving position of the interconnection line to be optimized if the line characteristic value of the current interconnection line is greater than the line threshold in the winding index threshold information further includes: If the current line length of the interconnection line is greater than the line length threshold in the winding index threshold information, the driving position corresponding to the current interconnection line is determined as the driving position of the interconnection line to be optimized.

8. An integrated circuit winding optimization device, characterized in that: include: A threshold information acquisition module, used to acquire timing path indicator threshold information and winding indicator threshold information; A timing analysis module is used to perform static timing analysis on the integrated circuit after winding to obtain static timing information; A critical path determination module, used to determine critical path information according to the static timing information and the timing path indicator threshold information; An optimization position determination module, used to determine a driving position of an interconnection line to be optimized according to the critical path information and the winding index threshold information; The winding attribute resetting module is used to reset the winding attributes corresponding to the driving position of the interconnection line to be optimized to the through-hole column winding attributes.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 7 are implemented.

10. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 7 are implemented.

Images