Driving method of display panel and display device

Abstract

The invention discloses a driving method of a display panel and a display device. The driving method comprises the following steps: providing a partition enable signal to a partition enable signal line, so that a shift register outputs a scanning signal to a correspondingly connected pixel circuit according to the partition enable signal to control the refresh frequency of the correspondingly connected pixel circuit, thereby realizing a partition multi-frequency display mode; in at least one frame of the partition multi-frequency display mode, before a scanning signal output by a first shifting register corresponding to the second display partition is controlled to be a first conduction level, a driving signal corresponding to the driving mode of the second display partition is provided for a driving signal line. According to the embodiment of the invention, the phenomenon of uneven display can be improved, and the display effect is improved.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display panel driving method and a display device. Background Art

[0002] When using electronic products (such as mobile phones and tablets), split-screen display is used in many application scenarios, for example, users can watch videos while playing games or reading novels at the same time. In most cases, the frequencies required for the two split-screen display scenarios are different. For example, reading novels may only require 10Hz refresh or lower, watching videos requires 36Hz or 60Hz, and playing games requires 60Hz or higher. Currently, there is a problem of abnormal display near the dividing line when splitting the screen, which affects the display effect. Summary of the invention

[0003] The present invention provides a display panel driving method and a display device, which can improve the abnormal display phenomenon near the dividing line during split-screen display and enhance the display effect.

[0004] In a first aspect, the present invention provides a method for driving a display panel, wherein the display panel comprises at least two display partitions, wherein the at least two display partitions comprise a first display partition and a second display partition, wherein the first display partition and the second display partition are adjacent to each other along an extension direction of a data line, and each display partition comprises a plurality of pixel circuits, wherein the pixel circuits are electrically connected to the data line; the display panel further comprises a gate drive circuit and at least one partition enable signal line, wherein the gate drive circuit comprises a plurality of cascaded shift registers, wherein the shift registers are electrically connected to the partition enable signal lines correspondingly; the driving method comprises: providing a partition enable signal to the partition enable signal line, so that the shift register outputs a scanning signal to the correspondingly connected pixel circuit according to the partition enable signal, so as to control the refresh frequency of the correspondingly connected pixel circuit, thereby realizing a partition multi-frequency display mode; wherein at least one shift register The scanning signal output by the register includes a first conduction level; in at least one frame of the partitioned multi-frequency display mode, before the scanning signal output by the first shift register corresponding to the second display partition is controlled to be the first conduction level, a driving signal corresponding to the driving mode of the second display partition is provided to the driving signal line; wherein the driving signal line includes a partition enable signal line and / or a data line; wherein, in the partitioned multi-frequency display mode, the refresh frequency of the second display partition is greater than the refresh frequency of the first display partition; the first shift register corresponding to the second display partition is a shift register connected to the first row of pixel circuits in the second display partition; the pixel circuit is used to write a data signal on the data line according to the received first conduction level; wherein, in the driving mode of the second display partition, the level on the partition enable signal line is an enable level, and the data line transmits the data signal.

[0005] In a second aspect, an embodiment of the present invention provides a method for driving a display panel, wherein the display panel includes at least two display partitions, wherein the at least two display partitions include a first display partition and a second display partition, wherein the first display partition and the second display partition are adjacent to each other along an extension direction of a data line, and each display partition includes a plurality of pixel circuits, and the pixel circuits are electrically connected to the data line; the display panel also includes a gate drive circuit and at least one partition enable signal line, wherein the gate drive circuit includes a plurality of cascaded shift registers, and the shift registers are electrically connected to the partition enable signal lines correspondingly; the driving method includes: providing a partition enable signal to the partition enable signal line, so that the shift register outputs a scanning signal to the correspondingly connected pixel circuit according to the partition enable signal, so as to control the refresh frequency of the correspondingly connected pixel circuit, thereby realizing partition enable signal. The invention relates to a partition multi-frequency display mode; wherein the scanning signal output by at least one shift register includes a first conduction level of a partition enable signal; in at least one frame of the partition multi-frequency display mode, before controlling the scanning signal output by the first shift register corresponding to the second display partition to be the first conduction level, providing the first conduction level to the set partition enable signal line; wherein the set partition enable signal line is the partition enable signal line connected to the first shift register corresponding to the second display partition; wherein, in the partition multi-frequency display mode, the refresh frequency of the second display partition is greater than the refresh frequency of the first display partition; the first shift register corresponding to the second display partition is the shift register connected to the first row of pixel circuits in the second display partition; the pixel circuit is used to write the data signal on the data line according to the received first conduction level.

[0006] In a third aspect, an embodiment of the present invention provides a display device, including a display panel and a display driving module, wherein the display panel includes at least two display partitions, wherein the at least two display partitions include a first display partition and a second display partition, wherein the first display partition and the second display partition are adjacent to each other along the extension direction of the data line, and each display partition includes a plurality of pixel circuits, and the pixel circuits are electrically connected to the data line; the display panel also includes a gate driving circuit and at least one partition enable signal line, wherein the gate driving circuit includes a plurality of cascaded shift registers, wherein the shift registers are electrically connected to the partition enable signal line correspondingly, and the shift registers are used to control the refresh frequency of the correspondingly connected pixel circuit according to the partition enable signal of the partition enable signal line; the display driving module is used to provide a partition enable signal to the partition enable signal line, so that the shift register outputs a scanning signal to the correspondingly connected pixel circuit according to the partition enable signal, so as to control the refresh frequency of the correspondingly connected pixel circuit refresh frequency, thereby realizing a partitioned multi-frequency display mode; wherein, the scanning signal output by at least one shift register includes a first conduction level; within at least one frame of the partitioned multi-frequency display mode, before controlling the scanning signal output by the first shift register corresponding to the second display partition to be the first conduction level, providing a driving signal corresponding to the driving mode of the second display partition to the driving signal line; wherein the driving signal line includes a partition enable signal line and / or a data line; wherein, in the partitioned multi-frequency display mode, the refresh frequency of the second display partition is greater than the refresh frequency of the first display partition; the first shift register corresponding to the second display partition is a shift register connected to the first row of pixel circuits in the second display partition; the pixel circuit is used to write a data signal on the data line according to the received first conduction level; wherein, in the driving mode of the second display partition, the level on the partition enable signal line is an enable level, and the data line transmits the data signal.

[0007] The driving method of the display panel provided in an embodiment of the present invention provides a partition enable signal to the partition enable signal line so that the shift register outputs a scan signal to the correspondingly connected pixel circuit according to the partition enable signal to control the refresh frequency of the correspondingly connected pixel circuit, thereby realizing a partition multi-frequency display mode. By providing a driving signal corresponding to the refresh frequency of the second display partition to the driving signal line before controlling the scanning signal output by the first shift register corresponding to the second display partition to be the first conduction level within at least one frame of the partition multi-frequency display mode, the driving signal includes a partition enable signal on the partition enable signal line and / or a data signal on the data line, so that before the pixel circuit connected to the first shift register corresponding to the second display partition starts to write the data signal, the data signal connected to the pixel circuit is already in a state matching its own driving mode; and / or, before the scanning signal output by the first shift register of the second display partition is the first conduction level, the partition enable signal of the partition enable signal line connected to the first shift register of the second display partition is already in a state matching the driving mode of the second display partition, so that the process of the partition enable signal jumping from the off level to the first conduction level can be completed before the first shift register corresponding to the second display partition outputs the first conduction level of the scanning signal, so that when the first shift register corresponding to the second display partition outputs the first conduction level of the scanning signal, that is, when the pixel circuit starts to write data, the first conduction level has reached stability, so that the pixel circuit can write data normally. In this way, the pixel brightness switching in the boundary area between the second display partition and the first display partition can be smoother, which can improve the abnormal display phenomenon near the boundary line during split-screen display and enhance the display effect.

[0008] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0010] Figure 1 It is a schematic diagram of a scenario in which a split-screen display of a display panel has display abnormality at the dividing line;

[0011] Figure 2 yes Figure 1 Schematic diagram of voltage waveform of corresponding signal;

[0012] Figure 3 is a structural schematic diagram of a display device provided by an embodiment of the present invention;

[0013] Figure 4 is a schematic structural diagram of a display panel provided by an embodiment of the present invention;

[0014] Figure 5 is a flow chart of a method for driving a display panel provided by an embodiment of the present invention;

[0015] Figure 6 is a schematic diagram of another display panel driving method provided by an embodiment of the present invention;

[0016] Figure 7 is a schematic structural diagram of a gate driving circuit provided by an embodiment of the present invention;

[0017] Figure 8 is a structural schematic diagram of another display panel provided by an embodiment of the present invention;

[0018] Fig. 9 It is a schematic diagram of a partition enabling signal jump between a first display frame and a second display frame provided by an embodiment of the present invention;

[0019] Fig.10 is a flow chart of another display panel driving method provided by an embodiment of the present invention;

[0020] Fig.11 is a flow chart of another display panel driving method provided by an embodiment of the present invention;

[0021] Fig.12 is a flow chart of another display panel driving method provided by an embodiment of the present invention;

[0022] Fig.13 is a working timing diagram of a display panel provided by an embodiment of the present invention;

[0023] Fig.14 is a structural schematic diagram of a shift register provided by an embodiment of the present invention;

[0024] Fig.15 is a structural schematic diagram of a pixel circuit provided by an embodiment of the present invention;

[0025] Fig.16 It is a structural schematic diagram of another pixel circuit provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0026] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0027] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0028] As described in the background technology, the display panel in the related technology may have abnormal display problems near the dividing line when split-screen display is performed. For example, the display area is divided into a low refresh frequency area and a high refresh frequency area in the column direction. Bright lines may be generated near the boundary between the low refresh frequency area and the high refresh frequency area, affecting the display effect.

[0029] Based on the above technical problems, the inventors have discovered the causes of the above technical problems after long-term research. Figure 1 This is a schematic diagram of a scenario in which a split-screen display of a display panel has abnormal display at the dividing line. Figure 2 yes Figure 1 The voltage waveform diagram of the corresponding signal. Figure 1 and Figure 2 The causes leading to the above technical problems are explained.

[0030] like Figure 1 As shown, exemplarily, the display area of ​​the display panel is divided into a first display area AA1, a second display area AA2 and a third display area AA3 in the column direction. Exemplarily, the refresh frequency of the first display area AA1 and the third display area AA3 is 1 Hz, and the refresh frequency of the second display area AA2 is 120 Hz.

[0031] For a display panel capable of switching display frequency, the display frame of a sub-pixel can be divided into an active frame and an idle frame. In the active frame, the shift register provides an on-state potential to the pixel circuit, so that the data voltage is written into the pixel circuit; in the idle frame, the shift register provides an off-state potential to the pixel circuit, so that the pixel circuit no longer writes data.

[0032] The refresh rate can be understood as the number of refresh frames contained in a unit time. For example, the high frequency display may only include refresh frames. Figure 1 , assuming that at the refresh frequency f, the display frames of the second display partition AA2 only include refresh frames, and the refresh frequencies of the first display partition AA1 and the third display partition AA3 are lower than the refresh frequency of the second display partition AA2. Exemplarily, when f=60Hz, the second display partition AA2 refreshes 60 display frames within 1 second. The low-frequency refresh of the first display partition AA1 and the third display partition AA3 is implemented as follows: a hold frame is inserted between adjacent refresh frames of the second display partition AA2, and the total number of display frames contained in a unit time remains unchanged, and the display duration of each display frame remains unchanged. Exemplarily, when the refresh frequency of the first display partition AA1 and the third display partition AA3 is f / 2, 1 hold frame is inserted between every two adjacent refresh frames. When the refresh frequency of the first display partition AA1 and the third display partition AA3 is f / 3, 2 hold frames are inserted between every two adjacent refresh frames. By analogy, when the refresh frequency of the first display partition AA1 and the third display partition AA3 is f / (N+1), N hold frames are inserted between every two adjacent refresh frames.

[0033] The display device includes a display driving module and a display panel, wherein the display driving module includes a data driver and the display panel includes a pixel circuit. The function of the data driver is to transmit a data signal to the pixel circuit to realize the correct display of the pixel.

[0034] The load size of the data driver is related to the refresh frequency. The higher the refresh frequency, the greater the load of the data driver. Assume that there are two display partitions, the refresh frequency of partition A is 1Hz, and the refresh frequency of partition B is 60Hz. In partition A, due to the low refresh frequency, data only needs to be updated once per second, the voltage jump frequency of the data driver to transmit data is low, and the load is relatively small. In partition B, the refresh frequency is 60Hz, and data needs to be updated 60 times per second. The voltage jump frequency of the data driver to transmit data is much higher than that of partition A, so its load will be much larger than that of partition A.

[0035] In the partition multi-frequency display process of the display device, there are some display frames in which the sub-pixels in some display partitions do not perform data refresh, and the sub-pixels in other display partitions perform data refresh, that is, the display frame for partially refreshing the display panel, and such display frame is referred to as the first display frame. Exemplarily, in the first display frame, the sub-pixels in the first display partition AA1 do not perform data refresh, and the sub-pixels in the second display partition AA2 perform data refresh. Since in the first display frame, each sub-pixel in the second display partition AA2 needs to perform a data writing process to complete the data refresh. However, each sub-pixel in the first display partition AA1 performs data retention and does not need to refresh the data again. At this time, the load of the data line is small, and the data voltage transmitted on the data line is set to a high resistance state (High resistance state, Hiz) or a fixed voltage, which can effectively save energy consumption. That is to say, in the first display partition AA1, due to the low refresh frequency, the pixel circuit has a low update frequency for data, and the demand for electric energy is relatively small. The data driver does not need to frequently provide a large amount of electric energy, so it is in a light load state. When entering the high refresh area (i.e., the second display partition AA2), the load of the data driver changes. The refresh rate in the high refresh area is higher, and the pixel circuit needs to update data more frequently. For example, the high refresh area may update pixel data dozens or even hundreds of times per second, which requires the data driver to provide more power to meet the needs of data transmission and pixel refresh, so the data driver enters an overloaded state.

[0036] This transition from the light load state in the low refresh area to the heavy load state in the high refresh area will couple other drive signals or power signals. For example, when the voltage on the data line suddenly changes, the drive power signal will be coupled to change. The partition enable signal used to control the refresh frequency of the pixel circuit in the display panel is generated according to the drive power signal, so the partition enable signal will be affected. In this case, the degree of charging to the storage capacitor in the pixel circuit will be affected, eventually leading to display abnormality. Figure 2 As shown, for example, when the refresh frequency of the first display partition AA1 changes from 1Hz to the refresh frequency of the second display partition AA2, the data driver load changes, causing the first conduction level NVGH1 of the partition enable signal VFE to drop, and the level stability fluctuates, resulting in a difference in the charging of the pixels in the front part of the rows of the second display partition AA2 and other rows, causing abnormal display. When the first conduction level NVGH1 is concave, the partition enable signal VFE gradually rises from a low level to a high level. In this process, near the boundary between the first display partition AA1 and the second display partition AA2, a bright band is generated in some rows of the second display partition AA2 close to the first display partition AA1.

[0037] In view of the above research findings of the inventors, in order to solve the problems of the prior art, the embodiments of the present invention provide a display panel driving method and a display device. The following first introduces a display device to which the driving method provided by the embodiments of the present invention can be applied.

[0038] Figure 3 is a schematic diagram of the structure of a display device provided by an embodiment of the present invention. Figure 3 The display device includes a display panel 01 and a display driver module 02. The display driver module 02 can be a driver chip (Display Driver Integrated Circuit, DDIC) or a touch and display driver integrated (Touch and Display Driver Integration, TDDI) chip, etc.

[0039] The display panel 01 may include a display area AA and a non-display area NAA. The display area AA includes at least two display subareas. Each display subarea includes a plurality of pixel circuits PX arranged in an array.

[0040] The display panel 11 also includes a plurality of scan lines GL and a gate drive circuit 11. The plurality of scan lines GL extend along a first direction X and are arranged in sequence along a second direction Y. Each scan line GL is connected to a pixel circuit PX of a corresponding row (which may be one or more rows). The gate drive circuit 11 is connected to the plurality of scan lines GL, and the gate drive circuit 11 may be located in the non-display area NAA. The display panel 01 also includes a plurality of data lines DL extending along a second direction Y and arranged along a first direction X. Each data line DL is connected to a pixel circuit PX of a corresponding column (which may be one or more columns). The first direction X (which may be a row direction) and the second direction Y (which may be a column direction) intersect, for example, may be perpendicular. A column of pixel circuits PX may also be connected to two corresponding data lines, which is not specifically limited in the embodiment of the present invention.

[0041] Figure 4 is a schematic diagram of a display panel provided by an embodiment of the present invention, with reference to Figure 3 and Figure 4 , at least two display subareas include a first display subarea AA1 and a second display subarea AA2. Figure 3 The first display partition AA1 and the second display partition AA2 are adjacent to each other, the first display partition AA1 is the previous display partition of the second display partition AA2, and the refresh frequency of the second display partition AA2 is greater than the refresh frequency of the first display partition AA1. The pixel circuit PX is located in the display area. Each display partition includes a plurality of rows of pixel circuits PX. The pixel circuit PX is used to receive the scanning signal output by the gate drive circuit 12. The refresh frequency refers to the number of times the screen is refreshed per second.

[0042] refer to Figure 4 The gate driving circuit 11 includes a plurality of shift registers 10. When the display panel 01 includes a plurality of rows of pixels, the plurality of shift registers 10 are connected in cascade to provide scanning signals to the corresponding rows (e.g., at least one row) of pixel circuits PX. The first-stage shift register receives the input signal EIN. The display panel also includes at least one partition enable signal line ENL, and the shift register 10 is electrically connected to the partition enable signal line ENL.

[0043] Figure 5 FIG. 1 is a flow chart of a method for driving a display panel provided by an embodiment of the present invention. Figure 5 As shown, the driving method of the display panel includes:

[0044] S101, providing a partition enable signal to a partition enable signal line, so that the shift register outputs a scan signal to a correspondingly connected pixel circuit according to the partition enable signal, so as to control the refresh frequency of the correspondingly connected pixel circuit, thereby realizing a partition multi-frequency display mode.

[0045] Specifically, the partition multi-frequency display mode is a mode in which at least two display partitions have different refresh frequencies. The scan signal output by at least one shift register includes a first conduction level NVGH1.

[0046] Optionally, the partition enable signal VFE includes an enable level and a disable level. By controlling the enable level and the disable level period of the partition enable signal VFE on the partition enable signal line within a frame, the scanning signal output by different shift registers is controlled to be the first on level NVGH1 or the off level NVGL to control the refresh frequency of the correspondingly connected pixel circuit, thereby realizing the partition multi-frequency display mode.

[0047] In some optional embodiments of the present invention, the enable level of the partition enable signal VFE can be used as the first conduction level NVGH1 of the scanning signal output by the shift register. When the shift register outputs the partition enable signal VFE, and the partition enable signal VFE is the first conduction level NVGH1, the shift register can output the enable level of the partition enable signal VFE, that is, the first conduction level NVGH1. When the shift register outputs the partition enable signal VFE, and the partition enable signal VFE is the non-enable level, the shift register can output the non-enable level of the partition enable signal VFE, that is, the off level NVGL.

[0048] In some other optional embodiments of the present invention, the partition enable signal VFE can be used as a control signal to control the shift register to output the first conduction level NVGH1. Exemplarily, the shift register includes a first conduction level output module, the input end of the first conduction level output module can be connected to the first conduction level NVGH1, and the potential of the control end of the first conduction level output module can be controlled by the partition enable signal and other control signals. When the other control signals meet the conditions for the first conduction level output module to output the first conduction level, when the partition enable signal VFE is an enable level, the first conduction level output module can output the first conduction level NVGH1; when the other control signals meet the conditions for the first conduction level output module to output the first conduction level, when the partition enable signal VFE is a non-enable level, the first conduction level output module cannot output the first conduction level NVGH1, but the shutdown level is output by the shutdown level output module in the shift register.

[0049] Take the example that the scan signal output by each shift register 10 is transmitted to the functional module related to the data voltage writing process in each row of pixel circuits PX through each row of scan lines. When the scan signal output by a certain level of shift register 10 includes the first conduction level, the pixel circuit PX of the corresponding row can be controlled to perform data refresh, so that the current frame of the pixel circuit PX of the row is a refresh frame; and when the scan signal output by a certain level of shift register 10 does not include the first conduction level, the pixel circuit PX of the corresponding row cannot perform data refresh, so that the current frame of the pixel circuit PX of the row is a hold frame. Based on this, the potential jump of the partition enable signal VFE can be controlled to realize that in a display frame, during the data writing stage of some pixel circuits PX, the corresponding connected shift register 10 outputs the first conduction level, thereby realizing the high-frequency display of the display partition where the pixel circuit PX is located; during the data writing stage of some pixel circuits PX, the corresponding shift register 10 outputs the off level, thereby realizing the low-frequency display of the display partition where the pixel circuit PX is located, so as to realize the display of different frequencies of the partitions of the display device in the column direction.

[0050] S102 . In at least one frame of the subarea multi-frequency display mode, before controlling the scanning signal output by the first shift register corresponding to the second display subarea to be at the first conduction level, providing a driving signal corresponding to the driving mode of the second display subarea to the driving signal line.

[0051] The driving signal line includes a partition enable signal line and / or a data line. In the partition multi-frequency display mode, the refresh frequency of the second display partition AA2 is greater than the refresh frequency of the first display partition AA1; the first shift register corresponding to the second display partition AA2 is the shift register connected to the first row of pixel circuits in the second display partition AA2; the pixel circuit is used to write the data signal on the data line according to the received first conduction level; in the driving mode of the second display partition, the level on the partition enable signal line is the enable level, and the data line transmits the data signal.

[0052] Specifically, the driving signal includes a partition enable signal VFE and a data signal Vdata. The partition enable signal VFE indirectly affects the writing of the data signal Vdata by controlling the scanning signal output by the shift register. For example, when the partition enable signal VFE causes the shift register to output a corresponding scanning signal (such as a first conduction level), the pixel circuit will write the data signal Vdata on the data line according to the scanning signal.

[0053] The data line transmits a data signal, that is, the data signal on the data line may change according to different display images, or the data signal on the data line may be different according to different display grayscales corresponding to the pixels, and may not be a DC level or may not transmit a signal. For example, different data lines in different frames may correspond to different data signals to the same pixel, and different data lines in the same frame may transmit different data signals to different pixels.

[0054] Optionally, the first display subarea AA1 is in the refresh direction of the display panel (ie, the extending direction of the data line, for example Figure 2 The display partition adjacent to the second display partition AA2 in the second direction Y) and in the full refresh frame (that is, the display frame in which each display partition of the display panel writes data), the first display partition AA1 writes data before the second display partition AA2. Figure 4, before the scanning signal output by the first shift register corresponding to the second display partition AA2 is controlled to be the first conduction level, a driving signal corresponding to the refresh frequency of the second display partition AA2 is provided to the driving signal line. This enables the data signal to be prepared in advance according to the refresh frequency and timing requirements of the second display partition AA2. For example, for the second display partition AA2, the data signal can be prepared in advance with a higher frequency and a suitable amount of data. Due to the advance preparation and orderly transmission of the data signal, the load of the data driver will not increase suddenly. Instead, it is more evenly distributed in time, avoiding the overload problem caused by the load being concentrated in a certain time period when the partition is switched. For example, in the process of switching from the first display partition AA1 to the second display partition AA2, the load of the data driver will gradually transition from a low load state to a load state suitable for the second display partition AA2, realizing load averaging. When the data driver load is averaged, it can provide data signals to different display partitions more stably. Near the dividing line, the data signal transmission will not be unstable due to excessive load on one side, thereby reducing the possibility of display abnormality. Before the scanning signal output by the first shift register of the second display partition AA2 is the first conduction level, the partition enable signal of the partition enable signal line connected to the first shift register of the second display partition AA2 is already in a state matching the refresh frequency of the second display partition AA2, so that the process of the partition enable signal jumping from the off level to the first conduction level can be completed before the first shift register corresponding to the second display partition AA2 outputs the first conduction level of the scanning signal, and then when the first shift register corresponding to the second display partition AA2 outputs the first conduction level of the scanning signal, that is, when the pixel circuit starts to write data, the first conduction level has reached a stable first conduction level, so that the pixel circuit can write data normally. In this way, the pixel brightness switching of the second display partition AA2 and the first display partition AA1 in the boundary area can be smoother, which can improve the abnormal display phenomenon near the boundary line during split-screen display and improve the display effect.

[0055] The driving method of the display panel provided in an embodiment of the present invention provides a partition enable signal to the partition enable signal line so that the shift register outputs a scan signal to the correspondingly connected pixel circuit according to the partition enable signal to control the refresh frequency of the correspondingly connected pixel circuit, thereby realizing a partition multi-frequency display mode. By providing a driving signal corresponding to the refresh frequency of the second display partition to the driving signal line before controlling the scanning signal output by the first shift register corresponding to the second display partition to be the first conduction level within at least one frame of the partition multi-frequency display mode, the driving signal includes a partition enable signal on the partition enable signal line and / or a data signal on the data line, so that before the pixel circuit connected to the first shift register corresponding to the second display partition starts to write the data signal, the data signal connected to the pixel circuit is already in a state matching its own driving mode; and / or, before the scanning signal output by the first shift register of the second display partition is the first conduction level, the partition enable signal of the partition enable signal line connected to the first shift register of the second display partition is already in a state matching the driving mode of the second display partition, so that the process of the partition enable signal jumping from the off level to the first conduction level can be completed before the first shift register corresponding to the second display partition outputs the first conduction level of the scanning signal, so that when the first shift register corresponding to the second display partition outputs the first conduction level of the scanning signal, that is, when the pixel circuit starts to write data, the first conduction level has reached a stable first conduction level, so that the pixel circuit can write data normally. In this way, the pixel brightness switching in the boundary area between the second display partition and the first display partition can be smoother, which can improve the abnormal display phenomenon near the boundary line during split-screen display and enhance the display effect.

[0056] Optionally, the enable level is a first conduction level NVGH1; in the partition multi-frequency display mode, the scanning signal output by at least one shift register includes the first conduction level NVGH1 of the partition enable signal VFE; Figure 6 FIG. 1 is a schematic diagram of another display panel driving method provided by an embodiment of the present invention. Figures 3 to 6 , the driving method of the display panel includes:

[0057] S201, providing a partition enable signal to a partition enable signal line, so that the shift register outputs a scan signal to a correspondingly connected pixel circuit according to the partition enable signal, so as to control a refresh frequency of the correspondingly connected pixel circuit, thereby realizing a partition multi-frequency display mode.

[0058] S202 . In at least one frame of the partition multi-frequency display mode, before controlling the scanning signal output by the first shift register corresponding to the second display partition to be at the first conduction level, provide a first conduction level to the partition enable signal line.

[0059] The partition enabling signal line is set to be the partition enabling signal line connected to the first shift register corresponding to the second display partition AA2.

[0060] Specifically, the output of the shift register 10 is affected by the partition enable signal VFE. The partition enable signal VFE indirectly affects the writing of the data signal Vdata by controlling the output of the shift register 10. When the partition enable signal line provides a first conduction level, the shift register 10 can output the first conduction level under appropriate conditions, so that the pixel circuit writes the data signal on the data line according to the scanning signal.

[0061] The pixel circuit writes the data signal on the data line according to the received scanning signal (such as the first conduction level NVGH1). Providing the first conduction level NVGH1 to the partition enable signal line in advance can make the partition enable signal jump from the off level to the first conduction level before the first shift register corresponding to the second display partition AA2 outputs the first conduction level, so that even if the voltage change on the data line causes the load change of the first display partition AA1 and the second display partition AA2, the first conduction level will be less affected by the load change on the data line because the time for the first conduction level to jump from the off level to the first conduction level is advanced, and the pixel circuit data voltage writing is less affected, thereby improving the display abnormality phenomenon.

[0062] Optionally, in at least part of the frames of the partition multi-frequency display mode, the time for providing the first conduction level to the set partition enable signal line is controlled to gradually increase or decrease compared to the time when the first shift register corresponding to the second display partition AA2 outputs the first conduction level.

[0063] Specifically, in at least a portion of the frames of the partitioned multi-frequency display mode, the time at which the partition enable signal line connected to the first shift register corresponding to the second display partition AA1 provides the first conduction level is earlier than the time at which the first shift register corresponding to the second display partition AA2 outputs the scanning signal as the first conduction level, and this advance time is gradually increasing or decreasing.

[0064] Exemplarily, it is assumed that the display panel is divided into two display partitions, the refresh frequency of the first display partition AA1 is 1 Hz, the refresh frequency of the second display partition AA2 is 120 Hz, and now the display is switched from the first display partition AA1 to the second display partition AA2.

[0065] In the partition multi-frequency display mode, the second frame, the third frame and the fourth frame perform a gradual operation. In the second frame, the time for providing the first conduction level to the partition enable signal line connected to the first shift register corresponding to the second display partition AA2 is 1 unit time earlier than the time when the first shift register corresponding to the second display partition AA2 outputs the scanning signal as the first conduction level (the unit time here can be a time scale such as microseconds, which is only set for the convenience of example). In the third frame, the advance time becomes 2 unit times. In the fourth frame, the advance time becomes 3 unit times. Through such a gradual change method, the load changes of the first display partition AA1 and the second display partition AA2 are gradually averaged to multiple rows of pixel circuits, reducing the impact of the load changes caused by different refresh frequencies of the display partitions on the display effect, and improving the display abnormality in the boundary area of ​​the first display partition AA1 and the second display partition AA2.

[0066] Optionally, in at least part of the frames of the partitioned multi-frequency display mode, the control provides a first conduction level to the set partition enable signal line, which is advanced by a time period that the scanning signal output by the first shift register corresponding to the second display partition AA2 is the first conduction level, and gradually increases or decreases in a manner that changes every d frames, where d is greater than or equal to 0.

[0067] Specifically, the partition enable signal line connected to the first shift register corresponding to the second display partition AA2 is controlled to provide a first conduction level. Compared with the scanning signal output by the first shift register corresponding to the second display partition AA2, the time of advance to the first conduction level is changed every d frames. In the case of d=0, the advance time can be changed for each frame. In the case of d being greater than or equal to 1, the advance time is not changed for each frame, but is changed at a certain interval of d frames. When the advance time is gradually changed at a certain interval, a sudden increase in the load on the data driver can be avoided, and the load is gradually increased, thereby achieving load averaging.

[0068] Optionally, in at least part of the frames of the partition multi-frequency display mode, the control gradually increases the time in advance of providing the first conduction level to the set partition enable signal line compared to the scanning signal output by the first shift register corresponding to the second display partition AA2 as the first conduction level. The advance time can change in a step-by-step manner at equal intervals. For example, every few frames, the advance time jumps to a fixed value. Assume that it increases once every 3 frames, and the fixed value of each increase is t. If the advance time is t0 in the first frame, then the advance time becomes t0+t in the 4th frame, and the advance time becomes t0+2t in the 7th frame, etc. It can also be a step-by-step change at non-equal intervals. For example, the advance time of the first two frames remains unchanged, and starting from the 3rd frame, different values ​​are added at different intervals of different frame numbers. For example, the advance time increases by t1 in the 3rd frame, and the advance time increases by t2 in the 6th frame, etc. Among them, t2 is greater than t1.

[0069] The partitioned multi-frequency display mode includes a first display frame and a second display frame. The first display frame is a holding frame for at least part of the row pixel circuits in the first display partition AA1 and a refresh frame for the second display partition AA2. The second display frame is a refresh frame for the first display partition AA1 and the second display partition AA2.

[0070] In the refresh frame of the pixel circuit, the pixel circuit writes the data voltage, and in the hold frame of the pixel circuit, the pixel circuit does not write the data voltage.

[0071] Optionally, n first display frames between adjacent second display frames are divided into multiple display sub-periods; n is less than or equal to the difference between the refresh frequency of the second display partition AA2 and the refresh frequency of the first display partition AA1; and the display sub-period includes multiple first display frames.

[0072] In at least one display sub-period, the control provides a first conduction level to the set partition enable signal line, and the time is advanced compared to the time when the first shift register corresponding to the second display partition AA2 outputs the first conduction level, and the time is gradually increased or decreased in a manner of changing every d frames; wherein the display sub-period includes multiple first display frames; wherein d is less than n.

[0073] Specifically, the first display frame is a holding frame for at least part of the row pixel circuits in the first display partition AA1, which means that these pixel circuits maintain the previous data state in the first display frame and do not write or refresh new data; at the same time, the first display frame is also a refresh frame for the second display partition AA2, that is, the second display partition AA2 will perform data update operations in this frame. The second display frame is a frame in which both the first display partition AA1 and the second display partition AA2 are refreshed. In the second display frame, the pixel circuits of the two partitions receive new data and update the display content.

[0074] For example, in a certain period of time, the second display partition AA2 is performing a refresh operation for the 10th frame, and at this time, at least some of the row pixel circuits in the first display partition AA1 are in a frame-holding state, and they keep displaying the data of the previous frame without writing new data. The second display partition AA2 is receiving new data signals and updating the display content of the corresponding pixels. The 10th frame is a refresh frame for the second display partition AA2, but a holding frame for some pixel circuits in the first display partition AA1.

[0075] In the second display frame, all pixel circuits of the first display partition AA1 (including the odd-numbered rows of pixel circuits that were previously in the hold state in the first display frame) are refreshed, receive new data signals and update the display. At the same time, the second display partition AA2 is also refreshed. For example, this may be a key frame in which the first display partition AA1 and the second display partition AA2 simultaneously update the display content to present a complete picture. For example, when displaying a large image spanning two partitions or switching video scenes, the two partitions need to be refreshed at the same time. The frame at this time is the second display frame.

[0076] Assuming that there are 10 first display frames (i.e., n=10) in a certain display sub-period, d can take a value less than 10, such as 3. This means that every 3 frames, the advance time for providing the first conduction level to the set partition enable signal line will change, which may be gradually increasing (such as the advance time is 1ms, 2ms, 3ms, etc.) or gradually decreasing (such as the advance time is 3ms, 2ms, 1ms, etc.). This control method enables the partition enable signal of the second display partition AA2 to switch from the off level to the first conduction level more smoothly when entering the refresh phase, reducing the load change that may be caused by the instantaneous level switching, thereby optimizing the effect of the multi-frequency display of the entire partition, and making the display transition of the two partitions in the boundary area smoother.

[0077] Optionally, in a previous display sub-period in an adjacent display sub-period, the time for providing the first conduction level to the set partition enable signal line is controlled to be gradually increased or decreased in advance compared to the time when the first shift register corresponding to the second display partition AA2 outputs the first conduction level, changing every d frames.

[0078] For example, assuming that d=3, there are 12 first display frames in the previous display sub-period, then in the 1st frame, the 4th frame, the 7th frame, and the 10th frame, the time for providing the first conduction level to the set partition enable signal line will gradually increase (such as 1ms, 2ms, 3ms, 4ms in advance) or gradually decrease (such as 4ms, 3ms, 2ms, 1ms in advance). The purpose of this control method is to gradually adjust the level state of the set partition enable signal line before the second display partition AA2 starts to refresh, so that the partition enable signal can switch from the off level to the first conduction level more smoothly, avoiding signal interference or display abnormality caused by sudden level changes. By gradually increasing or decreasing the advance time, the pixel circuit of the second display partition AA2 can adapt to the new data writing more smoothly when entering the refresh stage, reducing the brightness fluctuation or image flickering caused by the change of refresh frequency, especially in the partition boundary area, which can make the display transition more natural.

[0079] In the next display sub-period in the adjacent display sub-periods, the time for providing the first conduction level to the set partition enable signal line is controlled to gradually decrease or increase in a manner of changing every d frames compared to the time when the first shift register corresponding to the second display partition AA2 outputs the first conduction level.

[0080] For example, if the next display sub-cycle also has 12 first display frames, and d is still 3, then in the 1st frame, the 4th frame, the 7th frame, and the 10th frame, the time for providing the first conduction level to the set partition enable signal line in advance will change in the opposite trend to that of the previous display sub-cycle (if the previous one is gradually increasing, it is gradually decreasing here; vice versa). The reason for this is that the partition enable signal has been preliminarily adjusted in the previous display sub-cycle. The next display sub-cycle can further optimize the stability of the signal through reverse adjustment, so that the second display partition AA2 maintains a more stable state during the refresh process. At the same time, it also helps to balance the display differences between the two partitions, ensure the continuity and consistency of the entire display screen at the junction of the partitions, and avoid obvious visual fragmentation or display abnormalities. This control method that adopts different trends in adjacent display sub-cycles can more effectively adapt to the collaborative work between different frequency partitions in partition multi-frequency display and improve display quality.

[0081] Optionally, the number of first display frames included in the multiple display sub-periods is equal.

[0082] In some other optional embodiments of the present invention, within multiple frames of the partition multi-frequency display mode, the control provides a first conduction level to the set partition enable signal line at an equal advance time compared to the scanning signal output by the first shift register corresponding to the second display partition AA2 being the first conduction level.

[0083] Specifically, in multiple frames of the partition multi-frequency display mode, each time the first conduction level is provided to the set partition enable signal line, it is earlier than the time when the first shift register corresponding to the second display partition AA2 outputs the scan signal as the first conduction level, and this advance time is fixed and equal. For example, assuming that the advance time is fixed to t (which can be a time unit such as microseconds), in the first frame, the partition enable signal line provides the first conduction level at time point T1, and the first shift register outputs the scan signal as the first conduction level at time point T1+t; in the second frame, the partition enable signal line provides the first conduction level at time point T2, and the first shift register outputs the scan signal as the first conduction level at time point T2+t. Under the fixed time difference setting, the partition enable signal can reach the first shift register corresponding to the second display partition AA2 in advance according to a stable rhythm. The scan signal output by the first shift register also becomes more regular. Since the advance time of the partition enable signal is fixed, the output time of the scan signal as the first conduction level is also fixed accordingly. For example, when switching from one display partition to another, the scan signal can start to output the first conduction level at a fixed time point, so that the pixel circuit can receive the scan signal in a stable timing and perform data writing and refresh operations, thereby ensuring the stability of the display.

[0084] Figure 7 Schematic diagram of a gate drive circuit provided by an embodiment of the present invention. Figure 7 As shown, optionally, each level of shift register 10 includes a level transmission unit 220 and an output unit 230, the level transmission unit 220 is used to transmit the second conduction level NVGH2 step by step; the output unit 230 is connected to the partition enable signal VFE, and is used to transmit the partition enable signal VFE to the output end of the shift register 10 when the level transmission unit 220 outputs the second conduction level NVGH2, and the output end of the shift register 10 is used to output the scan signal.

[0085] Optionally, continue to refer to Figure 7 , in at least one frame of the partition multi-frequency display mode, before the control setting level transmission unit 220 outputs the second conduction level NVGH2, the first conduction level NVGH1 of the partition enable signal VFE is provided to the setting partition enable signal line. The setting level transmission unit 220 is the level transmission unit 220 of the shift register 10 connected to the first row of pixel circuits in the second display partition AA2. The magnitude of the first conduction level NVGH1 may be the same as the potential magnitude of the second conduction level NVGH2, or may be different from the potential magnitude of the second conduction level NVGH2.

[0086] Specifically, since the output unit 230 can output the partition enable signal when the level transmission unit 220 outputs the second conduction level, before the level transmission unit 220 is set to output the second conduction level NVGH2, the first conduction level NVGH1 of the partition enable signal VFE is provided to the set partition enable signal line, so that the output unit 230 of the first shift register corresponding to the second display partition AA2 can output the partition enable signal, and the first conduction level NVGH1 of the partition enable signal VFE is provided to the set partition enable signal line, so that the partition enable signal VFE can be prepared in advance. Providing the partition enable signal VFE in advance makes the subsequent signal transmission more orderly. In this way, even if the voltage change on the data line causes the load change of the first display partition AA1 and the second display partition AA2, because the time for the first conduction level to jump from the off level to the first conduction level is advanced, the first conduction level will be less affected by the load change on the data line, thereby making the pixel circuit data voltage writing less affected, thereby improving the display abnormality phenomenon. When the partition enable signal VFE reaches the first shift register 10 in advance, the shift register 10 can output the scanning signal in a correct order and rhythm, and then the pixel circuit can write the data signal on the data line in an orderly manner according to the scanning signal.

[0087] When the refresh rate of the second display partition AA2 is higher than that of the first display partition AA1, at the moment of switching, if the partition enable signal is not prepared in advance, the pixel circuit may suddenly put forward a higher load requirement on the data driver, resulting in a sudden increase in the load of the data driver. By providing the partition enable signal in advance, the data driver can have a gradual load adjustment process during the partition switching process. When the data driver load is averaged, the possibility of display abnormality can be reduced.

[0088] Figure 8 is a schematic diagram of the structure of another display panel provided by an embodiment of the present invention. Figure 8 Optionally, the display panel includes k partition enable signal lines, the gate drive circuit includes multiple cascaded shift register groups 20, each shift register group includes k cascaded shift register units 21, k is an integer greater than or equal to 2, each shift register unit 21 includes m shift registers 10, m is an integer greater than or equal to 1, different shift register units 21 in the same shift register group 20 are electrically connected to different partition enable signal lines, and different shift register groups 20 are connected to the same k partition enable signal lines.

[0089] The display partition includes multiple pixel circuit groups 12; the pixel circuit group 12 includes k sub-pixel circuit groups 121, and the sub-pixel circuit group 121 includes multiple rows of pixel circuits PX; the sub-pixel circuit groups 121 are electrically connected to the shift register units 21 in a one-to-one correspondence; the output end of the first-level shift register 10 is electrically connected to r rows of pixel circuits PX, where r is an integer greater than or equal to 1.

[0090] in, Figure 8 The case where k=4 is schematically shown in FIG. 4 . For example, m may be 16, and r may be 1. Each shift register group 20 may control the display conditions of k*m*r rows of pixel circuits. Figure 8 The shift register group 20 of the first gate driving circuit in the display panel shown can be regarded as including four cascaded shift register units 21, and four partition enable signal lines, namely ENL1, EN2, ENL3 and ENL4. One partition enable signal line is connected to m shift registers 10 in one shift register unit 21. Each partition enable signal line can drive m*r rows of pixel circuits driven by one shift register unit 21, and the number of rows driven by four partition enable signal lines is one cycle.

[0091] Optional, Fig. 9 Schematic diagram of the jump of the partition enabling signal in the first display frame and the second display frame provided by an embodiment of the present invention, with reference to Fig. 9 In the first display frame F1, the time when the pulse of the signal on the k partition enable signal line jumps to the first conduction level NVGH1 is delayed in sequence (combined with Figure 8 and Fig. 9 , VFE1 is the partition enable signal on the partition enable signal line ENL1, VFE2 is the partition enable signal on the partition enable signal line ENL2, VFE3 is the partition enable signal on the partition enable signal line ENL3, and VFE4 is the partition enable signal on the partition enable signal line ENL4); in the second display frame F2, the signals on the k partition enable signal lines are the first conduction level NVGH1. Among them, the first display frame is a holding frame for at least part of the row pixel circuits in the first display partition AA1, and is a refresh frame for the second display partition AA2; the second display frame is a refresh frame for the first display partition AA1 and the second display partition AA2. In the second display frame, the first display partition is refreshed before the second display partition.

[0092] Specifically, the first display frame F1 is a refresh frame of at least one display partition, and is a hold frame of at least one display partition. Fig. 9Taking the illustrated case as an example, the pixel circuit connected to the shift register corresponding to the off level NVGL works in the hold frame, and the pixel circuit connected to the shift register corresponding to the first on level NVGH works in the refresh frame. In this case, the moment when the pulse of the signal on the k partition enable signal lines jumps to the enable level is delayed in sequence, so as to facilitate the completion of the partition multi-frequency control. The second display frame F2 is the refresh frame of each display partition. In the second display frame, the signal on the k partition enable signal lines is the first on level, which can ensure that each display partition can be refreshed in the second display frame, and the signal on the partition enable signal line does not need to jump. The first partition enable signal line ENL1 transmits the first partition enable signal VFE1 to the corresponding shift register. The second partition enable signal line ENL2 transmits the second partition enable signal VFE2 to the corresponding shift register. The third partition enable signal line ENL3 transmits the third partition enable signal VFE3 to the corresponding shift register. The fourth partition enable signal line ENL4 transmits the fourth partition enable signal VFE4 to the corresponding shift register.

[0093] Optionally, k-1 shift register units 21 are connected between two adjacent shift register units 21 connected to the same partition enable signal line.

[0094] Specifically, the sub-pixel rows connected to the k partition enable signal lines are arranged periodically. Exemplarily, the number of sub-pixel rows connected to the first partition enable signal line ENL1 is 1 to 16 rows, 65 to 80 rows... The number of sub-pixel rows connected to the second partition enable signal line ENL2 is 17 to 32 rows, 81 to 96 rows... The number of sub-pixel rows connected to the third partition enable signal line ENL3 is 33 to 48 rows, 97 to 112 rows... The number of sub-pixel rows connected to the fourth partition enable signal line ENL4 is 49 to 64 rows, 98 to 128 rows...

[0095] Optionally, m is greater than or equal to 8, and k is greater than or equal to 4.

[0096] Continue to refer Figure 7 and Figure 8 Optionally, in at least one frame of the partition multi-frequency display mode, before the control setting level transmission unit 220 outputs the second conduction level NVGH2, and in the shift register 10 corresponding to the pixel circuit group 12 adjacent to the second display partition AA2 in the first display partition AA1, after the second conduction level output by the level transmission unit 220 of the shift register connected to the setting partition enable signal line jumps to the turn-off level NVGL, the first conduction level of the partition enable signal is provided to the setting partition enable signal line.

[0097] Exemplarily, the partition enable signal line is set to be the first partition enable signal line ENL1, and in the shift register 10 connected to the pixel circuit group 12 adjacent to the second display partition AA2 in the first display partition AA1, the shift register 10 connected to the first sub-pixel circuit group 121 is also connected to the first partition enable signal line ENL1. Only after the level transmission unit 220 of the shift register 10 connected to the first sub-pixel circuit group 121 in the first display partition AA1 outputs the turn-off level NVGL, and then provides the first turn-on level NVGH1 of the partition enable signal to the set partition enable signal line EN1, will it not affect the scan signal output by the shift register 10 connected to the first sub-pixel circuit group 121 in the first display partition AA1.

[0098] Optionally, the number of rows of pixel circuits in each pixel circuit group is the same.

[0099] Optionally, the time for providing the first conduction level to the set partition enable signal line is less than or equal to k*c*b in advance of the first conduction level output by the first shift register corresponding to the second display partition AA2, where c is the number of rows of pixel circuits included in a pixel circuit group 12, and b is equal to the sum of the first conduction level pulse width time corresponding to a row of pixel circuits and a preset time interval, where the preset time interval is equal to the time interval between two adjacent shift registers outputting the first conduction level. Optionally, the preset time interval is greater than or equal to 0.

[0100] Specifically, for example, k=4, c=16. Then k*c*b=4*16*b=64b, that is, the time for providing the first conduction level to the set partition enable signal line is less than or equal to 64b in advance of the first conduction level output by the first shift register corresponding to the second display partition AA2. This restriction condition can ensure that under this specific display panel setting, the signal transmission and display process can proceed normally, avoiding the display abnormality of the first display partition AA1 caused by too much advance in time. Since the writing of data voltage requires a certain amount of time, the time for providing the first conduction level to the set partition enable signal line is too long in advance of the first conduction level output by the first shift register corresponding to the second display partition AA2, which will result in insufficient data writing time for some rows of pixel circuits in the display panel. In some optional embodiments, the time for providing the first conduction level to the set partition enable signal line can be set to be less than or equal to (k-1)*c*b in advance of the first conduction level output by the first shift register corresponding to the second display partition AA2, so as to ensure that the pixel circuit in the display panel can write data voltage normally.

[0101] Optionally, in at least part of the first n frames of the partition multi-frequency display mode, the time in which the first conduction level NVGH1 is provided to the set partition enable signal line is gradually increased or decreased compared to the time in which the set level transfer unit outputs the second conduction level NVGH2; n is greater than or equal to 2.

[0102] Specifically, assuming n=5, the display panel is divided into two display partitions, the refresh frequency of the first display partition AA1 is 1 Hz, and the refresh frequency of the second display partition AA2 is 60 Hz. In the first 5 frames in the partition multi-frequency display mode, it is assumed that only the 2nd, 3rd and 4th frames perform a gradient operation.

[0103] In the second frame, the time for providing the first conduction level to the partition enable signal line connected to the first shift register corresponding to the second display partition AA2 is 1 unit time earlier than the time for the second conduction level output by the first stage transmission unit corresponding to the second display partition AA2. In the third frame, the advance time becomes 2 unit time. In the fourth frame, the advance time becomes 3 unit time. Through such a gradual change, the load of the data driver is more evenly distributed in time. In at least part of the first n frames of the partition multi-frequency display mode, as the advance time of the partition enable signal gradually changes, the data driver can gradually adjust its data output according to the gradually changing working state of the shift register. For example, in some frames, the data driver can steadily increase the amount of data provided according to the gradual increase in the data demand of the pixel circuit, rather than suddenly increasing a large amount of data in a certain frame, so that the load is more evenly distributed in these frames, and the load is averaged, so that the shift register corresponding to the second display partition AA2 can output the scanning signal more smoothly, thereby avoiding display abnormality in the boundary area between the first display partition AA1 and the second display partition AA2.

[0104] Optionally, in at least part of the first n frames of the partition multi-frequency display mode, the time for providing the first conduction level to the set partition enable signal line in advance of the second conduction level output by the set level transmission unit gradually increases. In this way, the load change caused by the change of the data signal can be gradually averaged to more rows of pixel circuits, which can further improve display abnormalities.

[0105] Optionally, the time in which the first conduction level of the partition enable signal is provided to the partition enable signal line ahead of the second conduction level output by the stage transfer unit is equal to an integer multiple of the sum of the first conduction level pulse width time output by the shift register and the preset time interval.

[0106] Specifically, the first on-level pulse width time output by the shift register is equal to the sum of the first on-level pulse width time of the input signal EIN connected to the shift register and the time of the preset time interval. Since the pixel circuit is refreshed row by row during the display panel refresh process, by setting the first on-level of the partition enable signal provided to the set partition enable signal line in advance of the time of the second on-level output by the set level transmission unit, which is equal to the integer multiple of the sum of the first on-level pulse width time output by the shift register and the time of the preset time interval, it is more convenient and easy to implement in the drive control of the display panel.

[0107] Fig.10 FIG. 1 is a flow chart of another method for driving a display panel provided by an embodiment of the present invention. Fig.10 As shown, the driving method of the display panel includes:

[0108] S301, providing a partition enable signal to a partition enable signal line, so that the shift register outputs a scan signal to a correspondingly connected pixel circuit according to the partition enable signal, so as to control the refresh frequency of the correspondingly connected pixel circuit, thereby realizing a partition multi-frequency display mode.

[0109] S302 , in at least one frame of the partition multi-frequency display mode, before controlling the first shift register corresponding to the second display partition to output the first conduction level of the partition enable signal, outputting a data signal to the data line in a first output mode.

[0110] Specifically, in the first output mode, the data signal output to the data line has a jump. In at least one frame of the partition multi-frequency display mode, before the first shift register corresponding to the second display partition AA2 is controlled to output the first conduction level of the partition enable signal, providing the data signal to the data line can create conditions for the preparation of the data signal of the second display partition AA2. Although the first shift register corresponding to the second display partition AA2 has not yet output the first conduction level of the partition enable signal, the data signal has been output in the first output mode corresponding to the second display partition AA2. When the partition is switched, if the data signal is not provided to the data line in advance, the load of the data driver may suddenly change. When the refresh frequency of the second display partition AA2 is higher than that of the first display partition AA1, at the moment of switching, the pixel circuit's demand for data suddenly increases, and the data driver may not be able to provide enough data signals in time, resulting in abnormal display. By providing the data signal to the data line in advance, the data driver can gradually adjust the provision of the data signal according to the refresh frequency and timing requirements of the second display partition AA2, so that the change in load is averaged to the scanning time corresponding to the multiple rows of pixel circuits, avoiding the influence of the load mutation on the display, thereby improving the abnormal display of the partition boundary.

[0111] Optionally, continue to refer to Figure 7 and Figure 8 , in at least one frame of the partition multi-frequency display mode, before the first level transmission unit 220 corresponding to the second display partition AA2 is controlled to output the second conduction level NVGH2, the data signal is output to the data line DL in the first output mode. The first level transmission unit 220 corresponding to the second display partition AA2 is the level transmission unit 220 of the shift register 10 connected to the first row of pixel circuits in the second display partition AA2.

[0112] Specifically, before the first level transfer unit 220 corresponding to the second display partition AA2 outputs the second conduction level NVGH2, a data signal is provided to the data line in the first output mode. First, during the partition switching process, if the data signal is not provided in advance, data conflicts may occur. When switching from the first display partition AA1 to the second display partition AA2, the requirements of the second display partition AA2 for the data signal may be different from those of the first display partition AA1. Providing the data signal to the data line in advance can be adjusted according to the refresh frequency and related requirements of the second display partition AA2, so that at the moment of partition switching, the data signal can meet the requirements of the second display partition AA2, avoiding display anomalies caused by mismatching of the data signal, such as flickering, bright lines, etc., thereby improving the abnormal display of the partition boundary. Secondly, providing the data signal to the data line in advance can make the load of the data driver more stable. When the partition is switched, if the data signal changes suddenly, the data driver will face the problem of sudden load changes. By providing the data signal in advance, the data driver can gradually adjust the provision of the data signal according to the refresh frequency and timing requirements of the second display partition AA2, so that the load is more evenly distributed in time, avoiding display anomalies caused by sudden changes in load, and thus improving the display anomalies at the partition boundary.

[0113] Fig.11 FIG. 1 is a flow chart of another method for driving a display panel provided by an embodiment of the present invention. Fig.11 As shown, the driving method of the display panel includes:

[0114] S401, providing a partition enable signal to a partition enable signal line, so that the shift register outputs a scan signal to a correspondingly connected pixel circuit according to the partition enable signal, so as to control the refresh frequency of the correspondingly connected pixel circuit, thereby realizing a partition multi-frequency display mode.

[0115] S402 , in at least one frame of the partitioned multi-frequency display mode, before controlling the first stage transmission unit corresponding to the second display partition to output a second conduction level, to output a data signal to the data line in a first output mode.

[0116] S403. In at least one frame of the partitioned multi-frequency display mode, when the level transfer unit of the shift register corresponding to the first display partition is controlled to output the second conduction level, a DC level is output to the data line in the second output mode, or no signal is output to the data line; and / or, in at least one frame of the partitioned multi-frequency display mode, when the level transfer unit corresponding to the first display partition is controlled to output the second conduction level, an off level is provided to the partition enable signal line.

[0117] Specifically, in the second output mode, the signal output to the data line is a DC level, and its value does not need to be changed frequently. This stable data signal transmission can reduce the workload of the data driver, because it does not need to continuously provide data signals of different values, thereby reducing the power consumption of the data driver. Not outputting signals to the data lines directly avoids energy consumption during data transmission, because no voltage flows on the data lines, and the data driver does not need to provide power for this part of the data transmission, thereby reducing the power consumption of the data driver. Providing a shutdown level to the partition enable signal line can make the related shift register or other circuit elements enter the shutdown state. When these circuit elements are turned off, they do not consume power, thereby reducing the power consumption of the entire display system. For example, the related transistors may be cut off due to the shutdown level of the partition enable signal line, and no current passes through, thereby reducing the consumption of power.

[0118] Optionally, the time in which the drive signal corresponding to the refresh frequency of the second display partition AA2 is provided to the drive signal line in advance relative to the first conduction level of the first shift register output partition enable signal corresponding to the second display partition AA2 is positively correlated with the refresh frequency difference between the second display partition AA2 and the first display partition AA1. This means that when the refresh frequency difference between the second display partition AA2 and the first display partition AA1 is greater, the advance time of providing the drive signal to the drive signal line is longer. This setting is to better adapt to the switching between partitions with different refresh frequencies, and ensure that the data signal and the scan signal can be more reasonably coordinated during the partition switching process to achieve a better display effect.

[0119] Assume that the refresh frequency of the first display partition AA1 is 10Hz, the refresh frequency of the second display partition AA2 is 60Hz, and the difference between the two refresh frequencies is 50Hz. According to the positive correlation, the time in advance of providing the drive signal line with the drive signal corresponding to the refresh frequency of the second display partition AA2 relative to the first conduction level of the first shift register output partition enable signal corresponding to the second display partition AA2 will be longer. Assume that the refresh frequency of the first display partition AA1 is 30Hz, the refresh frequency of the second display partition AA2 is 40Hz, and the difference between the two refresh frequencies is 10Hz. In this case, the advance time will be shorter than the previous case.

[0120] When the refresh frequency difference is large, providing the driving signal in advance for a long time can allow the data driver to have enough time to prepare the data signal according to the refresh frequency and timing requirements of the second display partition AA2. For example, for the second display partition AA2 with a high refresh frequency, the data driver can prepare the data signal with a higher frequency and a suitable data amount in advance to avoid display abnormalities caused by sudden changes in the data signal when the partition is switched.

[0121] Optionally, in at least one first display frame of the partition multi-frequency mode, before controlling the scanning signal output by the first shift register corresponding to the second display partition to be the first conduction level, a driving signal corresponding to the driving mode of the second display partition is provided to the driving signal line.

[0122] Specifically, the driving signal includes a partition enable signal on a partition enable signal line and / or a data signal on a data line. For example, providing a partition enable signal matching the driving mode of the second display partition AA2 in advance can make the process of the partition enable signal jumping from the off level to the first on level completed before the first shift register outputs the first on level of the scanning signal, thereby ensuring that when the pixel circuit starts to write data, the first on level has stabilized, so that the pixel circuit can write data normally. For the data signal on the data line, providing a signal corresponding to the driving mode of the second display partition AA2 in advance can allow the data driver to have enough time to prepare the data signal according to the refresh frequency and timing requirements of the second display partition AA2, avoiding display anomalies caused by sudden changes in the data signal during partition switching, such as flickering, bright lines, etc., thereby improving the abnormal display of the partition boundary, making the pixel brightness switching of the second display partition AA2 and the first display partition AA1 in the boundary area smoother, and improving the overall display effect.

[0123] Optionally, the first display frame and the second display frame include a first time period, a second time period and a third time period, respectively; in the first time period of the first display frame, the scan signal output to the N-row pixel circuit of the first display partition continues to be an off level, a non-enable level is provided to the partition enable signal line, and a DC level is provided to the data line, or no signal is output to the data line; in the second time period of the first display frame, the scan signal output to the M-row pixel circuit of the first display partition includes a turn-on level, an enable level is provided to the partition enable signal line, and a data signal is provided to the data line; in the third time period of the first display frame, the scan signal output to the pixel circuit of the second display partition includes a turn-on level, an enable level is provided to the partition enable signal line, and a data signal is provided to the data line; the M-row pixel circuit is located between the N-row pixel circuit and the second display partition; wherein, the M corresponding to at least two first display frames are not equal.

[0124] Specifically, in the first time period of the first display frame, the scanning signal output to the N rows of pixel circuits in the first display partition is continuously at the off level, which means that these pixel circuits are in an inactive state during this period and will not perform data update operations. At the same time, providing a non-enable level to the partition enable signal line further ensures that these pixel circuits will not be disturbed by unnecessary interference and mistakenly start data writing. For the data line, a DC level is provided (such as setting the data line to a high impedance state or providing a fixed DC voltage) or no signal is output to it. This is because these pixel circuits do not need new data during this period. In this way, the energy consumption of the data driver can be reduced and unnecessary data transmission can be avoided. For example, when displaying a relatively static part of a picture (such as a background area), the pixel circuit corresponding to the area can be in this low-power holding state in the first period, saving energy and maintaining the stability of the display.

[0125] In the second time period of the first display frame, the scan signal output to the M-row pixel circuit located between the N-row pixel circuit and the second display partition in the first display partition includes a conduction level, which enables the M-row pixel circuit to be activated and can receive data signals. At the same time, the enable level is provided to the partition enable signal line, creating conditions for data writing, and the data signal is provided to the data line, at which time these pixel circuits begin to perform data update operations. This time-division and line-division control method can more finely manage the pixel circuits in different areas of the display partition, and perform targeted data updates according to the needs of the display content. For example, if some areas in the display screen need to update data in the second time period of the first display frame, this can be achieved in this way. Moreover, since the M corresponding to at least two first display frames is not equal, it means that in different first display frames, the range of M-row pixel circuits for data update may be different, which can further optimize the display effect, make the dynamic changes of the screen more natural and smooth, and avoid abrupt update areas.

[0126] In the third period of the first display frame, the scan signal output to the pixel circuit of the second display partition AA2 includes a conduction level, the partition enable signal line also provides an enable level, and the data line provides a data signal, so that the pixel circuit of the second display partition AA2 performs a data refresh operation in this period. Since the first display frame is the refresh frame of the second display partition AA2, it is essential to ensure that the second display partition AA2 can update data normally during this period to maintain the smoothness and accuracy of its display. For example, when playing a video, the second display partition may need to update the dynamic part of the video screen in the third period of each first display frame to achieve a continuous video playback effect. The first display partition AA1 may continue to maintain the stable display of some pixel circuits (such as N rows of pixel circuits) during this period, and the M rows of pixel circuits that have completed data update also maintain the updated state. Through this coordinated control of partitions and periods, the entire display panel is implemented in a partition multi-frequency display mode. Efficient and stable operation, optimizing the display transition and overall display effect between different frequency partitions.

[0127] Optionally, in a first time period of the second display frame, a scan signal output to the N rows of pixel circuits in the first display partition includes a turn-on level, an enable level is provided to the partition enable signal line, and a data signal is provided to the data line; in a second time period of the second display frame, a scan signal output to the M rows of pixel circuits in the first display partition includes a turn-on level, an enable level is provided to the partition enable signal line, and a data signal is provided to the data line; in a third time period of the second display frame, a scan signal output to the pixel circuits in the second display partition includes a turn-on level, an enable level is provided to the partition enable signal line, and a data signal is provided to the data line; among multiple first display frames between two adjacent second display frames, M corresponding to at least two first display frames are not equal, and M corresponding to a first display frame that is earlier in timing is smaller than M corresponding to a first display frame that is later in timing.

[0128] Specifically, in the first period of the second display frame, the scan signal output to the N rows of pixel circuits in the first display partition AA1 includes a conduction level, which makes these pixel circuits in an activated state and ready for data update. At the same time, an enable level is provided to the partition enable signal line to create the necessary conditions for data writing, and a data signal is provided to the data line so that the N rows of pixel circuits can receive new data and perform update operations. This step ensures that at the beginning of the second display frame, some pixel circuits in the first display partition can respond and update the display content in a timely manner, which helps to maintain the continuity and dynamics of the entire display screen. For example, when displaying a screen containing dynamic elements, these N rows of pixel circuits may correspond to the area in the screen that needs to be updated first, such as the foreground elements in an animation or the key information area in an interactive interface.

[0129] In the second time period of the second display frame, the M rows of pixel circuits in the first display partition output a scanning signal with a conduction level, a partition enable signal with an enable level, and a data signal, so that the M rows of pixel circuits also perform data update. Such time-division and row-division control can more accurately manage the update sequence and timing of the pixel circuits in different parts of the first display partition according to the specific needs of the display content. For example, in the process of gradually unfolding an image, the M rows of pixel circuits may correspond to the subsequent parts of the image unfolding process and be updated according to a predetermined timing to present a natural and smooth display effect.

[0130] The third period of the second display frame operates the pixel circuit of the second display partition. Similarly, a scan signal with a conduction level is output, a partition enable signal with an enable level, and a data signal are provided to ensure that the pixel circuit of the second display partition can refresh the data. Since the second display frame is a frame in which both partitions are refreshed, it is very important to ensure the normal refresh of the second display partition during this period to maintain the consistency and accuracy of the entire picture. For example, in a multi-window display or split-screen application scenario, the second display partition may be used to display real-time updated videos, dynamic charts and other content. The update operation in the third period can ensure smooth playback and accurate display of these contents.

[0131] Fig.12 FIG. 1 is a flow chart of another method for driving a display panel provided by an embodiment of the present invention. Fig.12 As shown, the driving method includes:

[0132] S501, providing a partition enable signal to a partition enable signal line, so that the shift register outputs a scan signal to a correspondingly connected pixel circuit according to the partition enable signal, so as to control the refresh frequency of the correspondingly connected pixel circuit, thereby realizing a partition multi-frequency display mode.

[0133] Wherein, the scan signal output by at least one shift register includes a first conduction level of a partition enable signal;

[0134] S502 , in at least one frame of the partition multi-frequency display mode, before controlling the scanning signal output by the first shift register corresponding to the second display partition to be the first conduction level, providing a first conduction level to the partition enable signal line.

[0135] Among them, the partition enable signal line is set to the partition enable signal line connected to the first shift register corresponding to the second display partition; wherein, in the partition multi-frequency display mode, the refresh frequency of the second display partition is greater than the refresh frequency of the first display partition; the first shift register corresponding to the second display partition is the shift register connected to the first row of pixel circuits in the second display partition; the pixel circuit is used to write the data signal on the data line according to the received first conduction level.

[0136] Optionally, in at least part of the frames of the partition multi-frequency display mode, the time at which the first conduction level is provided to the set partition enable signal line is gradually increased or decreased compared to the time at which the first shift register corresponding to the second display partition outputs the first conduction level.

[0137] Optionally, the partitioned multi-frequency display mode includes a first display frame and a second display frame, the first display frame is a holding frame for at least part of the row pixel circuits in the first display partition, and is a refresh frame for the second display partition; the second display frame is a refresh frame for the first display partition and the second display partition.

[0138] Optionally, n first display frames between adjacent second display frames are divided into a plurality of display sub-periods; n is less than or equal to the difference between the refresh frequency of the second display partition and the refresh frequency of the first display partition; the display sub-period includes a plurality of first display frames. In at least one display sub-period, the time for providing the first conduction level to the set partition enable signal line is controlled to be gradually increased or gradually decreased in a manner of changing every d frames compared to the time when the first shift register corresponding to the second display partition outputs the first conduction level; wherein the display sub-period includes a plurality of first display frames; wherein d is less than n;

[0139] Optionally, in a previous display sub-period in adjacent display sub-periods, the time before which the first shift register corresponding to the second display sub-period outputs the first conduction level to provide the first conduction level to the set partition enable signal line is controlled to gradually increase or gradually decrease in a manner of changing every d frames. In a subsequent display sub-period in adjacent display sub-periods, the time before which the first shift register corresponding to the second display sub-period outputs the first conduction level to provide the first conduction level to the set partition enable signal line is controlled to gradually decrease or gradually increase in a manner of changing every d frames;

[0140] Optionally, the number of first display frames included in the display sub-periods is equal.

[0141] Optionally, in at least part of the frames of the partitioned multi-frequency display mode, the time at which the first conduction level is provided to the set partition enable signal line is gradually increased or decreased in advance compared to the time at which the first shift register corresponding to the second display partition outputs the first conduction level, in a manner that changes every d frames, where d is greater than or equal to 0.

[0142] Optionally, in at least part of the frames of the partition multi-frequency display mode, the time for providing the first conduction level to the set partition enable signal line is controlled to gradually increase compared with the time for the first shift register corresponding to the second display partition to output the first conduction level.

[0143] Fig.13 1 is a working timing diagram of a display panel provided by an embodiment of the present invention. Fig.13As shown, optionally, in the first frame F01 of the partition multi-frequency display mode, a partition enable signal VFE and a data signal Vdata corresponding to the refresh frequency of the display partition are provided to the driving signal line. Fig.13 The case where the first frame of a display partition is a refresh frame is schematically shown.

[0144] Optionally, in at least part of the first n frames of the partition multi-frequency display mode, the partition enable signal line connected to the first shift register corresponding to the second display partition is controlled to provide the first conduction level NVGH1 in advance of the time when the scan signal output by the first shift register corresponding to the second display partition is the first conduction level. Exemplarily, n=5, in the first 5 frames under the partition multi-frequency display mode, the second frame F02, the third frame F03 and the fourth frame F04 provide the first conduction level NVGH1 to the partition enable signal line connected to the first shift register corresponding to the second display partition in advance of the time when the scan signal output by the first shift register corresponding to the second display partition is the first conduction level NVGH1. The second display partition starts from the 960th row of pixel circuits. In the second frame F2, the time when the first conduction level NVGH1 is provided to the partition enable signal line connected to the first shift register corresponding to the second display partition is the same as the time when the first shift register corresponding to the second display partition outputs the scan signal as the first conduction level NVGH1. In the third frame, the time for providing the first conduction level NVGH1 to the partition enable signal line connected to the first shift register corresponding to the second display partition is the time for opening the scanning time of 8 rows of pixel circuits in advance relative to the second frame F2, that is, in the third frame F3, the pixel circuit in the 952nd row provides the first conduction level NVGH1 to the partition enable signal line connected to the first shift register corresponding to the second display partition. In the fourth frame F4, the time for providing the first conduction level NVGH1 to the partition enable signal line connected to the first shift register corresponding to the second display partition is the time for opening the scanning time of 16 rows of pixel circuits in advance relative to the second frame F2, that is, in the fourth frame F4, the pixel circuit in the 944th row provides the first conduction level NVGH1 to the partition enable signal line connected to the first shift register corresponding to the second display partition. This gradual adjustment method can effectively reduce display anomalies near the partition boundary. When the second display partition starts to start, if the pixel circuit near its boundary receives a suddenly changing signal, it is easy to have problems such as flickering and bright lines. Through this setting of gradually increasing the advance time, the pixel circuit near the boundary can more smoothly transition from the display mode of one partition to the display mode of the second display partition. For example, when switching from a low refresh rate partition to a second display partition, the boundary pixel circuit can gradually adapt to the new refresh rate change within multiple frames, thereby improving the display quality.

[0145] Optionally, in at least one frame of the partition multi-frequency display mode, before the first shift register corresponding to the second display partition is controlled to output the first conduction level NVGH1 of the partition enable signal VFE, the data signal Vdata is output to the data line in the first output mode; wherein the data signal Vdata output to the data line in the first output mode has a jump. Exemplarily, in the first 5 frames in the partition multi-frequency display mode, the third frame F3 and the fourth frame F4 output the data signal Vdata to the data line in the first output mode before the first shift register corresponding to the second display partition is controlled to output the first conduction level NVGH1 of the partition enable signal VFE. Outputting the data signal with a jump to the data line in advance can make the load of the data driver more balanced. During the partition switching process, if the data signal is not prepared in advance or changes suddenly, the data driver may face the problem of sudden load changes. For example, in the partition multi-frequency display mode, the data driver needs to adjust the output according to the refresh frequency and data requirements of different partitions. By outputting the data signal with a jump in advance, the data driver can gradually adjust the output power in multiple frames to avoid excessive load in a certain frame, thereby ensuring the stable operation of the data driver. The data signal jump is coordinated with the advance adjustment of the partition enable signal and the scan signal, so that the data signal can better match the refresh frequency and scan mode of the second display partition. When the partition is switched, the data signal needs to adapt to the new partition display requirements. For example, when the refresh frequency of the second display partition is high, the data signal jump can make it better meet the data writing requirements of the pixel circuit in the second display partition in terms of frequency, amplitude, etc., thereby improving the display effect.

[0146] Based on the same inventive concept, an embodiment of the present invention further provides a display device, referring to Figure 3 and Figure 4 The display device includes a display panel 01 and a display driving module 02. The display panel 01 includes at least two display partitions, and the at least two display partitions include a first display partition AA1 and a second display partition AA2. Figure 3 In the second direction Y), the first display partition AA1 and the second display partition AA2 are adjacent, each display partition includes a plurality of pixel circuits PX, and the pixel circuit PX is electrically connected to the data line DL; the display panel also includes a gate drive circuit 11 and at least one partition enable signal line ENL, the gate drive circuit 11 includes a plurality of cascaded shift registers 10, the shift register 10 is electrically connected to the partition enable signal line ENL, and the shift register 10 is used to control the refresh frequency of the correspondingly connected pixel circuit PX according to the partition enable signal of the partition enable signal line ENL.

[0147] The display driving module 02 is used to provide a partition enable signal to the partition enable signal line ENL, so that the shift register 10 outputs a scan signal to the corresponding pixel circuit PX according to the partition enable signal to control the refresh frequency of the corresponding pixel circuit PX, thereby realizing a partition multi-frequency display mode.

[0148] In which, the scanning signal output by at least one shift register 10 includes a first conduction level; in at least one frame of the partitioned multi-frequency display mode, before controlling the scanning signal output by the first shift register 10 corresponding to the second display partition to be the first conduction level, a driving signal corresponding to the driving mode of the second display partition is provided to the driving signal line; wherein the driving signal line includes a partition enable signal line ENL and / or a data line DL.

[0149] In the partition multi-frequency display mode, the refresh frequency of the second display partition AA2 is greater than the refresh frequency of the first display partition AA1; the first shift register 10 corresponding to the second display partition AA2 is the shift register 10 connected to the first row of pixel circuits PX in the second display partition AA2; the pixel circuit PX is used to write the data signal on the data line DL according to the received first conduction level; in the driving mode of the second display partition AA2, the level on the partition enable signal line ENL is the enable level, and the data line DL transmits the data signal. .

[0150] Optionally, the display device may be a mobile phone, a computer, a television, a smart wearable display device, etc., and the embodiments of the present invention do not specifically limit this. The technical principle and technical effect of the display device and the display panel driving method provided by any embodiment of the present invention are similar. The similarities can be referred to the explanation of the display panel driving method, which will not be repeated here.

[0151] Optionally, continue to refer to Figure 3, the enable level is the first conduction level; in the partition multi-frequency display mode, the scan signal output by at least one shift register includes the first conduction level of the partition enable signal; the display driving module 02 includes a first driving unit 021, the first driving unit 021 is used to provide the first conduction level to the set partition enable signal line before controlling the scan signal output by the first shift register corresponding to the second display partition AA2 to be the first conduction level within at least one frame of the partition multi-frequency display mode; wherein the set partition enable signal line is the partition enable signal line ENL connected to the first shift register corresponding to the second display partition AA2. And / or, the display driving module 02 includes a second driving unit 022, the second driving unit 022 is used to output the data signal to the data line DL in the first output mode before controlling the first shift register corresponding to the second display partition AA2 to output the first conduction level of the partition enable signal within at least one frame of the partition multi-frequency display mode; wherein the data signal output to the data line DL in the first output mode has a jump.

[0152] Continue to refer Figure 7 Optionally, the shift register 10 includes a stage transmission unit 220 and an output unit 230, and the stage transmission unit 220 is used to transmit the second conduction level NVGH2 stage by stage. The control end of the output unit 230 is electrically connected to the intermediate node of the stage transmission unit 220, and the potential of the intermediate node is used to control the stage transmission unit 220 to output the second conduction level NVGH2 or the shutdown level NVGL. The control end of the output unit 230 is electrically connected to the intermediate node of the stage transmission unit 220, and the potential of the intermediate node is used to control the stage transmission unit 220 to output the second conduction level NVGH2 or the shutdown level NVGL; the control end of the output unit 230 is electrically connected to the intermediate node, the first input end of the output unit 230 is electrically connected to the partition enable signal line, the second input end of the output unit 230 is connected to the shutdown level NVGL, and the output end of the output unit 230 is electrically connected to at least one row of pixel circuits.

[0153] Specifically, the intermediate node includes a first intermediate node N1 and a second intermediate node N2. In any level of the shift register 10, the level transmission unit 220 is electrically connected to the first intermediate node N1 and the second intermediate node N2, respectively, and is used to output the second on-level NVGH2 or the off-level NVGL as a level transmission signal according to the potential of the first intermediate node N1 and the second intermediate node N2. The level transmission signal is used as an input signal of the next level shift register 10. The cascade connection between the various levels of the shift register 10 can be as follows: Figure 6As shown, the first-stage shift register 101 receives the input signal EIN, and outputs the first-stage transfer signal Carry1 and the first-stage scan signal GOUT1 according to the input signal EIN, the clock signal ECK and the partition enable signal VFE. The first-stage transfer signal Carry1 is transmitted to the second-stage shift register 102 as the second-stage input signal EIN2. The second-stage shift register 102 outputs the second-stage transfer signal Carry2 (as the input signal EIN3 of the third-stage shift register) and the second-stage scan signal GOUT2 according to the second-stage input signal EIN2, the clock signal ECK and the partition enable signal VFE, and so on.

[0154] Exemplarily, the output unit 230 may include a first control terminal, a second control terminal, a first input terminal, a second input terminal, and an output terminal. The first control terminal is electrically connected to the first intermediate node N1, the second control terminal is electrically connected to the second intermediate node N2, the first input terminal is electrically connected to the partition enable signal line for receiving the partition enable signal VFE, the second input terminal receives the shutdown level NVGL, and the output terminal outputs the scan signal. Then, the output unit 230 may control whether the first input terminal is connected to the output terminal according to the potential of the first control terminal (i.e., the first intermediate node N1), thereby controlling whether the level of the partition enable signal VFE is output as a scan signal; and control whether the second input terminal is connected to the output terminal according to the potential of the second control terminal (i.e., the second intermediate node N2), thereby controlling whether the shutdown level NVGL is output as a scan signal.

[0155] Exemplarily, the first on-level NVGH1 is the on-potential of the functional module connected to the scan signal in the pixel circuit, and the off-level NVGL is the off-potential of the functional module connected to the scan signal in the pixel circuit, and the functional module is, for example, a functional module that controls the data voltage writing process of the gate of the driving transistor in the pixel circuit. The first on-level NVGH1 and the off-level NVGL can both be DC voltage signals. Exemplarily, if the transistor connected to the scan signal is an N-type transistor, the first on-level NVGH1 is a high potential, and the off-level NVGL is a low potential.

[0156] Specifically, when the output unit 230 controls the connection between the second input terminal and the output terminal according to the potential of the second control terminal, if the level of the partition enable signal VFE is the first conduction level NVGH1, then the scan signal is also at a high potential, which is equivalent to the scan signal including a conduction pulse in the display frame; if the level of the partition enable signal VFE is the off level NVGL at this time, then the partition enable signal VFE cannot provide a high potential to the output terminal of the output unit 230, then the scan signal maintains a low potential, which is equivalent to the scan signal not including a conduction pulse in the display frame. Therefore, by controlling the potential jump of the partition enable signal VFE, whether the output unit 230 outputs a conduction pulse is controlled, and the refresh frequency of the pixel circuit is controlled.

[0157] Optionally, the shift register 10 further includes: a driving control unit 210, the driving control unit 210 is used to control the potential of the first intermediate node N1 and the second intermediate node N2 according to the clock signal ECK and the input signal. The first intermediate node N1 and the second intermediate node N2 are respectively the first output terminal and the second output terminal of the driving control unit 210. The clock signal ECK can be understood as a general term for all clock signals connected to the driving control unit 210, and may include multiple clock signals with alternating high and low potentials.

[0158] It should be noted that the partition enable signal VFE takes effect during the time period when the stage transfer unit 220 outputs the second conduction level NVGH2. Controlling the potential of the partition enable signal VFE during this time period can control whether the output end of the shift register can output the conduction potential in a frame display.

[0159] Fig.14 Schematic diagram of a shift register provided by an embodiment of the present invention. Figure 7 and Fig.14 Optionally, the output unit 230 includes: a first transistor M1 and a second transistor M2. The gate of the first transistor M1 serves as a first control terminal, and the gate of the second transistor M2 serves as a second control terminal; the first electrode of the first transistor M1 serves as a first input terminal, the first electrode of the second transistor M2 serves as a second input terminal, and the second electrode of the first transistor M1 and the second electrode of the second transistor M2 are electrically connected to the output terminal of the output unit 230. In this embodiment, the output unit 230 is configured to include two transistors, which respectively control whether the partition enable signal VFE and the shutdown level NVGL are output as the scanning signal GOUT, so that the output unit 230 has a simple structure and is easy to implement.

[0160] Optionally, the level transmission unit 220 includes: a third transistor M3 and a fourth transistor M4. The gate of the third transistor M3 serves as the first control terminal of the level transmission unit 220 and is electrically connected to the second intermediate node N2; the first electrode of the third transistor M3 serves as the first input / output terminal of the level transmission unit 220 and is connected to the turn-off level NVGL, and the second electrode of the third transistor M3 serves as the output terminal of the level transmission unit 220 and is used to output the level transmission signal Carry. The gate of the fourth transistor M4 serves as the second control terminal of the level transmission unit 220 and is electrically connected to the first intermediate node N1; the first electrode of the fourth transistor M4 serves as the second input terminal of the level transmission unit 220 and is connected to the second conduction level NVGH2; the second electrode of the fourth transistor M4 is electrically connected to the second electrode of the third transistor M3. In this embodiment, the level transmission unit 220 includes two transistors, which respectively control whether the second conduction level NVGH2 and the turn-off level NVGL are output as the level transmission signal Carry, so that the level transmission unit 220 has a simple structure and is easy to implement.

[0161] The driving control unit 210 includes part or all of the thirteenth transistor M13 to the twenty-third transistor M23, the first capacitor C1, the second capacitor C2 and the third capacitor C3, wherein the first end of the eighteenth transistor M18, the control end of the seventeenth transistor M17, the control end of the sixteenth transistor M16 and the control end of the thirteenth transistor M13 are all connected to the turn-off level NVGL, the control end of the eighteenth transistor M18 and the control end of the twentieth transistor M20 are electrically connected to the first clock signal terminal ECK1, the first end of the fifteenth transistor M15, the control end of the fourteenth transistor M14, the control end of the twenty-second transistor M22 and the first end of the second capacitor C2 are electrically connected to the second clock signal terminal ECK2, the first end of the twenty-first transistor M21 and the first end of the twenty-third transistor M23 are all connected to the second conduction level NVGH2, the first end of the twentieth transistor M20 is connected to the input signal EIN, the first end of the eleventh transistor M11 is connected to the second conduction level NVGH2, the second end of the eleventh transistor M11 outputs the stage transmission signal Carry, and the first end of the twelfth transistor M12 is connected to the turn-off level NVGL.

[0162] For example, the first clock signal terminal of the odd-numbered shift register and the second clock signal terminal of the even-numbered shift register are connected to the first clock signal line, and the second clock signal terminal of the odd-numbered shift register and the first clock signal terminal of the even-numbered shift register are connected to the second clock signal line.

[0163] Optionally, in at least one frame of the partition multi-frequency display mode, before the control setting level transmission unit outputs the second conduction level NVGH2, the first conduction level NVGH1 of the partition enable signal VFE is provided to the set partition enable signal line. The set level transmission unit is the level transmission unit 220 of the shift register 10 connected to the first row of pixel circuits in the second display partition AA2.

[0164] Fig.15 is a schematic diagram of a pixel circuit provided by an embodiment of the present invention, with reference to Fig.15 Optionally, the pixel circuit PX includes a driving module 110 and a threshold compensation module 160, the threshold compensation module 160 is connected between the control terminal G and the first terminal D of the driving module 110, the control terminal of the threshold compensation module 160 is electrically connected to the output terminal of the shift register, and the threshold compensation module 160 is used to compensate for the threshold voltage of the driving module 110 during the compensation stage.

[0165] The pixel circuit PX also includes a first initialization module 130, which is connected between the first end of the light-emitting module 140 and the first initialization signal line. The first initialization module 130 is used to respond to the pulse signal of the first scanning signal S1 on the first scanning line and transmit the first initialization voltage Vref1 on the first initialization signal line to the first end of the light-emitting module 140.

[0166] Optionally, the pixel circuit PX further includes a data writing module 150, which is connected between the data line and the second terminal S of the driving module 110. The data writing module 150 is used to write the data signal Vdata to the control terminal G of the driving module 110 during the data writing phase.

[0167] In some optional embodiments of the present invention, the first conduction level NVGH1 is a signal that turns on the threshold compensation module 160 in the pixel circuit PX; in another part of the optional embodiments of the present invention, the first conduction level NVGH1 is a signal that turns on the data writing module 150 and the threshold compensation module 160 in the pixel circuit PX.

[0168] Optionally, the pixel circuit PX further includes a first light-emitting control module 181 and / or a second light-emitting control module 182, wherein the first light-emitting control module 181 is connected between the first power line L1 and the second end S of the driving module 110, and the second light-emitting control module 182 is connected between the first end D of the driving module 110 and the first end of the light-emitting module 140. The first light-emitting control module 181 and the second light-emitting control module 182 are used to be turned on in the light-emitting stage so that the driving module 110 drives the light-emitting module 140 to emit light, and the second end of the light-emitting module 140 is electrically connected to the second power line L2. The driving module 110 is connected between the first power line L1 and the first end of the light-emitting module 140. The driving module 110 is used to generate a driving current in the light-emitting stage to drive the light-emitting module 140 in the sub-pixel to emit light.

[0169] The control end of the threshold compensation module 160 is electrically connected to the output end of the output unit 230. When the output unit 230 of the shift register outputs the first on level to the threshold compensation module 160, the threshold compensation module 160 is turned on. When the data writing module 150 is also turned on, the data voltage can be written to the control end of the driving module 110 through the data writing module 150, the driving module 110 and the threshold compensation module 160. When the output unit 230 of the shift register outputs the off level to the threshold compensation module 160, the threshold compensation module 160 is turned off, and the data voltage cannot be written to the control end of the driving module 110. In this way, the refresh frequency of the pixel circuit can be controlled. The threshold compensation module 160 is connected between the second end D and the control end G of the driving module 110, and the threshold compensation module 160 is used to perform threshold compensation on the driving module 110 in response to the third scanning signal S3 on the third scanning line. It should be noted that in some optional embodiments of the present invention, in the refresh frame and the hold frame of the pixel circuit, the scan lines connected to the data writing module 150 are all at an effective level, so that the data writing module is turned on; and in the refresh frame of the pixel circuit, the output unit 230 of the shift register connected to the pixel circuit outputs a first conduction level, so that the threshold compensation module 160 is turned on and the data voltage is written; in the hold frame of the pixel circuit, the output unit 230 of the shift register connected to the pixel circuit outputs an off level, so that the threshold compensation module 160 is turned off. In this case, the pixel circuit data writing frequency, that is, the refresh frequency, is mainly controlled by the threshold compensation module 160. In other optional embodiments, in the refresh frame of the pixel circuit, the scan line connected to the data writing module 150 is at an effective level, so that the data writing module 150 is turned on; in the hold frame of the pixel circuit, the scan line connected to the data writing module 150 is at an off level, so that the data writing module 150 is turned off, and the data writing module 150 and the threshold compensation module 160 jointly control the data writing frequency of the pixel circuit, that is, the refresh frequency of the pixel circuit. Optionally, the pixel circuit PX further includes a storage module 170 , and the storage module 170 is connected between the first power line L1 and the control terminal G of the driving module 110 .

[0170] Specifically, the first power line L1 is used to transmit a first power voltage VDD, and the second power line L2 is used to transmit a second power voltage VSS. The first power voltage VDD may be greater than the second power voltage VSS. When the connection path between the first power line L1 and the second power line L2 is turned on, the driving module 110 drives the light-emitting module 140 to emit light. The working process of the pixel circuit at least includes a first initialization stage, a data writing stage, and a light-emitting stage.

[0171] In the first initialization stage, the first initialization module 130 is turned on in response to the first scan signal S1, and transmits the first initialization voltage Vref1 to the first end of the light emitting module 140 to initialize the potential of the first end of the light emitting module 140. In the data writing stage, the data writing module 150 is turned on in response to the second scan signal S2, and transmits the data signal Vdata on the data line DL to the second end S of the driving module 110, and writes the data signal Vdata to the control end G of the driving module 110 through the threshold compensation module 160. In the light emitting stage, the connection path between the first power line L1 and the second power line L2 is controlled to be turned on through the first light emitting control module 181 and the second light emitting control module 182, so that the driving module 110 can drive the light emitting module 140 to emit light.

[0172] Fig.16 is a schematic diagram of the structure of another pixel circuit provided by an embodiment of the present invention. Fig.16 On the basis of the above technical solution, optionally, the pixel circuit PX further includes a second initialization module 120, and the display device further includes: a second initialization signal line, the second initialization module 120 is connected between the second initialization signal line and the first terminal D of the driving module 110, the control terminal of the second initialization module 120 is electrically connected to the first scanning line, and the second initialization module 120 is used to respond to the pulse signal of the first scanning signal S1 on the first scanning line, and transmit the second initialization voltage Vref2 on the second initialization signal line to the first terminal D of the driving module 110. In the second initialization stage, the second initialization module 120 is turned on in response to the first scanning signal S1 to reset the first terminal D of the driving module 110.

[0173] Optionally, the pixel circuit PX further includes a third initialization module 190. Optionally, the scan line GL further includes a plurality of fourth scan lines, and the fourth scan lines are connected to the control terminals of the third initialization modules 190 in the pixel circuits PX of corresponding rows.

[0174] Optionally, the display device further includes: a third initialization signal line, a third initialization module 190 connected between the third initialization signal line and the first terminal D of the driving module 110, and the third initialization module 190 is used to respond to the fourth scan signal S4 on the fourth scan line, and transmit the third initialization voltage Vref3 on the third initialization signal line to the control terminal G of the driving module 110 via the threshold compensation module 160. Optionally, the third initialization module 190 can also be directly electrically connected to the control terminal G of the driving module 110, and the third initialization module 190 is connected between the third initialization signal line and one end of the threshold compensation module 160 connected to the control terminal G of the driving module 110. The third initialization module 190 is used to respond to the fourth scan signal S4 on the fourth scan line, and transmit the third initialization voltage Vref3 on the third initialization signal line directly to the control terminal G of the driving module 110. In the third initialization stage, the third initialization module 190 is turned on in response to the fourth scan signal S4 to reset the control terminal G of the driving module 110.

[0175] Specifically, the first initialization module 130 includes a fifth transistor M5, a gate of the fifth transistor M5 is connected to the first scan line G1, a first electrode of the fifth transistor M5 is connected to the first initialization signal line, a second electrode of the fifth transistor M5 is connected to the first end of the light-emitting module 140, and the fifth transistor M5 is used to transmit the first initialization voltage Vref1 on the first initialization signal line to the first end of the light-emitting module 140 in the first initialization stage.

[0176] Optionally, the second initialization module 120 includes a sixth transistor M6, a gate of the sixth transistor M6 is connected to the first scan line, a first electrode of the sixth transistor M6 is connected to the second initialization signal line, a second electrode of the sixth transistor M6 is connected to the first end D of the driving module 110, and the sixth transistor M6 is used to transmit the second initialization voltage Vref2 on the second initialization signal line to the first end D of the driving module 110 in the second initialization stage.

[0177] Optionally, the driving module 110 includes a seventh transistor M7 (i.e., a driving transistor), the data writing module 150 includes an eighth transistor M8, the threshold compensation module 160 includes a ninth transistor M9, the third initialization module 190 includes a tenth transistor M10, the first light-emitting control module 181 includes an eleventh transistor M11, the second light-emitting control module 182 includes a twelfth transistor M12, the light-emitting module 140 includes a light-emitting diode D1, and the storage module 170 includes a storage capacitor Cst. The gate of the twelfth transistor M12 is connected to the second scan line, the first electrode of the twelfth transistor M12 is connected to the data line, the second electrode of the twelfth transistor M12 is connected to the first electrode of the eleventh transistor M11, the gate of the ninth transistor M9 is connected to the third scan line, the first electrode of the ninth transistor M9 is connected to the second electrode of the eleventh transistor M11, and the second electrode of the ninth transistor M9 is connected to the gate of the eleventh transistor M11; the gate of the tenth transistor M10 is connected to the fourth scan line, the first electrode of the tenth transistor M10 is connected to the second initialization signal line, and the second electrode of the tenth transistor M10 is connected to the first electrode of the ninth transistor M9. The gate of the eleventh transistor M11 and the gate of the twelfth transistor M12 are both connected to the light control signal line, the first electrode of the eleventh transistor M11 is connected to the first power line L1, the second electrode of the eleventh transistor M11 is connected to the first electrode of the eleventh transistor M11, the first electrode of the twelfth transistor M12 is connected to the second electrode of the eleventh transistor M11, the second electrode of the twelfth transistor M12 is connected to the first electrode of the light emitting diode D1, and the second electrode of the light emitting diode D1 is connected to the second power line L2; the first electrode of the capacitor C is connected to the first power line L1, and the second electrode of the capacitor C is connected to the gate of the eleventh transistor M11. Here, the first electrode of the light emitting diode D1 can be an anode, and the second electrode can be a cathode. The ninth transistor M9 and the tenth transistor M10 can be N-type tubes or P-type tubes, and the remaining tubes are all P-type tubes. Fig.15 Only the case where the ninth transistor M9 and the tenth transistor M10 are N-type transistors is shown. For example, the ninth transistor M9 and the tenth transistor M10 can both be metal oxide transistors. The advantage of such a setting is that the leakage problem of the gate of the eleventh transistor M11 can be reduced, which is conducive to maintaining the stability of the gate voltage of the eleventh transistor M11.

[0178] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for driving a display panel, characterized in that: The display panel includes at least two display partitions, the at least two display partitions include a first display partition and a second display partition, the first display partition and the second display partition are adjacent to each other along the extension direction of the data line, each of the display partitions includes a plurality of pixel circuits, and the pixel circuits are electrically connected to the data line; the display panel also includes a gate drive circuit and at least one partition enable signal line, the gate drive circuit includes a plurality of cascaded shift registers, and the shift registers are electrically connected to the partition enable signal lines accordingly; The driving method comprises: Providing a partition enable signal to the partition enable signal line, so that the shift register outputs a scan signal to the correspondingly connected pixel circuit according to the partition enable signal, so as to control the refresh frequency of the correspondingly connected pixel circuit, thereby realizing a partition multi-frequency display mode; wherein the scan signal output by at least one of the shift registers includes a first conduction level; In at least one frame of the partition multi-frequency display mode, before controlling the scanning signal output by the first shift register corresponding to the second display partition to be the first conduction level, providing a driving signal corresponding to the driving mode of the second display partition to the driving signal line; wherein the driving signal line includes the partition enable signal line and / or the data line; Wherein, in the partition multi-frequency display mode, the refresh frequency of the second display partition is greater than the refresh frequency of the first display partition; the first shift register corresponding to the second display partition is the shift register connected to the first row of pixel circuits in the second display partition; the pixel circuit is used to write the data signal on the data line according to the received first conduction level; wherein, in the driving mode of the second display partition, the level on the partition enable signal line is the enable level, and the data line transmits the data signal.

2. The method for driving a display panel according to claim 1, wherein: The enable level is the first conduction level; in the partition multi-frequency display mode, the scanning signal output by at least one of the shift registers includes the first conduction level of the partition enable signal; in at least one frame of the partition multi-frequency display mode, before controlling the scanning signal output by the first shift register corresponding to the second display partition to be the first conduction level, providing a driving signal line with a driving signal corresponding to the driving mode of the second display partition, including: In at least one frame of the partition multi-frequency display mode, before controlling the scanning signal output by the first shift register corresponding to the second display partition to be the first conduction level, providing the first conduction level to the set partition enable signal line; wherein the set partition enable signal line is the partition enable signal line connected to the first shift register corresponding to the second display partition; Preferably, in a first frame of the partitioned multi-frequency display mode, a driving signal corresponding to a refresh frequency of the second display partition is provided to the driving signal line.

3. The method for driving a display panel according to claim 2, wherein: The method of providing the first conduction level to the set partition enable signal line before controlling the scanning signal output by the first shift register corresponding to the second display partition to be the first conduction level in at least one frame of the partition multi-frequency display mode includes: In at least part of the frames of the partition multi-frequency display mode, controlling the time for providing the first conduction level to the set partition enable signal line to be gradually increased or decreased compared to the time when the first shift register corresponding to the second display partition outputs the first conduction level; Preferably, in at least part of the frames of the partition multi-frequency display mode, the time at which the first conduction level is provided to the set partition enable signal line is controlled to be advanced compared to the time at which the first shift register corresponding to the second display partition outputs the first conduction level in advance, and the time is gradually increased or gradually decreased in a manner of changing every d frames, where d is greater than or equal to 0; Preferably, in at least part of the frames of the partition multi-frequency display mode, the time of providing the first conduction level to the set partition enable signal line is controlled to gradually increase compared with the time when the first shift register corresponding to the second display partition outputs the first conduction level; The partition multi-frequency display mode includes a first display frame and a second display frame, wherein the first display frame is a holding frame for at least part of the row pixel circuits in the first display partition and is a refresh frame for the second display partition; the second display frame is a refresh frame for the first display partition and the second display partition; Preferably, n first display frames between adjacent second display frames are divided into a plurality of display sub-periods; n is less than or equal to the difference between the refresh frequency of the second display partition and the refresh frequency of the first display partition; the display sub-period includes a plurality of the first display frames; In at least one of the display sub-periods, the time at which the first conduction level is provided to the set partition enable signal line is controlled to be gradually increased or gradually decreased in a manner of changing every d frames compared to the time at which the first shift register corresponding to the second display partition outputs the first conduction level in advance; wherein the display sub-period includes a plurality of the first display frames; wherein d is less than n; Preferably, in a previous display sub-period in the adjacent display sub-periods, the time at which the first conduction level is provided to the set partition enable signal line is controlled to be gradually increased or gradually decreased in a manner of changing every d frames compared to the time at which the first shift register corresponding to the second display partition outputs the first conduction level; In a subsequent display sub-period of the adjacent display sub-periods, the time for providing the first conduction level to the set partition enable signal line is controlled to gradually decrease or gradually increase in a manner of changing every d frames compared to the time when the first shift register corresponding to the second display partition outputs the first conduction level; Preferably, the number of the first display frames included in the plurality of display sub-periods is equal.

4. The method for driving a display panel according to claim 2, wherein: The method of providing the first conduction level to the set partition enable signal line before controlling the scanning signal output by the first shift register corresponding to the second display partition to be the first conduction level in at least one frame of the partition multi-frequency display mode includes: In multiple frames of the partition multi-frequency display mode, the first conduction level is provided to the set partition enable signal line at a time equal to the time in advance when the first shift register corresponding to the second display partition outputs the first conduction level.

5. The method for driving a display panel according to claim 2, wherein: The shift register comprises a level transmission unit and an output unit, wherein the level transmission unit is used to transmit the second conduction level step by step; the output unit is connected to a partition enable signal, and is used to transmit the partition enable signal to an output end of the shift register when the level transmission unit outputs the second conduction level, and the output end of the shift register is used to output the scan signal; The method of providing the first conduction level to the set partition enable signal line before controlling the scanning signal output by the first shift register corresponding to the second display partition to be the first conduction level in at least one frame of the partition multi-frequency display mode includes: In at least one frame of the partition multi-frequency display mode, before the control setting level transmission unit outputs the second conduction level, the first conduction level of the partition enable signal is provided to the set partition enable signal line; wherein the setting level transmission unit is a level transmission unit of the shift register connected to the first row of the pixel circuits in the second display partition; Preferably, the display panel includes k partition enable signal lines, the gate drive circuit includes a plurality of cascaded shift register groups, the shift register group includes k cascaded shift register units, k is an integer greater than or equal to 2, the shift register unit includes m shift registers, m is an integer greater than or equal to 1, different shift register units in the same shift register group are electrically connected to different partition enable signal lines, and different shift register groups are connected to the same k partition enable signal lines; The display partition includes a plurality of pixel circuit groups; the pixel circuit group includes k sub-pixel circuit groups, and the sub-pixel circuit group includes a plurality of rows of the pixel circuits; the sub-pixel circuit groups are electrically connected to the shift register units in a one-to-one correspondence; the output end of the first-level shift register is electrically connected to the r-row pixel circuits, where r is an integer greater than or equal to 1; Preferably, in the first display frame, the moments when the pulses of the signals of the k partition enable signal lines jump to the first conduction level are delayed in sequence; in the second display frame, the signals of the k partition enable signal lines are at the first conduction level; wherein the first display frame is a holding frame for at least part of the row pixel circuits in the first display partition, and is a refresh frame for the second display partition; the second display frame is a refresh frame for the first display partition and the second display partition; in the second display frame, the first display partition is refreshed before the second display partition; Preferably, k-1 shift register units are connected between two adjacent shift register units connected to the same partition enable signal line; Preferably, m is greater than or equal to 8, and k is greater than or equal to 4; In at least one frame of the partition multi-frequency display mode, before the control setting level transmission unit outputs the second conduction level, and after the second conduction level output by the level transmission unit of the shift register connected to the set partition enable signal line in the shift register correspondingly connected to the pixel circuit group adjacent to the second display partition in the first display partition jumps to the off level, the first conduction level of the partition enable signal is provided to the set partition enable signal line; Preferably, the number of rows of the pixel circuits in each of the pixel circuit groups is the same; Preferably, the time for providing the first conduction level to the set partition enable signal line is less than or equal to k*c*b in advance of the time for outputting the first conduction level of the first shift register corresponding to the second display partition, wherein c is the number of rows of the pixel circuits included in one pixel circuit group, and b is equal to the sum of the first conduction level pulse width time corresponding to a row of the pixel circuits and a preset time interval, wherein the preset time interval is equal to the time interval between two adjacent shift registers outputting the first conduction level; Preferably, the preset time interval is greater than or equal to 0; Preferably, in at least part of the first n frames of the partition multi-frequency display mode, the time at which the first conduction level is provided to the set partition enable signal line is gradually increased or gradually decreased compared to the time at which the set level transmission unit outputs the second conduction level; n is greater than or equal to 2; Preferably, in at least part of the first n frames of the partition multi-frequency display mode, the time for providing the first conduction level to the set partition enable signal line in advance of the second conduction level output by the set level transmission unit gradually increases.

6. The method for driving a display panel according to claim 5, characterized in that: The time in which the first conduction level of the partition enable signal is provided to the set partition enable signal line ahead of the second conduction level output by the set stage transfer unit is equal to an integer multiple of the sum of the first conduction level pulse width time output by the shift register and the preset time interval.

7. The method for driving a display panel according to any one of claims 1 to 6, characterized in that: The step of providing a driving signal corresponding to the driving mode of the second display partition to the driving signal line before controlling the scanning signal output by the first shift register corresponding to the second display partition to be the first conduction level within at least one frame of the partition multi-frequency display mode comprises: In at least one frame of the partitioned multi-frequency display mode, before the first shift register corresponding to the second display partition is controlled to output the first conduction level of the partition enable signal, a data signal is output to the data line in a first output mode; wherein the data signal output to the data line in the first output mode has a jump.

8. The method for driving a display panel according to claim 7, wherein: The shift register comprises a level transmission unit and an output unit, wherein the level transmission unit is used to transmit the second conduction level step by step; the output unit is connected to a partition enable signal, and is used to transmit the partition enable signal to an output end of the shift register when the level transmission unit outputs the second conduction level, and the output end of the shift register is used to output the scan signal; The method of outputting a data signal to the data line in a first output mode before controlling the first shift register corresponding to the second display partition to output the first conduction level of the partition enable signal in at least one frame of the partition multi-frequency display mode comprises: In at least one frame of the partitioned multi-frequency display mode, before the first level transmission unit corresponding to the second display partition is controlled to output the second conduction level, a data signal is output to the data line in the first output mode; wherein the first level transmission unit corresponding to the second display partition is the level transmission unit of the shift register connected to the first row of pixel circuits in the second display partition.

9. The method for driving a display panel according to claim 8, wherein: Also includes: In at least one frame of the partition multi-frequency display mode, when the level transfer unit of the shift register corresponding to the first display partition is controlled to output the second conduction level, a DC level is output to the data line in a second output mode, or no signal is output to the data line; and / or, In at least one frame of the partition multi-frequency display mode, when the level transfer unit corresponding to the first display partition is controlled to output the second conduction level, an off level is provided to the partition enable signal line.

10. The method for driving a display panel according to claim 1, wherein: The time when the drive signal line is provided with the drive signal of the refresh frequency corresponding to the second display partition in advance relative to the time when the first shift register corresponding to the second display partition controls the output of the first conduction level of the partition enable signal is positively correlated with the difference in refresh frequency between the second display partition and the first display partition.

11. The method for driving a display panel according to claim 1, wherein: The partition enable signal is provided to the partition enable signal line so that the shift register outputs a scan signal to the corresponding pixel circuit according to the partition enable signal to control the refresh frequency of the corresponding pixel circuit, thereby realizing a partition multi-frequency display mode, including: By controlling the time periods of the first on-level and off-level of the partition enable signal on the partition enable signal line within a frame, the scanning signals output by different shift registers are controlled to be the first on-level or off-level to control the refresh frequency of the correspondingly connected pixel circuit, thereby realizing a partition multi-frequency display mode.

12. The method for driving a display panel according to claim 1, wherein: The partition multi-frequency display mode includes a first display frame and a second display frame, wherein the first display frame is a holding frame for at least part of the row pixel circuits in the first display partition and is a refresh frame for the second display partition; the second display frame is a refresh frame for the first display partition and the second display partition; In at least one frame of the partition multi-frequency display mode, before controlling the scanning signal output by the first shift register corresponding to the second display partition to be the first conduction level, providing a driving signal corresponding to the driving mode of the second display partition to the driving signal line, comprising: In at least one of the first display frames of the partition multi-frequency mode, before controlling the scanning signal output by the first shift register corresponding to the second display partition to be the first conduction level, providing a driving signal line with a driving signal corresponding to the driving mode of the second display partition.

13. The method for driving a display panel according to claim 1, wherein: The first display frame and the second display frame include a first time period, a second time period and a third time period respectively; In a first period of the first display frame, the scan signal output to the N rows of pixel circuits of the first display partition is continuously at an off level, a non-enable level is provided to the partition enable signal line, and a DC level is provided to the data line, or no signal is output to the data line; In a second period of the first display frame, the scan signal output to the M rows of pixel circuits of the first display partition includes a conduction level, an enable level is provided to the partition enable signal line, and a data signal is provided to the data line; In a third period of the first display frame, the scan signal output to the pixel circuit of the second display partition includes a conduction level, an enable level is provided to the partition enable signal line, and a data signal is provided to the data line; The M rows of pixel circuits are located between the N rows of pixel circuits and the second display partition; Wherein, M corresponding to at least two of the first display frames are not equal; Preferably, in the second period of the first display frame, the data signal provided to the data line is the same as the data signal corresponding to the M rows of pixel circuits in the second display frame before the second display frame; Preferably, in the first period of the second display frame, the scan signal output to the N rows of pixel circuits of the first display partition includes a conduction level, an enable level is provided to the partition enable signal line, and a data signal is provided to the data line; In a second period of the second display frame, the scan signal output to the M rows of pixel circuits in the first display partition includes a conduction level, an enable level is provided to the partition enable signal line, and a data signal is provided to the data line; In a third period of the second display frame, the scan signal output to the pixel circuit of the second display partition includes a conduction level, an enable level is provided to the partition enable signal line, and a data signal is provided to the data line; Among the multiple first display frames between two adjacent second display frames, M corresponding to at least two of the first display frames are not equal, and M corresponding to the first display frame that is earlier in sequence is smaller than M corresponding to the first display frame that is later in sequence.

14. A method for driving a display panel, characterized in that: The display panel includes at least two display partitions, the at least two display partitions include a first display partition and a second display partition, the first display partition and the second display partition are adjacent to each other along the extension direction of the data line, each of the display partitions includes a plurality of pixel circuits, and the pixel circuits are electrically connected to the data line; the display panel also includes a gate drive circuit and at least one partition enable signal line, the gate drive circuit includes a plurality of cascaded shift registers, and the shift registers are electrically connected to the partition enable signal lines accordingly; The driving method comprises: Providing a partition enable signal to the partition enable signal line, so that the shift register outputs a scan signal to the correspondingly connected pixel circuit according to the partition enable signal, so as to control the refresh frequency of the correspondingly connected pixel circuit, thereby realizing a partition multi-frequency display mode; wherein the scan signal output by at least one of the shift registers includes a first conduction level of the partition enable signal; In at least one frame of the partition multi-frequency display mode, before controlling the scanning signal output by the first shift register corresponding to the second display partition to be the first conduction level, providing the first conduction level to the set partition enable signal line; wherein the set partition enable signal line is the partition enable signal line connected to the first shift register corresponding to the second display partition; Among them, in the partitioned multi-frequency display mode, the refresh frequency of the second display partition is greater than the refresh frequency of the first display partition; the first shift register corresponding to the second display partition is the shift register connected to the first row of pixel circuits in the second display partition; the pixel circuit is used to write the data signal on the data line according to the received first conduction level.

15. The method for driving a display panel according to claim 14, characterized in that: The method of providing the first conduction level to the set partition enable signal line before controlling the scanning signal output by the first shift register corresponding to the second display partition to be the first conduction level in at least one frame of the partition multi-frequency display mode includes: In at least part of the frames of the partition multi-frequency display mode, controlling the time for providing the first conduction level to the set partition enable signal line to be gradually increased or decreased compared to the time when the first shift register corresponding to the second display partition outputs the first conduction level; The partition multi-frequency display mode includes a first display frame and a second display frame, wherein the first display frame is a holding frame for at least part of the row pixel circuits in the first display partition and is a refresh frame for the second display partition; the second display frame is a refresh frame for the first display partition and the second display partition; Preferably, n first display frames between adjacent second display frames are divided into a plurality of display sub-periods; n is less than or equal to the difference between the refresh frequency of the second display partition and the refresh frequency of the first display partition; the display sub-period includes a plurality of the first display frames; In at least one of the display sub-periods, the time at which the first conduction level is provided to the set partition enable signal line is controlled to be gradually increased or gradually decreased in a manner of changing every d frames compared to the time at which the first shift register corresponding to the second display partition outputs the first conduction level in advance; wherein the display sub-period includes a plurality of the first display frames; wherein d is less than n; Preferably, in a previous display sub-period in the adjacent display sub-periods, the time at which the first conduction level is provided to the set partition enable signal line is controlled to be gradually increased or gradually decreased in a manner of changing every d frames compared to the time at which the first shift register corresponding to the second display partition outputs the first conduction level; In a subsequent display sub-period of the adjacent display sub-periods, the time for providing the first conduction level to the set partition enable signal line is controlled to gradually decrease or gradually increase in a manner of changing every d frames compared to the time when the first shift register corresponding to the second display partition outputs the first conduction level; Preferably, the number of the first display frames included in the plurality of display sub-periods is equal.

16. The method for driving a display panel according to claim 14, wherein: In at least part of the frames of the partitioned multi-frequency display mode, the control provides a first conduction level to the set partition enable signal line, and the time is advanced compared to the time when the first shift register corresponding to the second display partition outputs the first conduction level, and the time is gradually increased or decreased in a manner of changing every d frames, where d is greater than or equal to 0.

17. The method for driving a display panel according to claim 14, wherein: In at least part of the frames of the partition multi-frequency display mode, the time of providing the first conduction level to the set partition enable signal line is controlled to gradually increase compared with the time when the first shift register corresponding to the second display partition outputs the first conduction level.

18. A display device, characterized in that: The display panel comprises a display panel and a display driving module, wherein the display panel comprises at least two display partitions, wherein the at least two display partitions comprise a first display partition and a second display partition, wherein the first display partition and the second display partition are adjacent to each other along the extension direction of the data line, and each of the display partitions comprises a plurality of pixel circuits, wherein the pixel circuits are electrically connected to the data line; the display panel further comprises a gate driving circuit and at least one partition enabling signal line, wherein the gate driving circuit comprises a plurality of cascaded shift registers, wherein the shift registers are electrically connected to the partition enabling signal lines correspondingly, and wherein the shift registers are used to control the refresh frequency of the correspondingly connected pixel circuits according to the partition enabling signal of the partition enabling signal line; The display driving module is used to provide a partition enable signal to the partition enable signal line, so that the shift register outputs a scan signal to the correspondingly connected pixel circuit according to the partition enable signal, so as to control the refresh frequency of the correspondingly connected pixel circuit, thereby realizing a partition multi-frequency display mode; wherein, the scan signal output by at least one of the shift registers includes a first conduction level; within at least one frame of the partition multi-frequency display mode, before the scan signal output by the first shift register corresponding to the second display partition is controlled to be the first conduction level, a drive signal corresponding to the drive mode of the second display partition is provided to the drive signal line; wherein, the drive signal line includes the partition enable signal line and / or the data line; Wherein, in the partition multi-frequency display mode, the refresh frequency of the second display partition is greater than the refresh frequency of the first display partition; the first shift register corresponding to the second display partition is the shift register connected to the first row of pixel circuits in the second display partition; the pixel circuit is used to write the data signal on the data line according to the received first conduction level; wherein, in the driving mode of the second display partition, the level on the partition enable signal line is the enable level, and the data line transmits the data signal.

19. The display device according to claim 18, characterized in that The enable level is the first conduction level; in the partition multi-frequency display mode, the scan signal output by at least one of the shift registers includes the first conduction level of the partition enable signal; the display driving module includes a first driving unit, and the first driving unit is used to provide the first conduction level to the set partition enable signal line before controlling the scan signal output by the first shift register corresponding to the second display partition to be the first conduction level within at least one frame of the partition multi-frequency display mode; wherein the set partition enable signal line is the partition enable signal line connected to the first shift register corresponding to the second display partition; And / or, the display driving module includes a second driving unit, which is used to output a data signal to the data line in a first output mode within at least one frame of the partition multi-frequency display mode, before controlling the first shift register corresponding to the second display partition to output the first conduction level of the partition enable signal; wherein the data signal output to the data line in the first output mode has a jump.

20. The display device according to claim 18 or 19, characterized in that: The shift register includes a stage transmission unit and an output unit, the stage transmission unit is used to transmit the second conduction level step by step; the control end of the output unit is electrically connected to the intermediate node of the stage transmission unit, and the potential of the intermediate node is used to control the stage transmission unit to output the second conduction level or the shutdown level; the control end of the output unit is electrically connected to the intermediate node, the first input end of the output unit is electrically connected to the partition enable signal line, the second input end of the output unit is connected to the shutdown level, and the output end of the output unit is electrically connected to at least one row of the pixel circuit.

21. The display device according to claim 20, characterized in that The intermediate node includes a first intermediate node and a second intermediate node, the control end of the output unit includes a first control end and a second control end, the first control end is electrically connected to the first intermediate node, and the second control end is electrically connected to the second intermediate node; the output unit includes a first transistor and a second transistor; the gate of the first transistor serves as the first control end, and the gate of the second transistor serves as the second control end; the first electrode of the first transistor serves as the first input end, the first electrode of the second transistor serves as the second input end, and the second electrode of the first transistor and the second electrode of the second transistor are electrically connected to the output end of the output unit; Preferably, the pixel circuit comprises a driving module and a threshold compensation module, the threshold compensation module is connected between the control end and the first end of the driving module, and the control end of the threshold compensation module is electrically connected to the output end of the shift register; Preferably, the pixel circuit further comprises a data writing module, wherein the data writing module is connected between the data line and the second end of the driving module; Preferably, the pixel circuit also includes a first light-emitting control module and a second light-emitting control module, the first light-emitting control module is connected between the second end of the driving module and the first power line, the second light-emitting control module is connected between the first end of the driving module and the first end of the light-emitting module, and the second end of the light-emitting module is electrically connected to the second power line.

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