Scanning driving circuit and display panel

Abstract

The invention discloses a scanning driving circuit and a display panel. The scanning driving circuit comprises a plurality of cascaded shifting registers, each shifting register comprises a gating module and a shifting module, the first input end of each gating module is used for accessing a first trigger signal, the first input end of the gating module in the first-stage shifting register is electrically connected with a first trigger signal line, and the second input end of the gating module in the second-stage shifting register is electrically connected with a second trigger signal line; the first input end of the gating module in the (i + 1) th stage of shifting register is electrically connected with the output end of the shifting module in the ith stage of shifting register, i is an integer greater than 0, the second input end of the gating module is electrically connected with a second trigger signal line, and the second trigger signal line is used for transmitting a second trigger signal; the gating module is used for outputting an enabling level of at least one of the first trigger signal and the second trigger signal to the shifting module; the shifting module is used for outputting a signal including an enable level in response to the enable signal output by the gating module. According to the embodiment of the invention, the scanning driving circuit can output scanning signals with different refresh frequencies.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a scanning drive circuit and a display panel. Background Art

[0002] With the continuous development of display technology, the functions of display products are becoming more and more diversified. For example, display panels support partitioned refresh display, that is, the display area of ​​the display panel is divided into multiple display areas, and the refresh rate of each display area can be set independently to achieve the effect of reducing the power consumption of the display panel drive.

[0003] The display area of ​​the display panel is scanned and driven by a scan driving circuit. How to design the scan driving circuit so that the scan driving circuit can perform frequency division refresh on different display areas is a technical problem faced by those skilled in the art. Summary of the invention

[0004] The embodiments of the present application provide a scan driving circuit and a display panel, wherein the scan driving circuit can output scan signals with different refresh frequencies.

[0005] In the first aspect, an embodiment of the present application provides a scan drive circuit, comprising: a plurality of cascaded shift registers, the shift register comprising a gating module and a shift module, the first input end of the gating module being used to access a first trigger signal, the first input end of the gating module in the first-stage shift register being electrically connected to a first trigger signal line, the first input end of the gating module in the i+1-stage shift register being electrically connected to an output end of the shift module in the i-stage shift register, i being an integer greater than 0, the second input end of the gating module being electrically connected to a second trigger signal line, the second trigger signal line being used to transmit a second trigger signal; the gating module being used to output an enable level of at least one of the first trigger signal and the second trigger signal to the shift module; the shift module being used to output a signal including an enable level in response to an enable signal output by the gating module.

[0006] In a second aspect, an embodiment of the present application provides a display panel, comprising a scan drive circuit as described in the embodiment of the first aspect.

[0007] According to an embodiment of the present application, the shift register includes a gating module and a shift module. The first input end and the second input end of the gating module of each shift register are respectively used to access the second trigger signal. The first input end of the gating module of the i+1-th level shift register is electrically connected to the output end of the shift module in the i-th level shift register. Even if the shift module in the i-th level shift register outputs a signal at a low refresh frequency, by controlling the second trigger signal connected to the i+1-th level shift register to include an enable signal, the shift module in the i+1-th level shift register can output a signal at a high refresh frequency, thereby enabling different shift registers in the scan drive circuit to refresh different display areas of the display panel at different refresh frequencies. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Other features, objects and advantages of the present application will become more apparent by reading the following detailed description of non-limiting embodiments with reference to the accompanying drawings, in which the same or similar reference numerals represent the same or similar features and the accompanying drawings are not drawn to scale.

[0009] Figure 1 A schematic diagram showing the structure of a scan driving circuit provided by an embodiment of the present application is shown;

[0010] Figure 2 A schematic diagram showing a structure of a shift register in a scan drive circuit provided by an embodiment of the present application is shown;

[0011] Figure 3 Another structural schematic diagram of a shift register in a scan drive circuit provided by an embodiment of the present application is shown;

[0012] Figure 4 Another structural schematic diagram of a shift register in a scan drive circuit provided by an embodiment of the present application is shown;

[0013] Figure 5 Another structural schematic diagram of a scan driving circuit provided by an embodiment of the present application is shown;

[0014] Figure 6 Another structural schematic diagram of a scan driving circuit provided by an embodiment of the present application is shown;

[0015] Figure 7 Another structural schematic diagram of a shift register in a scan drive circuit provided by an embodiment of the present application is shown;

[0016] Figure 8 A schematic diagram showing a structure of a sub-pixel in a display panel provided by an embodiment of the present application is shown;

[0017] Fig. 9 A schematic diagram showing the structure of a display panel provided by an embodiment of the present application is shown;

[0018] Fig.10 A timing diagram of a display panel provided by an embodiment of the present application is shown;

[0019] Fig.11 Another structural schematic diagram of a display panel provided by an embodiment of the present application is shown;

[0020] Fig.12 Another timing diagram of a display panel provided by an embodiment of the present application is shown;

[0021] Fig.13A schematic structural diagram of a display device provided by an embodiment of the present application is shown. DETAILED DESCRIPTION

[0022] The features and exemplary embodiments of various aspects of the present application will be described in detail below. In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only configured to explain the present application and are not configured to limit the present application. For those skilled in the art, the present application can be implemented without the need for some of these specific details. The following description of the embodiments is only to provide a better understanding of the present application by illustrating the examples of the present application.

[0023] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the statement "include..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0024] It should be understood that when describing the structure of a component, when a layer or a region is referred to as being "on" or "over" another layer or another region, it may mean that it is directly on the other layer or another region, or that other layers or regions are included between it and the other layer or another region. Moreover, if the component is turned over, the layer or a region will be "below" or "beneath" another layer or another region.

[0025] It should be understood that the term "and / or" used in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0026] In the embodiments of the present application, the term “electrically connected” may refer to a direct electrical connection between two components, or may refer to an electrical connection between two components via one or more other components.

[0027] In the embodiment of the present application, the first node, the second node and the third node are only defined for the convenience of describing the circuit structure, and the first node, the second node and the third node are not actual circuit units.

[0028] It is obvious to those skilled in the art that various modifications and changes can be made in the present application without departing from the spirit or scope of the present application. Therefore, the present application is intended to cover modifications and changes of the present application that fall within the scope of the corresponding claims (technical solutions for protection) and their equivalents. It should be noted that the implementation methods provided in the embodiments of the present application can be combined with each other without contradiction.

[0029] The embodiments of the present application provide a scan driving circuit and a display panel. The embodiments of the present application will be described below in conjunction with the accompanying drawings.

[0030] like Figure 1 The scanning driving circuit 10 provided in the embodiment of the present application includes a plurality of cascaded shift registers VSR, and the signal output by the shift register VSR is used to drive the sub-pixels of the display panel. The signal output by the i-th shift register is also used as a trigger signal for the i+1-th shift register, where i is an integer greater than 0.

[0031] The shift register VSR comprises a gating module 11 and a shifting module 12. The gating module 11 comprises a first input terminal IN1 and a second input terminal IN2. The first input terminal IN1 of the gating module 11 is used to access a first trigger signal, and the second input terminal IN2 of the gating module 11 is used to access a second trigger signal.

[0032] The first input terminal IN1 of the selection module 11 in the first stage shift register VSR(1) is electrically connected to the first trigger signal line 31, and the first input terminal IN1 of the selection module 11 in the i+1 stage shift register is electrically connected to the output terminal out1 of the shift module 12 in the i stage shift register, where i is an integer greater than 0.

[0033] Exemplarily, the other end of the first trigger signal line 31 is electrically connected to the driver chip. The first trigger signal line 31 is used to transmit the first trigger signal to the first-stage shift register VSR(1). The first trigger signal received by the first-stage shift register VSR(1) comes from the driver chip.

[0034] It can be understood that the output end out1 of the shift module 12 in the i-th shift register transmits the first trigger signal to the i+1-th shift register, that is, the first trigger signal connected to the i+1-th shift register comes from the signal output by the shift module in the i-th shift register. For example, the first trigger signal connected to the second-stage shift register VSR (2) comes from the signal output by the shift module in the first-stage shift register VSR (1), the first trigger signal connected to the third-stage shift register VSR (3) comes from the signal output by the shift module in the second-stage shift register VSR (2), the first trigger signal connected to the fourth-stage shift register VSR (4) comes from the signal output by the shift module in the third-stage shift register VSR (3), and so on. In other words, the signal output by the shift module in the previous-stage shift register serves as the first trigger signal of the next-stage shift register.

[0035] The second input terminal IN2 of the strobe module 11 is electrically connected to the second trigger signal line 32, and the second trigger signal line 32 is used to transmit the second trigger signal. The second input terminal IN2 of the strobe module 11 in each level of the shift register is electrically connected to the second trigger signal line 32.

[0036] The gating module 11 is used to output the enable level of at least one of the first trigger signal and the second trigger signal to the shift module 12; the shift module 12 is used to output a signal including the enable level in response to the enable signal output by the gating module 11. Here, the enable level of the first trigger signal and the second trigger signal refers to a level that can trigger the shift module to work. The enable level output by the shift module 12 refers to a level that can trigger the next-stage shift register to work, or the enable level output by the shift module 12 refers to a level that can trigger the next-stage shift register to work, and can control the sub-pixel to write data. Exemplarily, the enable levels of the first trigger signal and the second trigger signal include a low level, and the enable level output by the shift module 12 includes a low level.

[0037] It is understandable that, when any one of the first trigger signal and the second trigger signal connected to the gating module 11 includes an enable level, the gating module 11 can output a trigger signal including the enable level to trigger the shifting module 12 to work. When neither the first trigger signal nor the second trigger signal connected to the gating module 11 includes an enable level, the gating module 11 cannot output a trigger signal including the enable level, and the shifting module 12 does not work.

[0038] As an example, the first trigger signal and the second trigger signal connected to the selection module 11 are non-enable signals, the selection module 11 outputs a non-enable level, and the shift module 12 does not work. In this case, the shift module 12 outputs a scanning signal with a low refresh frequency.

[0039] As another example, the first trigger signal connected to the gating module 11 does not include an enable signal, and the second trigger signal connected to the gating module 11 includes an enable signal. The gating module 11 can output a trigger signal including an enable level, and the shift module 12 can work. In this case, the shift module 12 outputs a scanning signal with a high refresh frequency.

[0040] It is understandable that the first input end of the gating module in the i+1th shift register is electrically connected to the output end of the shift module in the i-th shift register, and the signal output by the shift module in the i-th shift register is used as the first trigger signal of the i+1th shift register. Even if the signal output by the shift module in the i-th shift register is a non-enable level, when the second trigger signal connected to the i+1th shift register includes an enable level, the signal output by the shift module in the i+1th shift register can still include an enable level. In other words, when the i-th shift register outputs a signal at a low refresh rate, the i+1th shift register can output a signal at high and low refresh rates.

[0041] For example, the 1st to mth shift registers are used to refresh sub-pixels in the first display area, and the m+1th to nth shift registers are used to refresh sub-pixels in the second display area, where 1<m<m+1<n, and m and n are both integers.

[0042] In the first refresh cycle, the first trigger signal controlling the access of the 1st to the mth stage shift registers and the m+1th to the nth stage shift registers includes an enable signal, so that the 1st to the mth stage shift registers and the m+1th to the nth stage shift registers can both output enable levels, and the first display area and the second display area can both be effectively refreshed and scanned.

[0043] In the second refresh cycle, the first trigger signal and the second trigger signal controlling the access of the 1st to the mth stage shift registers are both kept as non-enable signals, so that the 1st to the mth stage shift registers cannot output enable signals and the first display area cannot be refreshed and scanned.

[0044] In the second refresh cycle, the first trigger signal controlling the access of the m+1th to nth shift registers maintains a non-enable level, but the second trigger signal controlling the access of the m+1th to nth shift registers includes an enable level, so that the m+1th to nth shift registers can still output an enable level, thereby still being able to effectively refresh and scan the second display area.

[0045] That is to say, by controlling the second trigger signal connected to the shift register, the refresh frequency of the output signal of the shift register can be controlled, thereby achieving frequency-divided refresh of different display areas.

[0046] According to an embodiment of the present application, the shift register includes a gating module and a shift module. The first input end and the second input end of the gating module of each shift register are respectively used to access the second trigger signal. The first input end of the gating module of the i+1-th level shift register is electrically connected to the output end of the shift module in the i-th level shift register. Even if the shift module in the i-th level shift register outputs a signal at a low refresh frequency, by controlling the second trigger signal connected to the i+1-th level shift register to include an enable signal, the shift module in the i+1-th level shift register can output a signal at a high refresh frequency, thereby enabling different shift registers in the scan drive circuit to refresh different display areas of the display panel at different refresh frequencies.

[0047] In some embodiments, Figure 2 As shown, the gating module 11 includes an AND gate and, a first input terminal IN1 of the AND gate and is a first input terminal of the gating module 11, a second input terminal IN2 of the AND gate and is a second input terminal of the gating module 11, an output terminal of the AND gate and is an output terminal of the gating module 11, and an enable level of the first trigger signal and the second trigger signal is a low level.

[0048] Table 1 is the output logic of the AND gate, where "0" represents a low level and "1" represents a high level. When at least one of the two input terminals of the AND gate is connected to a low level, the AND gate outputs a low level; when both input terminals of the AND gate are connected to a high level, the AND gate outputs a high level.

[0049] Table 1

[0050] IN1 IN2 Output 0 0 0 1 0 0 0 1 0 1 1 1

[0051] The circuit structure of the AND gate and may adopt any existing circuit structure, and this application does not limit this.

[0052] In this embodiment, the selection module includes an AND gate. When at least one of the two input terminals of the AND gate is connected to a low level, the AND gate outputs a low level, thereby triggering the shift module to work; when both input terminals of the AND gate are connected to a high level, the AND gate outputs a high level, so that the shift module cannot receive a valid trigger signal, thereby causing the shift module to not work.

[0053] In some embodiments, Figure 3 As shown, the gating module 11 also includes a first transistor M1, a first electrode of the first transistor M1 is electrically connected to the second trigger signal line 32, a second electrode of the first transistor M1 is electrically connected to the second input terminal IN2 of the gating module 11, and a gate of the first transistor M1 is used to access the frequency cutting signal Ctrl.

[0054] The first transistor M1 can control whether the second trigger signal on the second trigger signal line 32 can be connected to the gating module 11. When the first transistor M1 is turned on, the second trigger signal line 32 is connected to the second input terminal IN2 of the gating module 11, and the second trigger signal can be transmitted to the second input terminal IN2. When the first transistor M1 is turned off, the second trigger signal line 32 is disconnected from the second input terminal IN2 of the gating module 11, and the second trigger signal cannot be transmitted to the second input terminal IN2.

[0055] Exemplarily, the frequency-cutting signal Ctrl is used to switch the frequency of the scanning signal output by the shift register. For example, the first trigger signal remains a non-enable signal, and the second trigger signal includes an enable signal. When the frequency-cutting signal Ctrl is at an enable level, the first transistor M1 is turned on, and the enable level of the second trigger signal can be transmitted to the shift module 12, the shift module 12 maintains normal operation, and the shift module 12 can output a signal with a high refresh frequency; and when the frequency-cutting signal Ctrl is at a non-enable level, the first transistor M1 is turned off, and the enable level of the second trigger signal cannot be transmitted to the shift module 12, the shift module 12 cannot work normally, and the shift module 12 outputs a signal with a low refresh frequency.

[0056] Exemplarily, the first transistor M1 is a P-type transistor, the enable level of the frequency cutting signal Ctrl is a low level, and the disable level of the frequency cutting signal Ctrl is a low level.

[0057] Exemplarily, still taking the example that the 1st to mth shift registers are used to refresh the sub-pixels of the first display area, and the m+1th to nth shift registers are used to refresh the sub-pixels of the second display area, the frequency cutting signal Ctrl connected to the first transistor in the 1st to mth shift registers is controlled to be a non-enable level, and the frequency cutting signal Ctrl connected to the first transistor in the m+1th to nth shift registers is controlled to be an enable level, so that the first display area is refreshed at a low refresh frequency, and the second display area is refreshed at a high refresh frequency.

[0058] In this embodiment, a first transistor is connected between the second input terminal of the gating module and the second trigger signal line, and the first transistor is controlled by the frequency cutting signal, which can better ensure the accuracy of the partition frequency refreshing.

[0059] In some embodiments, Figure 4 As shown, in the case where the gating module 11 includes the first transistor M1, the gating module 11 also includes a pull-up submodule 111, and the pull-up submodule 111 is electrically connected to the second input terminal IN2 of the gating module 11, and the pull-up submodule 111 is used to maintain the level of the second input terminal IN2 of the gating module 11 at a non-enabling level when the frequency cutting signal Ctrl is at a non-enabling level.

[0060] For example, the non-enable level is a high level, and the pull-up submodule 111 includes a first resistor R1, one end of the first resistor R1 is electrically connected to the second input terminal IN2 of the gating module 11, and the other end is electrically connected to the first power supply V1, and the first power supply V1 is used to provide a positive voltage. When the frequency cutting signal Ctrl is a non-enable level, the first transistor M1 is disconnected, and the positive voltage provided by the first power supply V1 is transmitted to the second input terminal IN of the gating module 11 through the first resistor R1, so as to pull up the voltage of the second input terminal IN2.

[0061] In this embodiment, by adding a pull-up submodule, it is possible to avoid the second input terminal IN2 being in a floating state when the frequency cutting signal Ctrl is at a non-enable level, so as to ensure the reliability of the gating module.

[0062] In some embodiments, Figure 5 or Figure 6 As shown, the shift module includes a control submodule 121 and a level transmission submodule 122. The input end of the control submodule 121 is electrically connected to the output end of the gating module 11. The control submodule 121 is electrically connected to the first node N1 and the second node N2. The control submodule 121 is used to control the potential of the first node N1 and the second node N2. The level transmission submodule 122 is electrically connected to the first node N1 and the second node N2. The output end out1 of the level transmission submodule 122 is the output end of the shift module. The level transmission submodule 122 is used to output a signal according to the potential of the first node N1 and the second node N2.

[0063] The output terminal out1 of the stage transmission submodule 122 in the i-th stage shift register is electrically connected to the first input terminal IN1 of the selection module in the i+1-th stage shift register. That is, the signal outputted from the output terminal out1 of the stage transmission submodule 122 in the i-th stage shift register serves as the first trigger signal of the i+1-th stage shift register. The signal outputted from the output terminal out1 of the stage transmission submodule 122 serves as the stage transmission signal.

[0064] As an example, Figure 5 As shown, the output terminal out1 of the level transmission submodule 122 is also used to electrically connect the sub-pixel 20. In this example, the signal outputted by the output terminal out1 of the level transmission submodule 122 is not only used as a level transmission signal, but also as a scanning signal of the sub-pixel 20.

[0065] As an example, Figure 6As shown, the shift register VSR further includes an output module 13, the output module 13 is electrically connected to the first node N1 and the second node N2, the output module 13 is used to output a signal according to the potentials of the first node N1 and the second node N2, and the output terminal out2 of the output module 13 is used to electrically connect the sub-pixel 20. In this example, the signal output by the output terminal out1 of the level transmission submodule 122 is used as the level transmission signal, and the signal output by the output terminal out2 of the output module 13 is used as the scanning signal of the sub-pixel 20.

[0066] Exemplarily, in the same stage of the shift register, the output terminal out1 of the stage transmission submodule 122 and the output terminal out2 of the output module 13 output the same signal.

[0067] Figure 7 The circuit structure of the control submodule 121 , the level transmission submodule 122 and the output module 13 is shown as an example. Figure 7 Each transistor is a P-type transistor, and the shift register is also connected to a first clock signal CK1, a second clock signal CK2, and a third clock signal CK3. The second clock signal CK2 and the third clock signal CK3 may be the same or different. In addition, the high-level signal VGH is a high level (e.g., approximately +7V), and the low-level signal VGL is a low level (e.g., approximately -7V).

[0068] It should be noted that the focus of the present application is not on the specific structure of the shift module and / or output module, but on the addition of a gating module. That is to say, the present application can be applied to adding a gating module on the basis of any existing shift register to achieve zone-by-zone frequency refresh.

[0069] An embodiment of the present application further provides a display panel, and the display panel includes the scan driving circuit as described in any one of the above embodiments.

[0070] The display panel provided in the embodiment of the present application has the beneficial effects of the scan driving circuit provided in the embodiment of the present application. For details, please refer to the specific description of the scan driving circuit in the above embodiments, which will not be repeated in this embodiment.

[0071] Exemplarily, the display panel may be an organic light-emitting diode (OLED) display panel. Those skilled in the art should understand that in other implementations of the present application, the display panel may also be a micro light-emitting diode (Micro LED) display panel, a mini light-emitting diode (Mini LED) display panel, etc.

[0072] The display panel includes sub-pixels. Exemplarily, the structure of the sub-pixels includes: Figure 8The "7T1C" circuit structure shown, of course, in other examples, the structure of the sub-pixel can be a "4T1C", "8T1C" or other circuit structure, where the "7T1C" circuit structure means there are 7 transistors and 1 capacitor, and the same applies to the others.

[0073] The signal output by the shift register in the scan driving circuit can be used as a signal to control whether the sub-pixel data signal data can be written. Figure 8 The transistor T2 is used to control the writing of the data signal data, and the scanning signal SP is a signal output by the shift register. Exemplarily, the scanning signal S2 and the scanning signal SP may be the same.

[0074] In some embodiments, Fig. 9 As shown, the display panel 100 includes a first display area A1 and a second display area A2 adjacent to each other. Exemplarily, each display area includes a plurality of sub-pixels 20 arranged in an array in the intersecting first direction X and second direction Y. When an abnormal data signal is written to the sub-pixel 20, the sub-pixel is refreshed once. The first display area A1 and the second display area A2 are adjacent to each other in the second direction Y.

[0075] The shift register VSR includes a first shift register and a second shift register. The first shift register is electrically connected to the sub-pixels 20 in the first display area A1, and the second shift register is electrically connected to the sub-pixels 20 in the second display area A2.

[0076] For example, the 1st-stage shift register VSR(1) to the mth-stage shift register VSR(m) are used to electrically connect the sub-pixels in the first display area A1, and the m+1th-stage shift register VSR(m+1) to the nth-stage shift register VSR(n) are used to electrically connect the sub-pixels 20 in the second display area A2, wherein 1<m<m+1<n, and m and n are both integers.

[0077] The 1st-stage shift register VSR(1) to the m-th-stage shift register VSR(m) are first shift registers, and the m+1-th-stage shift register VSR(m+1) to the n-th-stage shift register VSR(n) are second shift registers.

[0078] like Fig.10 As shown, the working process of the display panel includes a first refresh period F1 and a second refresh period F2.

[0079] In the first refresh cycle F1, the first trigger signal connected to the first input terminal IN1 of the first shift register and the second shift register both include an enable level; in the second refresh cycle F2, the first trigger signal connected to the first input terminal IN1 of the first shift register and the second shift register remains at a non-enable level, and the second trigger signal connected to the second input terminal IN2 of the first shift register remains at a non-enable level, and the second trigger signal connected to the second input terminal IN2 of the second shift register includes an enable level.

[0080] For example, the first refresh period F1 includes a first period t11 and a second period t12, and the second refresh period F2 includes a third period t21 and a fourth period t22. The multi-stage shift register of the scan driving circuit outputs signals stage by stage.

[0081] Please refer to Fig. 9 and Fig.10 The first time period t11 is the scanning time period corresponding to the first display area A1 in the first refresh cycle F1, the second time period t12 is the scanning time period corresponding to the second display area A2 in the first refresh cycle F1, the third time period t21 is the scanning time period corresponding to the first display area A1 in the second refresh cycle F2, and the fourth time period t22 is the scanning time period corresponding to the second display area A2 in the second refresh cycle F2.

[0082] Fig.10 SP1 represents the scanning signal output by the first shift register, and is also the scanning signal connected to a row of sub-pixels in the first display area A1; SP2 represents the scanning signal output by the second shift register, and is also the scanning signal connected to a row of sub-pixels in the second display area A2. The signal on the first input terminal IN1 and the signal in the first time period t11 and the third time period t21 represent the first trigger signal connected to the first input terminal of the first shift register; the signal on the first input terminal IN1 in the second time period t12 and the fourth time period t22 represent the first trigger signal connected to the first input terminal of the second shift register. The signal on the second input terminal IN2 is the same. In addition, the trigger signal STV represents the signal output by the selection module 11. Fig.10 In the figure, the enable levels of the signal on the first input terminal IN1, the signal on the second input terminal IN2, the trigger signal STV, the scanning signal SP1, and the scanning signal SP2 are low levels for illustration.

[0083] In the first time period t11 of the first refresh cycle F1, the first trigger signal connected to the first input terminal IN1 of the first shift register includes an enable level (low level), so that the scanning signal SP1 output by the first shift register in the first refresh cycle F1 includes an enable level (low level), so that the data signal can be written into the sub-pixels in the first display area.

[0084] In the second time period t12 of the first refresh cycle F1, the first trigger signal connected to the first input terminal IN1 of the second shift register includes an enable level (low level), so that the scanning signal SP2 output by the second shift register in the first refresh cycle F1 includes an enable level (low level), so that the data signal can be written into the sub-pixels in the second display area.

[0085] In the third time period t21 of the second refresh cycle F2, the first trigger signal connected to the first input terminal IN1 of the first shift register maintains a non-enable level (high level), and the second trigger signal connected to the second input terminal IN2 of the first shift register maintains a non-enable level (high level). In this way, the scanning signal SP1 output by the first shift register in the second refresh cycle F2 maintains a non-enable level (high level), so that the data signal cannot be written into the sub-pixels in the first display area.

[0086] In the third time period t21 of the second refresh cycle F2, the first trigger signal connected to the first input terminal IN1 of the second shift register maintains a non-enable level (high level), and the second trigger signal connected to the second input terminal IN2 of the second shift register includes an enable level (low level). In this way, the scanning signal SP2 output by the second shift register in the second refresh cycle F2 still includes an enable level (low level), so that the data signal can be written into the sub-pixels in the second display area.

[0087] In this way, the first display area is refreshed at a low refresh rate, and the second display area is refreshed at a high refresh rate.

[0088] In some embodiments, please refer to Figure 7 , Fig. 9 and Fig.10 The shift register is also used to access the clock signal. For example, the shift register is also used to access the first clock signal CK1, the second clock signal CK2 and the third clock signal CK3.

[0089] In the first refresh cycle F1, the clock signals connected to the first shift register and the second shift register are both high-low level transition signals; in the second refresh cycle F2, the clock signal connected to the first shift register remains unchanged, and the clock signal connected to the second shift register is a high-low level transition signal.

[0090] The clock signal signals in the first time period t11 and the third time period t21 represent the first clock signal CK1, the second clock signal CK2 and the third clock signal CK3 connected to the first shift register; the signals in the second time period t12 and the fourth time period t22 represent the first clock signal CK1, the second clock signal CK2 and the third clock signal CK3 connected to the second shift register.

[0091] In the third period t21, the scan signal SP1 that the first shift register does not need to output does not need to include an enable level (low level). At this time, the signal output by the shift module of the first shift register does not need to include an enable level (low level). Therefore, in the third period t21, the first clock signal CK1, the second clock signal CK2, and the third clock signal CK3 do not need to be high-low level jumps, but keep a level unchanged. For example, in the third period t21, the first clock signal CK1 and the second clock signal CK2 keep a low level, and the third clock signal CK3 keeps a high level. In this way, the power consumption of the driver chip can be reduced.

[0092] In the fourth time period t22, the first clock signal CK1, the second clock signal CK2 and the third clock signal CK3 are signals that jump from high to low levels, and the second trigger signal connected to the second input terminal IN2 of the second shift register includes an enable level (low level), ensuring that the scan signal SP2 output by the second shift register in this stage includes an enable level (low level).

[0093] In some embodiments, please refer to Figure 7 , Fig. 9 and Fig.10 The level transmission module includes a control submodule 121 and a level transmission submodule 122 , and the shift register VSR also includes an output module 13 .

[0094] The input end of the control submodule 121 is electrically connected to the output end of the gating module 11, and the control submodule 121 is electrically connected to the first node N1 and the second node N2. The control submodule 121 is used to control the potential of the first node N1 and the second node N2. The level transmission submodule 122 is electrically connected to the first node N1 and the second node N2. The output end out1 of the level transmission submodule 122 is the output end of the shift module. The level transmission submodule 122 is used to output a signal according to the potential of the first node N1 and the second node N2. The output end out1 of the level transmission submodule 122 in the i-th stage shift register is electrically connected to the first input end IN1 of the gating module in the i+1-th stage shift register.

[0095] The output module 13 is electrically connected to the first node N1 and the second node N2. The output module 13 is used to output a signal according to the potentials of the first node N1 and the second node N2. The output terminal out2 of the output module 13 is used to electrically connect to the sub-pixel 20. In this example, the signal output by the output terminal out1 of the level transmission submodule 122 is used as the level transmission signal, and the signal output by the output terminal out2 of the output module 13 is used as the scanning signal of the sub-pixel 20.

[0096] In the second refresh cycle F2, the clock signal input to the output module of the first shift register remains at a non-enable level.

[0097] Exemplarily, in the third time period t21 of the second refresh cycle F2, the third clock signal CK3 connected to the output module of the first shift register remains at a non-enable level (high level). When the transistor M11 in the output module 13 is turned on, the output terminal out2 of the output module 13 will output the signal of the third clock signal CK3, and the third clock signal CK3 remains at a high level. In this way, even if the transistor M11, the output terminal out2 of the output module 13 also outputs a high-level signal, so that the scanning signal SP1 remains at a high level in the third time period t21.

[0098] In some embodiments, please refer to Figure 7 , Fig. 9 and Fig.10 The gating module 11 further includes a first transistor M1, a first electrode of the first transistor M1 is electrically connected to the second trigger signal line 32, a second electrode of the first transistor M1 is electrically connected to the second input terminal IN2 of the AND gate AND, and a gate of the first transistor M1 is used to access the frequency cutting signal Ctrl.

[0099] In the first refresh cycle F1, the frequency-cutting signal Ctrl connected to the first shift register and the second shift register both maintain a non-enable level. In the second refresh cycle F2, the frequency-cutting signal Ctrl connected to the first shift register maintains a non-enable level, the frequency-cutting signal Ctrl connected to the second shift register includes an enable level, and the enable level of the second trigger signal connected to the second input terminal IN2 of the second shift register and the enable level of the frequency-cutting signal Ctrl at least partially overlap.

[0100] In the first time period t11 of the first refresh cycle F1, the frequency-cutting signal Ctrl connected to the first shift register maintains a high level, the first transistor M1 of the first shift register is disconnected, and the second trigger signal cannot be transmitted to the AND gate and of the first shift register. During this period, the first trigger signal connected to the first input terminal IN1 of the first shift register includes an enable level (low level), so that the scanning signal SP1 output by the first shift register in the first refresh cycle F1 includes an enable level (low level), so that the data signal can be written into the sub-pixels in the first display area.

[0101] In the second time period t12 of the first refresh cycle F1, the frequency-cutting signal Ctrl connected to the second shift register maintains a high level, the first transistor M1 of the second shift register is disconnected, and the second trigger signal cannot be transmitted to the AND gate and of the second shift register. During this period, the first trigger signal connected to the first input terminal IN1 of the second shift register includes an enable level (low level), so that the scanning signal SP2 output by the second shift register in the first refresh cycle F1 includes an enable level (low level), so that the data signal can be written into the sub-pixels in the second display area.

[0102] In the third period t21 of the second refresh cycle F2, the frequency-cutting signal Ctrl connected to the first shift register maintains a high level, the first transistor M1 of the first shift register is disconnected, and the second trigger signal cannot be transmitted to the AND gate and of the first shift register. In addition, during this period, the first trigger signal connected to the first input terminal IN1 of the first shift register maintains a non-enable level (high level), so that the scanning signal SP1 output by the first shift register in the second refresh cycle F2 maintains a non-enable level (high level), so that the data signal cannot be written into the sub-pixels in the first display area.

[0103] In the third time period t21 of the second refresh cycle F2, the frequency cutting signal Ctrl connected to the second shift register maintains a low level, and the second trigger signal includes an enable level (low level), the first transistor M1 is turned on, and the low level of the second trigger signal on the second trigger signal line is transmitted to the second input terminal IN2 of the second shift register. In this way, the scanning signal SP2 output by the second shift register in the second refresh cycle F2 still includes the enable level (low level), so that the data signal can be written into the sub-pixels in the second display area.

[0104] Exemplarily, the refresh frequency corresponding to the first refresh period F1 and the second refresh period F2 is 120 Hz.

[0105] It should be noted that Fig. 9 Taking the example that the first display area A1 is located above the second display area A2 and the refresh rate of the first display area A1 is lower than the refresh rate of the second display area A2, this is not used to limit the present application. In other embodiments, the display area with a high refresh rate may be located on the side of the original driver chip of the display area with a low refresh rate.

[0106] For example, please refer to Figure 7 , Fig.11 and Fig.12 The display panel may further include a third display area A3, and in the second direction Y, the second display area A2 is located between the first display area A1 and the second display area A3, wherein the refresh frequency of the second display area A2 is the highest, or the refresh frequency of the second display area A2 is the lowest.

[0107] The following description is made by taking an example that the refresh frequency of the second display area A2 is the highest, and the refresh frequencies of the first display area A1 and the third display area A3 are the same.

[0108] For example, the 1st-level shift register VSR(1) to the mth-level shift register VSR(m) are used to electrically connect the sub-pixels in the first display area A1, the m+1th-level shift register VSR(m+1) to the nth-level shift register VSR(n) are used to electrically connect the sub-pixels 20 in the second display area A2, and the n+1th-level shift register VSR(n+1) to the kth-level shift register VSR(k) are used to electrically connect the sub-pixels 20 in the third display area A3, wherein 1<m<m+1<n<n+1<k, and m, n, and k are all integers.

[0109] The 1st-stage shift register VSR(1) to the mth-stage shift register VSR(m) are the first shift registers, the m+1th-stage shift register VSR(m+1) to the nth-stage shift register VSR(n) are the second shift registers, and the n+1th-stage shift register VSR(n+1) to the kth-stage shift register VSR(k) are the third shift registers.

[0110] Fig.12 and Fig.11 The similarities are not introduced here, but the differences include:

[0111] Fig.12 The signals in the time periods t13 and t23 represent the signals connected to the third shift register.

[0112] In the first refresh cycle F1, the first trigger signal connected to the first input terminal IN1 of the third shift register includes an enable level; in the second refresh cycle F2, the first trigger signal connected to the first input terminal IN1 of the third shift register maintains a non-enable level, and the second trigger signal connected to the second input terminal IN2 of the third shift register maintains a non-enable level.

[0113] In the fifth time period t13 of the first refresh cycle F1, the first trigger signal connected to the first input terminal IN1 of the third shift register includes an enable level (low level), so that the scanning signal SP3 output by the third shift register in the first refresh cycle F1 includes an enable level (low level), so that the data signal can be written into the sub-pixels in the third display area.

[0114] In the sixth time period t23 of the second refresh cycle F2, the first trigger signal connected to the first input terminal IN1 of the third shift register maintains a non-enable level (high level), and the second trigger signal connected to the second input terminal IN2 of the third shift register maintains a non-enable level (high level). In this way, the scanning signal SP3 output by the third shift register in the second refresh cycle F2 maintains a non-enable level (high level), so that the data signal cannot be written into the sub-pixels in the third display area.

[0115] Exemplarily, in the first refresh cycle F1, the clock signals connected to the third shift register are all high-low level transition signals; in the second refresh cycle F2, the clock signals connected to the third shift register remain unchanged.

[0116] Exemplarily, the level transmission module includes a control submodule 121 and a level transmission submodule 122, and the shift register VSR also includes an output module 13. In the second refresh cycle F2, the clock signal connected to the output module of the third shift register remains unchanged at a non-enabled level. For example, the clock signal CK31 connected to the output module of the odd-numbered shift register and the clock signal CK32 connected to the output module of the even-numbered shift register, in the time period t21 and the time period t23 of the second refresh cycle F2, the clock signal CK31 and the clock signal CK32 both maintain a high level.

[0117] Exemplarily, when the gating module includes a first transistor, in the first refresh cycle F1, the frequency cutting signal Ctrl connected to the third shift register maintains a non-enabling level; in the second refresh cycle F2, the frequency cutting signal Ctrl connected to the third shift register maintains a non-enabling level.

[0118] Exemplarily, the working modes of the display panel include Normal mode and MFD mode. In Normal mode, multiple rows of sub-pixels in the entire display area of ​​the display panel are refreshed at the same refresh frequency. In MFD mode, the display area of ​​the display panel is divided into multiple display areas, and the refresh frequencies of at least two display areas are different, that is, the area is refreshed at a different frequency.

[0119] The embodiment of the present application can realize the switching of the display panel between the Normal mode and the MFD mode, and in the MFD mode, any partition can be performed.

[0120] For example, the display panel includes 100 rows of sub-pixels.

[0121] In the first application scenario, the sub-pixels in rows 1 to 50 can be divided into one display area, and the sub-pixels in rows 51 to 100 can be divided into another display area, and the scanning drive circuit can refresh the sub-pixels in rows 1 to 50 at a refresh frequency f1, and refresh the sub-pixels in rows 51 to 100 at a refresh frequency f2, f1≠f2, for example, f1<f2, or f1>f2.

[0122] In the second application scenario, the sub-pixels in rows 1 to 30 can be divided into one display area, the sub-pixels in rows 31 to 60 can be divided into another display area, and the sub-pixels in rows 61 to 100 can be divided into yet another display area, and the scanning drive circuit can refresh the sub-pixels in rows 1 to 30 at a refresh frequency f3, refresh the sub-pixels in rows 31 to 60 at a refresh frequency f4, and refresh the sub-pixels in rows 61 to 100 at a refresh frequency f5, f4≠f3, f4≠f5, for example, f4>f3=f5, or, f4<f3=f5.

[0123] Of course, there are many other application scenarios, which are not listed here one by one.

[0124] The present application also provides a display device, including the display panel provided by the present application. Fig.13 , Fig.13 It is a structural schematic diagram of a display device provided in an embodiment of the present application. Fig.13 The provided display device 1000 includes the display panel 100 provided by any of the above embodiments of the present application. Fig.13 The embodiment only takes a mobile phone as an example to illustrate the display device 1000. It can be understood that the display device provided in the embodiment of the present application can be a wearable product, a computer, a television, a car display device, or other display devices with display functions, and the present application does not make specific restrictions on this. The display device provided in the embodiment of the present application has the beneficial effects of the display panel provided in the embodiment of the present application. For details, please refer to the specific description of the display panel in the above embodiments, and this embodiment will not be repeated here.

[0125] According to the embodiments described above in the present application, these embodiments do not describe all the details in detail, nor do they limit the present application to the specific embodiments described. Obviously, many modifications and changes can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present application, so that those skilled in the art can make good use of the present application and the modifications based on the present application. The present application is limited only by the claims and their full scope and equivalents.

Claims

1. A scanning driving circuit, characterized in that: include: A plurality of cascaded shift registers, wherein the shift registers include a gating module and a shifting module, wherein a first input end of the gating module is used to access a first trigger signal, a first input end of the gating module in the first-stage shift register is electrically connected to a first trigger signal line, a first input end of the gating module in the i+1-stage shift register is electrically connected to an output end of the shift module in the i-stage shift register, i being an integer greater than 0, a second input end of the gating module is electrically connected to a second trigger signal line, and the second trigger signal line is used to transmit a second trigger signal; The gating module is used to output an enable level (the enable level in this application is a low level) of at least one of the first trigger signal and the second trigger signal to the shift module; The shift module is used for outputting a signal including an enable level in response to the enable signal output by the gating module.

2. The scanning driving circuit according to claim 1, characterized in that: The gating module includes an AND gate, a first input end of the AND gate is the first input end of the gating module, a second input end of the AND gate is the second input end of the gating module, an output end of the AND gate is the output end of the gating module, and an enable level of the first trigger signal and the second trigger signal is a low level.

3. The scanning driving circuit according to claim 1 or 2, characterized in that: The gating module further includes a first transistor, a first electrode of the first transistor is electrically connected to the second trigger signal line, a second electrode of the first transistor is electrically connected to the second input end of the gating module, and a gate of the first transistor is used to access the frequency cutting signal.

4. The scanning driving circuit according to claim 3, characterized in that: The gating module further comprises a pull-up submodule electrically connected to the second input terminal of the gating module, and configured to keep the level of the second input terminal of the gating module at a non-enabling level when the frequency cutting signal is at a non-enabling level.

5. The scanning driving circuit according to claim 1 or 2, characterized in that: The shift module includes a control submodule and a level transmission submodule. The input end of the control submodule is electrically connected to the output end of the gating module, the control submodule is electrically connected to the first node and the second node, and the control submodule controls the potential of the first node and the second node; The level transmission submodule is electrically connected to the first node and the second node, the output end of the level transmission submodule is the output end of the shift module, and the level transmission submodule is used to output a signal according to the potentials of the first node and the second node; The output end of the stage transmission submodule in the i-th stage shift register is electrically connected to the first input end of the gating module in the (i+1)-th stage shift register; The output end of the stage transfer submodule is used to electrically connect the sub-pixel, or the shift register also includes an output module, the output module is electrically connected to the first node and the second node, the output module is used to output a signal according to the potential of the first node and the second node, and the output end of the output module is used to electrically connect the sub-pixel.

6. A display panel, characterized in that: The invention comprises a scanning driving circuit as claimed in any one of claims 1 to 5.

7. The display panel according to claim 6, characterized in that: The display panel includes a first display area and a second display area adjacent to each other; The shift register includes a first shift register and a second shift register, the first shift register is electrically connected to the sub-pixels in the first display area, and the second shift register is electrically connected to the sub-pixels in the second display area; The working process of the display panel includes a first refresh cycle (refresh frame) and a second refresh cycle; In the first refresh cycle, the first trigger signals connected to the first input terminals of the first shift register and the second shift register both include an enable level; In the second refresh cycle, the first trigger signal connected to the first input terminal of the first shift register and the second shift register maintains a non-enable level, and the second trigger signal connected to the second input terminal of the first shift register maintains a non-enable level, and the second trigger signal connected to the second input terminal of the second shift register includes an enable level.

8. The display panel according to claim 7, characterized in that: The shift register is also used to access the clock signal; In the first refresh cycle, the clock signals connected to the first shift register and the second shift register are both high-low level transition signals; In the third time period of the second refresh cycle, the clock signal connected to the first shift register remains unchanged. In the fourth time period of the second refresh cycle, the clock signal connected to the second shift register is a signal with high and low level jumps. The third time period is a scanning time period corresponding to the first display area, and the fourth time period is a scanning time period corresponding to the second display area.

9. The display panel according to claim 8, characterized in that: The shift module of the shift register includes a control submodule and a stage transmission submodule, and the shift register also includes an output module; The input end of the control submodule is electrically connected to the output end of the gating module, the control submodule is electrically connected to the first node and the second node, and the control submodule controls the potential of the first node and the second node; The level transmission submodule is electrically connected to the first node and the second node, the output end of the level transmission submodule is the output end of the shift module, and the level transmission submodule is used to output a signal according to the potentials of the first node and the second node; The output module is electrically connected to the first node and the second node, the output end of the output module is used to electrically connect to the sub-pixel, and the output module is used to output a signal according to the potentials of the first node and the second node; During a third period of the second refresh cycle, the clock signal input to the output module of the first shift register remains at a non-enable level.

10. The display panel according to claim 7, characterized in that: The gating module further comprises a first transistor, a first electrode of the first transistor is electrically connected to the second trigger signal line, a second electrode of the first transistor is electrically connected to the second input end of the gating module, and a gate of the first transistor is used to access the frequency cutting signal; In the first refresh cycle, the frequency cutting signals connected to the first shift register and the second shift register both maintain a non-enable level; In the second refresh cycle, the frequency cutting signal connected to the first shift register maintains a non-enable level, the frequency cutting signal connected to the second shift register includes an enable level, and the enable level of the second trigger signal connected to the second input terminal of the second shift register and the enable level of the frequency cutting signal at least partially overlap.

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