RISC-V-based general parallel computing architecture co-processing system

Abstract

The invention discloses a general parallel computing architecture co-processing system based on RISC-V, belongs to the technical field of digital integrated circuits, and is used for solving the problems of low computing speed and complex data propagation path in the prior art. A universal parallel operation module, a scheduling module and a shared memory; the scheduling module receives an operation request sent by the RISC-V main processor, and schedules the shared memory and controls the universal parallel operation module according to decoding information; and the universal parallel operation module performs operation on the data in the shared memory to obtain an operation result, and writes the operation result back to the shared memory. According to the method, multiple complex algorithms such as multiplication, floating point, vector and matrix are supported at the same time based on the general parallel computing architecture, support of other computing coprocessors is not needed, hardware computing resources are reused to the maximum extent in the general parallel computing architecture, hardware redundancy is reduced, non-parallel computing is optimized by utilizing the advantages of the parallel architecture, the computing speed is increased, and the computing cost is reduced. A data propagation path is optimized, and redundant data reading and writing in the transmission process are reduced.

Description

Technical Field

[0001] The present invention relates to the field of digital integrated circuit technology, and in particular to a general parallel computing architecture coprocessor system based on RISC-V. Background Art

[0002] A coprocessor is an auxiliary processor used to assist the central processing unit in performing specific tasks or processing specific types of data. It can improve the performance and efficiency of the computer system and reduce the burden on the CPU. From early mathematical coprocessors to modern graphics processors, coprocessors have a wide range of applications.

[0003] The optimization idea of ​​the coprocessor is based on DSA (Domain Specific Architecture). The so-called DSA refers to optimization for specific application scenarios, rather than being designed to handle a variety of different tasks like general-purpose processors. By specifically optimizing the processor's architecture and instruction set, DSA can more effectively perform tasks in a specific domain, thereby improving performance and reducing power consumption. Due to the current performance bottleneck of general computing, coprocessors that can provide higher performance and lower power consumption have become a new solution, and key breakthroughs have been made in areas such as graphics processing and artificial intelligence.

[0004] RISC-V is an open source, reduced instruction set architecture known for its flexibility, scalability and openness. As a general instruction set architecture, RISC-V can be widely used in various computing devices and fields, including embedded systems, personal computers, servers and supercomputers, providing users with free and flexible choices.

[0005] In recent years, with the rapid development of IoT technology and artificial intelligence technologies such as neural networks, the demand for complex algorithms that support floating-point operations, multiplication and division, vector calculations, and matrix operations has also increased. For example, in the IoT, real-time processing and analysis of sensor data requires efficient floating-point computing capabilities, while in the field of artificial intelligence, the training and reasoning of neural network models require a large number of vector and matrix operations. Therefore, RISC-V coprocessors face more complex and diverse application scenarios and need to have more powerful and flexible computing capabilities.

[0006] Therefore, there is an urgent need to provide a more reliable RISC-V-based general parallel computing architecture co-processing system. Summary of the invention

[0007] The purpose of the present invention is to provide a general parallel computing architecture coprocessing system based on RISC-V, which is used to solve the problems of slow computing speed and complex data propagation path in the prior art.

[0008] In order to achieve the above object, the present invention provides the following technical solutions:

[0009] In a first aspect, the present invention provides a general parallel computing architecture co-processing system based on RISC-V, the system comprising:

[0010] General parallel computing architecture coprocessor and RISC-V main processor;

[0011] The general parallel computing architecture coprocessor includes: a general parallel computing module, a scheduling module and a shared memory;

[0012] The scheduling module receives the operation request issued by the RISC-V main processor, and schedules the shared memory and controls the general parallel operation module according to the decoding information;

[0013] The general parallel operation module operates on the data in the shared memory to obtain an operation result, and writes the operation result back to the shared memory.

[0014] Compared with the prior art, the RISC-V-based general parallel computing architecture coprocessor system provided by the present invention includes: a general parallel computing module, a scheduling module and a shared memory; the scheduling module receives the computing request issued by the RISC-V main processor, and schedules the shared memory and controls the general parallel computing module according to the decoding information; the general parallel computing module performs computing on the data in the shared memory, obtains the computing result, and writes the computing result back to the shared memory. The present invention supports a variety of complex algorithms such as multiplication, floating point, vector, and matrix based on the general parallel computing architecture, and does not require the support of other computing coprocessors, so as to achieve the purpose of replacing multiple coprocessors with one coprocessor, and maximizes the reuse of hardware computing resources within the general parallel computing architecture, reduces hardware redundancy, optimizes non-parallel computing by utilizing the advantages of the parallel architecture, improves computing speed, optimizes the data propagation path, and reduces redundant data reading and writing during transmission. Thus, a high-performance, low-power, widely used, and flexible RISC-V coprocessor system is realized.

[0015] Optionally, the general parallel operation module includes a result processing unit and a plurality of general parallel operation units;

[0016] The general parallel operation module receives the memory index provided by the scheduling module;

[0017] Obtaining a source operand from the shared memory according to the memory index, performing a corresponding operation according to the operation type provided by the scheduling module, and writing the operation result back to the shared memory;

[0018] The general parallel operation module is used to provide support for various algorithms such as multiplication, floating point, vector and matrix, which can maximize the reuse of hardware resources and reduce consumption.

[0019] Optionally, the scheduling module includes an instruction scheduling unit responsible for instruction flow control, a data scheduling unit responsible for data flow control, and a calculation scheduling unit responsible for calculation task control;

[0020] The scheduling module is used to decode the operation request, obtain decoding information, and generate scheduling logic according to the decoding information, configure the shared memory and control the general parallel operation module according to the scheduling logic, and return the operation result to the RISC-V main processor after the operation task is completed and deliver the current operation instruction.

[0021] Optionally, the shared memory is implemented by a synchronization register; a data interaction interface is maintained between the shared memory, the scheduling module and each of the general parallel computing units, and the shared memory is used for data sharing within the general parallel computing module and for data interaction caching with external master and slave processors.

[0022] Optionally, the general parallel computing unit includes:

[0023] An operation path selection subunit, an integer operation subunit, a multiplication and division operation subunit, a floating point operation subunit and a matrix operation subunit;

[0024] The result processing unit is controlled by the operation scheduling unit, and processes the intermediate results output by each of the general parallel operation units when processing integers, multiplications, divisions and floating-point operations exceeding the processor bit width, and outputs the final result.

[0025] Optionally, the operation path selection subunit is used to enable a corresponding operation unit according to the operation type of the operation scheduling unit;

[0026] The integer operation subunit is used to perform integer operations of the bit width of the RISC-V main processor;

[0027] Vector integer operations and integer operations exceeding the bit width of the processor are implemented in parallel by the integer operation subunits in a plurality of general parallel operation units;

[0028] The multiplication and division operator unit is used to perform multiplication and division operations of the bit width of the RISC-V main processor; vector multiplication and division operations and multiplication and division operations exceeding the processor bit width are implemented in parallel by multiplication and division operator units in multiple general parallel operation units;

[0029] The floating-point operation subunit is used to perform floating-point operations of the bit width of the RISC-V main processor; vector floating-point operations and floating-point operations exceeding the processor bit width are implemented in parallel by floating-point operation subunits in multiple general parallel operation units;

[0030] The matrix operation subunit is used for reusing the floating-point operation subunit, and the matrix algorithm is implemented by converting the matrix operation into a multi-cycle vector operation through a scheduling module.

[0031] Optionally, the instruction scheduling unit includes:

[0032] an instruction cache subunit, an instruction decode subunit, and an instruction delivery subunit;

[0033] The instruction scheduling unit is responsible for controlling the instruction flow in the coprocessor, receiving instruction requests from the RISC-V main processor, caching instructions and decoding instructions, providing decoding information to other components of the scheduling module, and delivering instructions to the RISC-V main processor after completing the calculation task and writing back the results;

[0034] The instruction cache subunit and the RISC-V main processor implement instruction transmission through valid-ready handshake, and the instruction cache subunit includes a synchronization register for caching the current instruction;

[0035] The instruction decoding subunit is used to decode the instructions in the instruction cache subunit and distribute the extraction results to the data scheduling unit and the operation scheduling unit;

[0036] The instruction delivery subunit and the RISC-V main processor implement instruction delivery and result write-back through valid-ready handshake; the instruction delivery subunit includes a synchronization register.

[0037] Optionally, the data scheduling unit includes:

[0038] an address generation subunit, a bus interface subunit, a data processing subunit, and a memory configuration subunit;

[0039] The data scheduling unit is responsible for controlling the data flow in the coprocessor, receiving information from the operation scheduling unit, calculating the coprocessor read and write target address, managing data interaction between the master and slave processors through the bus interface, implementing data verification and processing according to the data type, and configuring data to the shared memory according to the register index.

[0040] Optionally, the address generation subunit receives information from the operation scheduling unit and calculates the actual target address of the read and write instructions for use by the bus interface subunit;

[0041] The bus interface subunit and the RISC-V main processor implement memory access from the processor to the RISC-V main processor memory through a valid-ready handshake protocol, receive address information and access type of the address generation subunit, and manage data interaction from the processor to the main memory;

[0042] The data processing subunit receives information from the operation scheduling unit, processes the obtained data according to the calculation type and data type, and obtains target data;

[0043] The memory configuration subunit receives information from the operation scheduling unit, data from the data processing subunit, and data in the general registers and system control registers of the RISC-V main processor, configures the data of the data processing subunit and the data in the general registers of the RISC-V main processor according to the configuration of the system control register and the control of the scheduling operation module, and writes them to the specified location of the shared memory for use by the general parallel operation module.

[0044] Optionally, the operation scheduling unit includes:

[0045] Operation scheduling subunit and operation cache subunit.

[0046] The operation scheduling subunit is used to receive information from the instruction decoding module and perform hardware operation scheduling according to the operation type;

[0047] Directly schedule vector operations, multiplication and division operations that do not exceed the processor bit width, and floating-point operations, and assign them to the operation unit for calculation;

[0048] Indirect scheduling is performed for matrix operations and multiplication and division operations that exceed the processor bit width, as well as floating-point operations, which are converted into multiple vector operations and multiplication and division operations that do not exceed the processor bit width, and floating-point operations, and then assigned to the operation unit for calculation;

[0049] The operation cache subunit is implemented by a synchronization register, which is responsible for storing operation scheduling information that requires multiple cycles to complete and storing the current completion progress. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0051] Figure 1 A structural block diagram of a general parallel computing architecture co-processing system based on RISC-V provided by the present invention;

[0052] Figure 2 A schematic diagram of the structure of a general parallel computing module provided by the present invention;

[0053] Figure 3 A schematic diagram of the scheduling module structure provided by the present invention;

[0054] Figure 4 A workflow diagram of a general parallel computing architecture co-processing system based on RISC-V provided by the present invention;

[0055] Figure 5 A schematic diagram of shared memory path optimization provided by the present invention.

[0056] Reference numerals:

[0057] 1-general parallel computing architecture coprocessor, 2-RISC-V main processor, 11-general parallel computing module, 12-scheduling module, 13-shared memory, 111-result processing unit, 112-general parallel computing unit, 121-instruction scheduling unit, 122-computation scheduling unit, 123-data scheduling unit. DETAILED DESCRIPTION

[0058] In order to clearly describe the technical solutions of the embodiments of the present invention, in the embodiments of the present invention, words such as "first" and "second" are used to distinguish the same items or similar items with basically the same functions and effects. For example, the first threshold and the second threshold are only used to distinguish different thresholds, and their order is not limited. Those skilled in the art can understand that words such as "first" and "second" do not limit the quantity and execution order, and words such as "first" and "second" do not necessarily limit them to be different.

[0059] It should be noted that, in the present invention, words such as "exemplary" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in the present invention should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a specific way.

[0060] In the present invention, "at least one" means one or more, and "plurality" means two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the associated objects before and after are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b or c can mean: a, b, c, the combination of a and b, the combination of a and c, the combination of b and c, or the combination of a, b and c, where a, b, c can be single or multiple.

[0061] In the prior art, the traditional RISC-V coprocessor serves a single instruction extension, that is, a coprocessor is oriented to a single extended instruction set and can meet the needs of a certain operation.

[0062] However, with the diversification and complexity of application scenarios, traditional RISC-V processors can no longer meet the growing computing needs. Traditional RISC-V coprocessors serve single instruction extensions. For example, RISC-V's floating-point instruction extension requires floating-point coprocessor support, and vector instruction extension requires vector coprocessor support. When both floating-point extension and vector extension need to be supported, different extended instructions need to be sent to different coprocessors for separate operations, and the hardware operation unit is only activated part of the time, which causes hardware resource redundancy and data path complexity.

[0063] In order to solve the problems in the prior art, the present invention provides a RISC-V-based general parallel computing architecture coprocessor system, which supports multiplication, floating point, vector, matrix and other complex algorithms based on the general parallel computing architecture, without the need for other computing coprocessors, so as to achieve the purpose of replacing multiple coprocessors with one coprocessor. Next, the scheme provided by the embodiment of this specification is described in conjunction with the accompanying drawings:

[0064] like Figure 1 As shown, a general parallel computing architecture coprocessing system based on RISC-V provided by the present invention may include:

[0065] General parallel computing architecture coprocessor 1 and RISC-V main processor 2;

[0066] The general parallel computing architecture coprocessor 1 includes: a general parallel computing module 11, a scheduling module 12 and a shared memory 13, and is connected to the RISC-V main processor 2 through the scheduling module 12;

[0067] The scheduling module 12 receives the operation request issued by the RISC-V main processor 2, and schedules the shared memory 13 and controls the general parallel operation module 11 according to the decoding information;

[0068] The general parallel operation module 11 operates on the data in the shared memory 13 to obtain an operation result, and writes the operation result back to the shared memory 13 .

[0069] Figure 1 The structure in the embodiment includes: a general parallel operation module 11, a scheduling module 12 and a shared memory 13; the scheduling module 12 receives the operation request issued by the RISC-V main processor 2, and schedules the shared memory 13 and controls the general parallel operation module 11 according to the decoding information; the general parallel operation module 11 operates on the data in the shared memory 13, obtains the operation result, and writes the operation result back to the shared memory 13. The present invention supports a variety of complex algorithms such as multiplication, floating point, vector, and matrix based on the general parallel operation architecture, and does not require the support of other computing coprocessors, so as to achieve the purpose of replacing multiple coprocessors with one coprocessor, and maximizes the reuse of hardware computing resources within the general parallel operation architecture, reduces hardware redundancy, optimizes non-parallel operations by utilizing the advantages of the parallel architecture, improves the operation speed, optimizes the data propagation path, and reduces redundant data reading and writing during the transmission process. Thus, a high-performance, low-power, widely used, and flexible RISC-V coprocessor system is realized.

[0070] Of course, in practical applications, the same support for multiple complex algorithms can also be achieved by adding multiple co-processing modules.

[0071] based on Figure 1 The system structure of this specification also provides some specific implementation methods of the system, which are described below.

[0072] For the general parallel operation module 11, Figure 2 As shown, it may include a plurality of general parallel operation units 112 and a result processing unit 111. The general parallel operation module 11 is responsible for receiving the control of the scheduling module 12, performing operations on the data in the shared memory 13, and writing the results back to the shared memory 13 for the scheduling module 12 to deliver and use.

[0073] The general parallel operation module 11 is characterized in that it can provide support for various algorithms such as multiplication, floating point, vector and matrix, and maximize the reuse of hardware resources to reduce consumption.

[0074] For the scheduling module 12, Figure 3As shown, it may include an instruction scheduling unit 121 responsible for instruction flow control, a data scheduling unit 123 responsible for data flow control, and an operation scheduling unit 122 responsible for operation control. The scheduling module 12 is responsible for receiving operation requests from the RISC-V main processor 2, scheduling the shared memory 13 and controlling the general parallel operation module 11 according to the decoding information, and writing back the results and delivering instructions after the operation is completed.

[0075] Among them, the shared memory 13 is implemented by a synchronization register, and maintains a data interaction interface with the scheduling module 12 and each general parallel operation unit 112. The shared memory 13 realizes data sharing within the internal general parallel operation module 11 and data interaction cache for the external master and slave processors. The shared memory 13 reserves a part of the space dedicated to the data storage of vector extensions, so that the coprocessor is compatible with the RISC-V standard vector extension without making additional adjustments, that is, no additional coprocessor storage is required. The data transmission path is optimized to reduce the performance and power consumption losses caused by meaningless reading and writing of data during the circulation process.

[0076] As an optional implementation, the general parallel operation unit 112 may include an operation path selection subunit, an integer operation subunit, a multiplication and division operation subunit, a floating point operation subunit, and a matrix operation subunit.

[0077] The general parallel operation unit 112 receives an enable signal from the operation scheduling unit 122. The disabled units maintain a low level to reduce power consumption. The enabled operation units select an operation path according to the signal of the operation scheduling unit 122, so that one of the integer operation subunit, the multiplication and division operation subunit and the floating-point operation subunit is effective.

[0078] The general parallel operation unit 112 can provide support for various integer, multiplication, division and floating-point algorithms, so the RISC-V main processor 2 does not require an additional computing coprocessor.

[0079] In addition, the integer operation subunit, the multiplication and division operation subunit and the floating-point operation subunit are used in a time-sharing manner, and there is no resource conflict, which allows a certain degree of circuit reuse, thereby improving performance while reducing power consumption.

[0080] The result processing unit 111 is controlled by the operation scheduling unit 122, and processes the intermediate results output by each general parallel operation unit 112 when processing integers, multiplications, divisions and floating-point operations exceeding the processor bit width, and outputs the final result.

[0081] The operation path selection subunit is a multiple-select-one data selector, which enables the corresponding operation unit according to the operation type of the operation scheduling unit 122 .

[0082] The integer operator unit can perform integer operations with a 2-bit width of the RISC-V main processor, and vector integer operations and integer operations exceeding the processor bit width are implemented in parallel through the integer operator units in multiple general parallel operation units 112.

[0083] The multiplication and division operator subunit can perform multiplication and division operations of the RISC-V main processor 2-bit width. Vector multiplication and division operations and multiplication and division operations exceeding the processor bit width are implemented in parallel through the multiplication and division operator subunits in multiple general parallel operation units 112.

[0084] The floating-point operation subunit can perform floating-point operations with a 2-bit width of the RISC-V main processor. Vector floating-point operations and floating-point operations exceeding the processor bit width are implemented in parallel through the floating-point operation subunits in multiple general parallel operation units 112.

[0085] The matrix operation subunit is actually a reuse of the floating-point operation subunit, and the matrix algorithm is implemented by converting the matrix operation into a multi-cycle vector operation through the scheduling module 12.

[0086] The instruction scheduling unit 121 includes an instruction cache subunit, an instruction decoding subunit and an instruction delivery subunit. The instruction scheduling unit 121 is responsible for controlling the instruction flow of the co-processing system, receiving instruction requests issued by the RISC-V main processor 2, caching instructions and decoding instructions, providing the decoding information to other components of the scheduling module 12, and delivering the instructions to the RISC-V main processor 2 after completing the calculation task and writing back the results.

[0087] The instruction cache subunit and the RISC-V main processor 2 implement instruction transmission through valid-ready handshake, and include a synchronization register to cache the current instruction.

[0088] The instruction decoding subunit is a pure combinational circuit that decodes the instructions in the instruction cache subunit and distributes the extracted results to the data scheduling unit 123 and the operation scheduling unit 122 .

[0089] The instruction delivery subunit and the RISC-V main processor 2 implement instruction delivery and result write back through valid-ready handshake, including synchronization registers to cache untransmitted results when multiple cycles are required to write back data.

[0090] Optionally, the data scheduling unit 123 includes an address generation subunit, a bus interface subunit, a data processing subunit, and a memory configuration subunit. The data scheduling unit 123 is responsible for controlling the data flow of the coprocessor system, receiving information from the operation scheduling unit 122, calculating the coprocessor read and write target address, managing the data interaction between the master and slave processors through the bus interface, implementing data verification and processing according to the data type, and implementing the configuration of data to the shared memory 13 according to the register index.

[0091] The address generation subunit receives information from the operation scheduling unit 122 and calculates the actual target address of the read and write instructions for use by the bus interface subunit.

[0092] The bus interface subunit and the RISC-V main processor 2 implement the memory access of the slave processor to the RISC-V main processor 2 memory through the valid-ready handshake protocol, receive the address information and access type from the address generation subunit, and manage the data interaction from the processor to the main memory. In order to avoid the occurrence of data conflicts, the bus interface subunit will initiate a request only when the slave processor computing task is cleared. In order to improve the efficiency of data transmission, the slave processor can directly access the general registers and system control registers of the RISC-V main processor 2 when there is no correlation conflict, but when writing back the general registers and system control registers, it still needs to go through the handshake protocol of the instruction delivery module.

[0093] The data processing subunit receives information from the operation scheduling unit 122, processes the obtained data according to the calculation type and data type, and obtains actual meaningful data.

[0094] The memory configuration subunit receives information from the operation scheduling unit 122, data from the data processing subunit, and data in the general registers and system control registers of the RISC-V main processor 2. According to the configuration of the system control register and the control of the scheduling operation module, the data of the data processing subunit and the data in the general registers of the RISC-V main processor 2 are configured, and written to the location specified by the shared memory 13 for use by the general parallel operation module 11.

[0095] Optionally, further, the operation scheduling unit 122 includes an operation scheduling subunit and an operation cache subunit.

[0096] The operation scheduling subunit is responsible for receiving information from the instruction decoding module, and performing hardware operation scheduling according to the operation type. For vector operations and multiplication and division that do not exceed the processor bit width, floating-point operations are directly scheduled and assigned to the operation unit for calculation; for matrix operations and multiplication and division that exceed the processor bit width, floating-point operations are indirectly scheduled and converted into multiple vector operations and multiplication and division that do not exceed the processor bit width, and then assigned to the operation unit for calculation after the floating-point operation.

[0097] The operation cache subunit is implemented by a synchronization register, which is responsible for storing operation scheduling information that requires multiple cycles to complete and storing the current completion progress. After all operations of the instruction are completed, it is delivered to the instruction delivery subunit for processing.

[0098] Optionally, the RISC-V main processor 2 is responsible for program execution. When executing non-extended instructions, the RISC-V main processor 2 itself completes the instruction operation; when executing extended instructions, the RISC-V main processor 2 will initiate an extended instruction operation request, and the coprocessor will complete the operation.

[0099] In order to further illustrate the RISC-V-based general parallel computing architecture coprocessing system provided by the present invention, the system execution process of the present invention is described below using a specific embodiment:

[0100] A specific example of the implementation of extended instructions by the present invention: after the RISC-V main processor initiates an extended instruction operation request, the instruction cache subunit of the coprocessor instruction scheduling unit responds, and the instruction cache subunit implements instruction transmission with the RISC-V main processor through the valid-ready handshake protocol, and caches the transmitted instructions. After the instruction cache subunit obtains a valid instruction request, the instruction decoding subunit of the coprocessor instruction scheduling unit decodes the instruction. The instruction decoding subunit is a pure combinational circuit, which extracts the decoding information and sends it to the operation scheduling unit.

[0101] After receiving the valid decoding information, the operation scheduling unit responds to the operation scheduling unit of the operation scheduling unit. The operation scheduling unit will schedule the operation task according to the operation type, and coordinate the control data scheduling unit and the general parallel operation module to complete the current operation task. For vector operations and multiplication and division that do not exceed the processor bit width, floating-point operations are directly scheduled and assigned to the operation unit for calculation. For matrix operations and multiplication and division that exceed the processor bit width, floating-point operations are indirectly scheduled and converted into multiple vector operations and multiplication and division that do not exceed the processor bit width, and then assigned to the operation unit for calculation after floating-point operations.

[0102] Taking matrix operation as an example, the specific parameter configuration of the present invention allows for custom settings. If the width of a single shared memory register is 32 bits, the vector register part is 32, and the general register part is 48, a 4×4×4 32-bit matrix multiplication operation is supported. When the operation scheduling unit receives a 4×4×4 32-bit matrix multiplication instruction, it decomposes it into 4 vector instructions, each of which implements 4 1×4 vector dot multiplication inner products. At the same time, the operation scheduling unit enables the result processing unit to add the results of the vector dot multiplication inner products to obtain the final output as a point of the output matrix. Since each vector instruction can process 4 vector inner products, only 4 cycles of vector operations are required to implement a 4×4×4 32-bit matrix multiplication.

[0103] For operation scheduling information that requires multiple cycles to complete, the operation scheduling unit will hand over the operation scheduling information and the current execution status to the operation cache sub-unit for storage, which is implemented by the synchronization register.

[0104] Taking matrix operations as an example, under the same configuration, the matrix instruction is hardware decoded into 4 vector instructions and stored in the operation cache subunit. The pipeline is blocked before the matrix instruction operation is completed, and the vector instruction operation is performed in sequence. Unexecuted vector instructions are stored in the instruction queue, and the execution module does not need additional registers to save the processing status. It only needs to execute the vector instructions in sequence. Shared memory realizes data sharing in this process, so the source operand does not need to be read and written every time a vector operation is performed. It only needs to be loaded once through the memory configuration module before the first vector operation, which reduces the frequency of data reading to 1 / 16, greatly reducing dynamic power consumption.

[0105] After receiving the control signal from the operation scheduling unit, the data scheduling unit responds by the address generation subunit. If the current instruction is a memory access instruction, the address generation subunit generates the corresponding memory address according to the decoding information and sends it to the bus interface subunit.

[0106] After receiving the control signal from the operation scheduling unit, the data processing subunit processes the read / write data of the bus interface subunit according to the data type and extracts / synthesizes the valid data.

[0107] After receiving the control signal and data address from the operation scheduling unit, the bus interface subunit will initiate a read / write request to the RISC-V main processor memory through the bus interface. After passing the valid-ready handshake protocol, the bus interface subunit completes the data transmission.

[0108] After receiving the control signal from the operation scheduling unit, the memory allocation unit will obtain data from the bus interface subunit and the RISC-V main processor register according to the source of the source operand, and write it to the specified location of the shared memory to complete the task of the data scheduling unit.

[0109] After the data scheduling is completed, the general parallel operation module that receives the operation scheduling unit control signal and the data scheduling completion signal will respond. The general parallel operation module will enable the corresponding number of general parallel operation units according to the operation scheduling requirements. The disabled units will maintain a low level to reduce power consumption. The enabled operation units will select the operation path according to the operation type of the scheduling module, so that one of the integer operation subunit, the multiplication and division operation subunit and the floating-point operation subunit is effective to complete the calculation task of the operation scheduling unit.

[0110] After the general parallel operation unit completes the calculation task, it will determine whether the result processing unit needs additional processing based on the control signal of the operation scheduling unit. The enabled result processing unit will process the intermediate results output by each general parallel operation unit when processing integers, multiplication, division and floating-point operations that exceed the processor bit width, and output the final result.

[0111] After the computing task is completed, the computing scheduling control unit will access the computing cache subunit to check whether there are any unexecuted computing tasks. If so, it will continue; if not, it will end the current instruction computing task and hand over the computing result and instruction delivery request to the instruction delivery subunit for processing.

[0112] After receiving the request from the operation scheduling unit, the instruction delivery subunit will try to communicate with the RISC-V main processor through the valid-ready handshake protocol to write back the results and deliver the instructions to complete the current task cycle.

[0113] Next, the workflow of the system is described. Figure 4 As shown, the implementation process may include:

[0114] S1: The RISC-V main processor initiates a request for acceleration of arithmetic instructions;

[0115] S2: The general parallel computing architecture co-processing system responds, receives the instruction and decodes it;

[0116] S3: Perform computational scheduling based on the decoding results and use parallelization to accelerate the computation of non-parallel tasks;

[0117] S4: configure the shared memory according to the operation scheduling information and enable the general parallel operation module;

[0118] S5: complete parallel computing and process the final result;

[0119] S6: Return the operation result and deliver the operation instruction acceleration request;

[0120] By executing the above steps S1-S6, the co-processing system accelerates the calculation to completion.

[0121] More specifically, the overall workflow of the present invention is:

[0122] When the RISC-V main processor executes an extended instruction, it will initiate an extended instruction request to the coprocessor, communicate with the instruction cache subunit of the coprocessor through the valid-ready protocol, the instruction cache subunit will synchronously store the current instruction, the instruction decoding subunit will decode the current instruction, and send the decoding information to the operation scheduling unit.

[0123] After receiving the valid request and decoding information, the operation scheduling unit will schedule the operation according to the operation type, and coordinate the control data scheduling unit and the general parallel operation module to complete the current operation task. Direct scheduling is performed for vector operations and operations that do not exceed the processor bit width, and indirect scheduling is performed for matrix operations and operations that exceed the processor bit width, which are converted into multiple vector operations and multiplication and division that do not exceed the processor bit width, and then allocated to the operation unit for calculation after floating-point operations.

[0124] The data scheduling unit will perform data scheduling according to the control signal sent by the operation scheduling unit. The address generation subunit calculates the address, the data processing subunit extracts valid data, the bus interface subunit and the RISC-V main processor storage complete the data transmission, and the memory allocation unit correctly writes the data to the corresponding position of the shared memory.

[0125] After receiving the data scheduling completion signal, the general parallel operation module will enable the corresponding number of general parallel operation units according to the control signal sent by the operation scheduling unit, and select the corresponding sub-operation module to operate on the shared memory data, and write it into the shared memory after the operation is completed. The result processing unit will decide whether to perform final processing on the intermediate results according to the control of the operation scheduling unit.

[0126] After the general parallel operation module completes the operation, the operation scheduling unit will access the operation cache sub-unit, and when there are no remaining computing tasks, it will hand over the current result and instruction delivery request to the instruction delivery module. The instruction delivery module will perform a valid-ready handshake with the RISC-V main processor to complete the current task cycle.

[0127] In summary, the general parallel computing architecture of the present invention can support multiplication, floating point, vector, matrix and other complex algorithms without the support of other computing coprocessors, so as to achieve the purpose of replacing multiple coprocessors with one coprocessor, and has significant advantages in the era of the Internet of Things where application requirements are increasingly diversified. In addition, the integer operator unit, multiplication and division operator unit, floating point operator unit and matrix operator unit inside the general parallel computing unit of the present invention are used in time-sharing, there is no resource conflict, and a certain degree of circuit reuse is allowed, so as to achieve improved performance while reducing power consumption and saving hardware resources. Finally, the shared memory of the present invention realizes data sharing inside the general parallel computing module and data interaction caching for external master-slave processors, without the need for additional coprocessing storage, optimizes the data transmission path, and reduces the performance and power consumption loss caused by meaningless reading and writing of data during circulation. Therefore, the present invention realizes a high-performance, low-power, widely used and flexible RISC-V coprocessing system.

[0128] More specifically, the beneficial effects of the present invention may include:

[0129] 1) The general parallel computing architecture of the present invention can support a variety of complex algorithms such as multiplication, floating point, vector, and matrix, without the need for support from other computing coprocessors, achieving the purpose of replacing multiple coprocessors with one coprocessor, which has significant advantages in the era of the Internet of Things where application requirements are becoming more and more diversified;

[0130] 2) The integer operator unit, multiplication and division operator unit, floating-point operator unit and matrix operator unit within the general parallel operation unit of the present invention are used in a time-sharing manner, and there is no resource conflict, allowing a certain degree of circuit reuse, thereby improving performance while reducing power consumption and saving hardware resources.

[0131] 3) The shared memory of the present invention realizes data sharing within the internal general parallel computing module and data interactive caching for external master and slave processors, without the need for additional co-processing storage, optimizes the data transmission path, and reduces performance and power consumption losses caused by meaningless reading and writing of data during circulation.

[0132] Therefore, the present invention realizes a high-performance, low-power, widely applicable and flexible RISC-V coprocessor system.

[0133] Next, the beneficial effects of shared memory in this solution are described in detail with reference to the accompanying drawings:

[0134] like Figure 5As shown in the figure, shared memory can optimize the original DRAM storage → L2 Cache → L1 Cache → Reg → MEM → Reg data path to DRAM storage → L2 Cache → SHARE-MEM; it reduces the redundant path of data reading from L2 Cache through registers; and it also avoids the waste of resources caused by the same reused data being loaded into different operation registers multiple times.

[0135] In addition, when performing 4bit×4bit×4bit matrix operations, using ordinary storage solutions, the same element needs to be loaded into the registers of different FMA units four times; while in shared memory, since different FMA units can access the specified locations of shared memory, the data only needs to be loaded directly into the shared memory; as the scale of matrix operations increases, the advantages of shared memory will become more obvious.

[0136] Although the present invention is described herein in conjunction with various embodiments, in the process of implementing the claimed invention, those skilled in the art may understand and implement other variations of the disclosed embodiments by viewing the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other components or steps, and "one" or "an" does not exclude multiple situations. A single processor or other unit may implement several functions listed in the claims. Certain measures are recorded in different dependent claims, but this does not mean that these measures cannot be combined to produce good results.

[0137] Although the present invention has been described in conjunction with specific features and embodiments thereof, it is apparent that various modifications and combinations may be made thereto without departing from the spirit and scope of the present invention. Accordingly, this specification and the accompanying drawings are merely exemplary illustrations of the present invention as defined by the appended claims and are deemed to cover any and all modifications, variations, combinations or equivalents within the scope of the present invention. Obviously, those skilled in the art may make various modifications and variations to the present invention without departing from the spirit and scope of the present invention. Thus, the present invention is intended to include such modifications and variations if they fall within the scope of the claims of the present invention and their equivalents.

Claims

1. A general parallel computing architecture coprocessing system based on RISC-V, characterized in that: The system includes: General parallel computing architecture coprocessor and RISC-V main processor; The general parallel computing architecture coprocessor includes: a general parallel computing module, a scheduling module and a shared memory; The scheduling module receives the operation request issued by the RISC-V main processor, and schedules the shared memory and controls the general parallel operation module according to the decoding information; The general parallel operation module operates on the data in the shared memory to obtain an operation result, and writes the operation result back to the shared memory.

2. The RISC-V-based general parallel computing architecture coprocessor system according to claim 1, characterized in that: The general parallel operation module includes a result processing unit and a plurality of general parallel operation units; The general parallel operation module receives the memory index provided by the scheduling module; Obtaining a source operand from the shared memory according to the memory index, performing a corresponding operation according to the operation type provided by the scheduling module, and writing the operation result back to the shared memory; The general parallel operation module is used to provide support for various algorithms such as multiplication, floating point, vector and matrix.

3. The RISC-V based general parallel computing architecture coprocessing system according to claim 2, characterized in that: The scheduling module includes an instruction scheduling unit responsible for instruction flow control, a data scheduling unit responsible for data flow control, and a calculation scheduling unit responsible for calculation task control; The scheduling module is used to decode the operation request, obtain decoding information, and generate scheduling logic according to the decoding information, configure the shared memory and control the general parallel operation module according to the scheduling logic, and return the operation result to the RISC-V main processor after the operation task is completed and deliver the current operation instruction.

4. The RISC-V-based general parallel computing architecture coprocessor system according to claim 2, characterized in that: The shared memory is implemented by a synchronization register; a data interaction interface is maintained between the shared memory, the scheduling module and each of the general parallel computing units, and the shared memory is used for data sharing within the general parallel computing module and for data interaction caching with external master and slave processors.

5. The RISC-V-based general parallel computing architecture coprocessor system according to claim 3, characterized in that: The general parallel computing unit comprises: An operation path selection subunit, an integer operation subunit, a multiplication and division operation subunit, a floating point operation subunit and a matrix operation subunit; The result processing unit is controlled by the operation scheduling unit, and processes the intermediate results output by each of the general parallel operation units when processing integers, multiplications, divisions and floating-point operations exceeding the processor bit width, and outputs the final result.

6. The RISC-V-based general parallel computing architecture coprocessor system according to claim 5, characterized in that: The operation path selection subunit is used to enable the corresponding operation unit according to the operation type of the operation scheduling unit; The integer operation subunit is used to perform integer operations of the bit width of the RISC-V main processor; Vector integer operations and integer operations exceeding the bit width of the processor are implemented in parallel by the integer operation subunits in a plurality of general parallel operation units; The multiplication and division operator unit is used to perform multiplication and division operations of the bit width of the RISC-V main processor; vector multiplication and division operations and multiplication and division operations exceeding the processor bit width are implemented in parallel by multiplication and division operator units in multiple general parallel operation units; The floating-point operation subunit is used to perform floating-point operations of the bit width of the RISC-V main processor; vector floating-point operations and floating-point operations exceeding the processor bit width are implemented in parallel by floating-point operation subunits in multiple general parallel operation units; The matrix operation subunit is used for reusing the floating-point operation subunit, and the matrix algorithm is implemented by converting the matrix operation into a multi-cycle vector operation through a scheduling module.

7. The RISC-V-based general parallel computing architecture coprocessor system according to claim 3, characterized in that: The instruction scheduling unit comprises: an instruction cache subunit, an instruction decode subunit, and an instruction delivery subunit; The instruction scheduling unit is responsible for controlling the instruction flow in the coprocessor, receiving instruction requests from the RISC-V main processor, caching instructions and decoding instructions, providing decoding information to other components of the scheduling module, and delivering instructions to the RISC-V main processor after completing the calculation task and writing back the results; The instruction cache subunit and the RISC-V main processor implement instruction transmission through valid-ready handshake, and the instruction cache subunit includes a synchronization register for caching the current instruction; The instruction decoding subunit is used to decode the instructions in the instruction cache subunit and distribute the extraction results to the data scheduling unit and the operation scheduling unit; The instruction delivery subunit and the RISC-V main processor implement instruction delivery and result write-back through valid-ready handshake; the instruction delivery subunit includes a synchronization register.

8. The RISC-V-based general parallel computing architecture coprocessor system according to claim 3, characterized in that: The data scheduling unit comprises: an address generation subunit, a bus interface subunit, a data processing subunit, and a memory configuration subunit; The data scheduling unit is responsible for controlling the data flow in the coprocessor, receiving information from the operation scheduling unit, calculating the coprocessor read and write target address, managing data interaction between the master and slave processors through the bus interface, implementing data verification and processing according to the data type, and configuring data to the shared memory according to the register index.

9. The RISC-V based general parallel computing architecture coprocessing system according to claim 8, characterized in that: The address generation subunit receives information from the operation scheduling unit and calculates the actual target address of the read and write instructions for use by the bus interface subunit; The bus interface subunit and the RISC-V main processor implement memory access from the processor to the RISC-V main processor memory through a valid-ready handshake protocol, receive address information and access type of the address generation subunit, and manage data interaction from the processor to the main memory; The data processing subunit receives information from the operation scheduling unit, processes the obtained data according to the calculation type and data type, and obtains target data; The memory configuration subunit receives information from the operation scheduling unit, data from the data processing subunit, and data in the general registers and system control registers of the RISC-V main processor, configures the data of the data processing subunit and the data in the general registers of the RISC-V main processor according to the configuration of the system control register and the control of the scheduling operation module, and writes them to the specified location of the shared memory for use by the general parallel operation module.

10. The RISC-V-based general parallel computing architecture coprocessor system according to claim 6, characterized in that: The operation scheduling unit comprises: A calculation scheduling subunit and a calculation cache subunit; The operation scheduling subunit is used to receive information from the instruction decoding module and perform hardware operation scheduling according to the operation type; Directly schedule vector operations, multiplication and division operations that do not exceed the processor bit width, and floating-point operations, and assign them to the operation unit for calculation; Indirect scheduling is performed for matrix operations and multiplication and division operations that exceed the processor bit width, as well as floating-point operations, which are converted into multiple vector operations and multiplication and division operations that do not exceed the processor bit width, and floating-point operations, and then assigned to the operation unit for calculation; The operation cache subunit is implemented by a synchronization register, which is responsible for storing operation scheduling information that requires multiple cycles to complete and storing the current completion progress.

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