Time delay calculation algorithm based on implicit circuit modeling and model order reduction algorithm

Abstract

The invention discloses a time delay calculation algorithm based on implicit circuit modeling and a model reduction algorithm, and the algorithm comprises the steps: S1, traversing the serial number of a circuit to a node, and representing a topological structure through a vector; s2, creating an equivalent implicit differential model of the circuit; s3, solving a linear system; s4, model order reduction is carried out through an improved Arnoldi algorithm; and S5, calculating the final time delay of the circuit through an iterative algorithm. The invention discloses a time delay calculation algorithm based on implicit circuit modeling and a model order reduction algorithm, and the time delay calculation efficiency and precision are remarkably improved through the methods of circuit model optimization, order reduction processing, characteristic value calculation, incremental updating of an iterative algorithm result and the like.

Description

Technical Field

[0001] The present invention belongs to the technical field of circuit delay calculation, and in particular relates to a delay calculation algorithm based on implicit circuit modeling and model order reduction algorithm. Background Art

[0002] Electronic Design Automation (EDA) refers to a collection of specialized software tools and methods used to design, analyze, and verify integrated circuits (ICs) and electronic systems. EDA tools cover the entire design process from the initial circuit concept to final manufacturing, including circuit simulation, layout and routing, logic synthesis, timing analysis, and other links. With the continuous advancement of semiconductor technology, the complexity and scale of integrated circuits have also increased dramatically, and EDA has become an essential tool for chip design and manufacturing. Through automation and efficient algorithms, designers can handle complex chip designs with billions of transistors, improve design efficiency and accuracy, shorten product development cycles, and reduce development costs.

[0003] Static Timing Analysis (STA) is a key method for verifying the timing characteristics of digital circuits. STA analyzes all possible paths in the circuit, evaluates the propagation time of the signal from input to output, and ensures that the circuit can work correctly within a given clock cycle. STA does not rely on specific input vectors, but performs a comprehensive timing check on the circuit, covering the timing performance in the worst case. Its main purpose is to ensure that the circuit can meet the timing requirements under various operating conditions (such as temperature, process, voltage changes, etc.) to avoid functional errors caused by timing problems. STA is widely used in various stages of digital IC design, including architecture evaluation in the early stage of design, optimization and adjustment during the design process, and timing verification after the design is completed. It helps designers identify and fix potential timing problems and improves the reliability and performance of the chip.

[0004] Delay Calculation calculates the signal propagation time in the circuit, which is a key step to ensure the correctness and efficiency of static timing analysis. Delay calculation is mainly divided into two parts: Gate Delay and Wire Delay. Gate delay refers to the time it takes for a signal to pass through a logic gate (such as an inverter, AND gate, or OR gate). It includes the time required from the input signal changing to the output signal stabilizing. Wire delay refers to the time it takes for a signal to pass through the circuit wiring (interconnection wire). This includes the transmission time of the signal in the wiring, as well as the delay caused by wiring resistance and capacitance.

[0005] Existing delay calculation methods usually include the following main steps. First, the designer needs to establish a set of differential equations that describe the circuit behavior based on the circuit topology and component characteristics. These equations usually reflect the dynamic response of components such as capacitors, resistors, and inductors. Secondly, the model reduction technique is used to simplify the high-order system into a low-order system to simplify the calculation. Commonly used methods include order reduction techniques in the time domain and frequency domain, such as the Krylov subspace method. However, the model reduction process itself is computationally intensive, and the key dynamic characteristics of the system need to be maintained during the order reduction process, which increases the complexity of the calculation. Based on the reduced-order model, the designer needs to calculate the transfer function of the system to describe the relationship between the input signal and the output signal. When calculating the transfer function, it is necessary to solve the eigenvalue problem of the asymmetric matrix, which is a task with high computational complexity and easy to introduce numerical errors. Finally, in order to obtain the delay of the circuit, the designer uses an iterative algorithm to repeat the above steps to iteratively approximate the theoretical solution and calculate the final delay of the circuit.

[0006] One of the main problems faced by existing delay calculation methods is the huge amount of calculation. As the scale of the circuit increases, the size of the matrix in the differential equation grows quadratically, and the model reduction and eigenvalue calculation are also very complicated, resulting in a significant increase in the overall amount of calculation. The iterative process needs to repeat the above steps, which further increases the amount of calculation. At the same time, the stability of the calculation is also a challenge. In the process of model reduction, if it is not handled properly, the key characteristics of the system may be lost, resulting in inaccurate results; in the calculation of the eigenvalues ​​of asymmetric matrices, numerical instability is easily introduced; in the iterative process, numerical errors may gradually accumulate, resulting in an increase in the error of the final result, and even leading to the collapse of the STA calculation.

[0007] Therefore, further improvements are made to the above problems. Summary of the invention

[0008] The main purpose of the present invention is to provide a delay calculation algorithm based on implicit circuit modeling and model order reduction algorithm, which significantly improves the efficiency and accuracy of delay calculation by optimizing circuit models, reducing order processing, eigenvalue calculation, incremental updating of iterative algorithm results and other methods.

[0009] To achieve the above objectives, the present invention provides a delay calculation algorithm based on implicit circuit modeling and model reduction algorithm, comprising the following steps:

[0010] Step S1: traverse the numbering of nodes in the circuit and use vectors to represent the topological structure;

[0011] Step S2: creating an equivalent implicit differential model of the circuit;

[0012] Step S3: solving the linear system;

[0013] Step S4: Model reduction is performed using an improved Arnoldi algorithm (C-Arnoldi algorithm);

[0014] Step S5: Calculate the final delay of the circuit through an iterative algorithm.

[0015] As a further preferred technical solution of the above technical solution, for step S1, the RC network of the circuit is efficiently represented by an RC network representation model, and the RC network representation model includes a RES vector, a CAPS vector and a SRCS vector, wherein:

[0016] The RES vector is used to record all resistance values;

[0017] The CAPS vector is used to record all capacitance values;

[0018] The SRCS vector is used to record the topological structure of the RC network (the SRCS vector is obtained by graph traversal, including but not limited to breadth-based traversal (BFS) and depth-based traversal (DFS), and the value in the SRCS vector must be smaller than its index value).

[0019] As a further preferred technical solution of the above technical solution, for step S2, implicit expression is performed through a small vector including a RES vector, a CAPS vector and a SRCS vector, and the equivalent implicit differential model is specifically constructed as follows:

[0020] G=A g ·diag(1 / RES)·A g T ;

[0021] C=A c ·diag(CAPS)·A c T ;

[0022] Among them, G represents the admittance matrix, C represents the capacitance matrix, and A g and A c is the adjacency matrix of resistors and capacitors in the circuit. The diag() function is used to construct a diagonal matrix. Without considering the coupling capacitor, A c That is, the identity matrix, A g It is constructed through SRCS vector, specifically:

[0023] Starting from the identity matrix, for each column of the matrix, use its serial number as the index value to search in the SRCS vector, and use the search number as the serial number of the matrix row, and replace A g The matrix element in this column and row is set to -1. In this way, A g The matrix is ​​guaranteed to be upper triangular.

[0024] As a further preferred technical solution of the above technical solution, for step S3, the linear system is directly solved by an equivalent implicit differential model and completed in linear time (without the need for matrix decomposition of traditional methods, such as LU decomposition and QR decomposition), which is specifically implemented as follows:

[0025] Gx=C·b

[0026] A g y=C·b

[0027] A g T x = RES.*y;

[0028] Using A g The matrix is ​​an upper triangular matrix, and the LU decomposition of the G matrix is ​​directly obtained, thereby obtaining an efficient linear system solver, which is divided into two steps;

[0029] First, use A g Matrix Solution A g y = C·b This linear system, thereby obtaining the solution of y, this step takes O(n) time;

[0030] The second step is to solve A g *x=y, thus obtaining the solution of x, this step also takes O(n) time.

[0031] As a further preferred technical solution of the above technical solution, for the algorithm of step S4, the algorithm is based on the normal form of the vector with respect to the diagonal matrix C, called the C-normal form, and the formula is defined as:

[0032]

[0033] Given matrices G and C, construct an orthogonal basis about the C matrix. The first basis vector is:

[0034]

[0035] Its value is vector G -1 b, and normalize it to C-normal form. The second and subsequent basis vectors are constructed based on the previous basis vectors. -1 C i Project to the subspace generated by the first 1, 2…i basis vectors, and normalize the projection residual as the next basis vector. The formula is:

[0036] v=G -1 C i ;

[0037]

[0038] Among them, v is the initial vector for calculating the next basis vector, is its preceding basis vector q j The projection component on the vector q is obtained by subtracting the projection component. i+1 The matrix C is perpendicular to all the basis vectors q1, q2, ..., q i , and finally normalize it to get the next basis vector. Finally, all basis vectors generate Krvlov subspace. Under this orthogonal basis about C matrix, the initial G -1 The C matrix is ​​transformed into a tridiagonal matrix;

[0039] This is an iterative algorithm and can be stopped midway. For each iteration of the algorithm, a fast linear solver is used to solve the linear system A*b, and then an orthogonal basis symmetric about the C matrix is ​​obtained through a non-orthogonal projection algorithm. These orthogonal bases constitute the projection matrix Q, and the coordinates under the orthogonal basis constitute the reduced-order matrix H. The H matrix is ​​a symmetric tridiagonal matrix, so the diagonal elements and sub-diagonal elements are calculated. The complexity of the algorithm is O(n / k), where k is the system dimension to be reduced.

[0040] As a further preferred technical solution of the above technical solution, for step S5, the iterative process needs to repeat the above steps multiple times to approximate the actual delay value. In each iterative process, after the model of the gate circuit is updated, the characteristics of the improved Arnoldi algorithm (i.e., C-Arnoldi algorithm) are used, and there is no need to perform a completely new model reduction, so as to ensure that the projection matrix Q does not change, and only the reduced-order matrix H needs to be locally updated;

[0041] Specifically, when the gate circuit model is updated and its internal source resistance changes, only the last diagonal element of the reduced-order matrix H needs to be updated as follows:

[0042]

[0043] in:

[0044] A r : The value of the last diagonal element of matrix A under the original resistance value;

[0045] The updated value of the last diagonal element of the A matrix after the resistance value is updated, where u represents update.

[0046] Δr: resistance value change (Δr = r new -r old );

[0047] ∑c i : The sum of all capacitance values;

[0048] e1: unit vector, the first element of the vector is 1, and the others are 0, e1 = [1; 0; ...];

[0049] e1 ′ : The transpose of a unit vector, or row vector.

[0050] The beneficial effects of the present invention are:

[0051] 1. More efficient model representation

[0052] By implicitly constructing the differential equation model corresponding to the circuit and using O(n) vectors to replace O(n^2) matrices, an efficient circuit model expression is obtained, which helps to greatly reduce the algorithm's memory requirements and solves the problem of memory limitations on parallel hardware (which is beneficial to GPUs).

[0053] 2. Optimize the amount of calculation

[0054] First, through the implicit circuit model, the LU matrix is ​​automatically obtained, avoiding the LU decomposition of O(n^3) complexity. Thereby reducing the complexity of the linear system from O(n^4) to O(n^2). Secondly, the C-Arnoldi algorithm uses a linear solver, and the algorithm complexity is more efficient than the traditional Krylov subspace algorithm. At the same time, the result is a tridiagonal matrix, and the calculation of its eigenvalues ​​is greatly reduced from O(n^3) to O(n^2). At the same time, its characteristic matrix does not require additional calculations, further optimizing performance and memory. In the iterative algorithm, incremental updates only need to update one element, reducing the algorithm complexity by one dimension.

[0055] 3. Enhanced numerical stability

[0056] The efficient model makes the linear system solver and C-Arnoldi algorithm more stable and reduces the occurrence of extreme situations. The C-Arnoldi algorithm ensures that the result is a symmetric tridiagonal matrix, which greatly improves the stability of subsequent eigenvalue calculations. There is no need to deal with complex situations such as eigenvalues ​​being complex numbers, and ensures that the system is still stable after order reduction. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] Figure 1 It is a schematic diagram of the process of the present invention. DETAILED DESCRIPTION

[0058] The following description is used to disclose the present invention so that those skilled in the art can implement the present invention. The preferred embodiments described below are only examples, and those skilled in the art can think of other obvious variations. The basic principles of the present invention defined in the following description can be applied to other embodiments, variations, improvements, equivalents, and other technical solutions that do not deviate from the spirit and scope of the present invention.

[0059] In the preferred embodiments of the present invention, those skilled in the art should note that the time delay and the like involved in the present invention may be regarded as prior art.

[0060] Preferred embodiments.

[0061] like Figure 1 As shown, the present invention discloses a delay calculation algorithm based on implicit circuit modeling and model reduction algorithm, comprising the following steps:

[0062] Step S1: traverse the numbering of nodes in the circuit and use vectors to represent the topological structure;

[0063] Step S2: creating an equivalent implicit differential model of the circuit;

[0064] Step S3: Solve the linear system (i.e., the HX linear solver in the figure);

[0065] Step S4: Model reduction is performed using an improved Arnoldi algorithm (C-Arnoldi algorithm);

[0066] Step S5: Calculate the final delay of the circuit through an iterative algorithm.

[0067] Specifically, for step S1, the RC network of the circuit is efficiently represented by an RC network representation model, and the RC network representation model includes a RES vector, a CAPS vector and a SRCS vector, wherein:

[0068] The RES vector is used to record all resistance values;

[0069] The CAPS vector is used to record all capacitance values;

[0070] The SRCS vector is used to record the topological structure of the RC network (the SRCS vector is obtained by graph traversal, including but not limited to breadth-based traversal (BFS) and depth-based traversal (DFS), and the value in the SRCS vector must be smaller than its index value).

[0071] More specifically, the voltage response of the circuit can be represented by a set of differential equations, which reflect the relationship between the voltage and current of each node in the circuit in matrix form. The basic equation is:

[0072] Where G represents the admittance matrix, C represents the capacitance matrix, V is the node voltage vector, and Vin is the input voltage. The present invention does not explicitly construct large matrices such as G and C. Instead, it uses small vectors such as RES, CAPS, and SRCS to implicitly express)

[0073] For step S2, implicit expression is performed through a small vector including RES vector, CAPS vector and SRCS vector. The specific construction method of the equivalent implicit differential model is as follows:

[0074] G=A g ·diag(1 / RES)·A g T ;

[0075] C=A c ·diag(CAPS)·A c T ;

[0076] Among them, G represents the admittance matrix, C represents the capacitance matrix, and A g and A c is the adjacency matrix of resistors and capacitors in the circuit. The diag() function is used to construct a diagonal matrix (RES and CAPS are the above vectors, where each element represents the resistance and capacitance value at the circuit node, A g T represents matrix transpose), without considering the coupling capacitance, A c That is, the identity matrix, A g It is constructed through SRCS vector, specifically:

[0077] Starting from the identity matrix, for each column of the matrix, use its serial number as the index value to search in the SRCS vector, and use the search number as the serial number of the matrix row, and replace A g The matrix element in this column and row is set to -1. In this way, A g The matrix is ​​guaranteed to be upper triangular.

[0078] Furthermore, for step S3, (for the linear system Gx=Cb or its variant x=A*b) the linear system is directly solved by an equivalent implicit differential model and completed in linear time (without the matrix decomposition of the traditional method, such as LU decomposition, QR decomposition), which is specifically implemented as follows:

[0079] Gx=C·b

[0080] A g y=C·b

[0081] A g T x = RES.*y;

[0082] Among them, RES.*y is a dot product operation. RES and y are both vectors. Each element in the vector is multiplied to obtain a new vector. For example, the first element of RES is multiplied by the first element of y to obtain the first element of the result vector, and so on.

[0083] Using Ag The matrix is ​​an upper triangular matrix, and the LU decomposition of the G matrix is ​​directly obtained, thereby obtaining an efficient linear system solver, which is divided into two steps;

[0084] First, use A g Matrix Solution A g y = C·b This linear system, thereby obtaining the solution of y, this step takes O(n) time;

[0085] The second step is to solve A g *x=y, thus obtaining the solution of x, this step also takes O(n) time.

[0086] Furthermore, the algorithm of step S4 is an improvement on the traditional Krylov subspace method Arnoldi algorithm (no longer constructing a standard orthogonal basis, but constructing an orthogonal basis about the C matrix. Its advantage is that it does not require the input matrix to be a symmetric matrix, and for an asymmetric matrix, it can also ensure that the reduced-order matrix after projection is a symmetric tridiagonal matrix). The algorithm is based on the normal form of the vector about the diagonal matrix C, called the C-normal form, and the formula is defined as:

[0087]

[0088] Given matrices G and C, construct an orthogonal basis about the C matrix. The first basis vector is:

[0089]

[0090] Its value is vector G -1 b, and normalize it to C-normal form. The second and subsequent basis vectors are constructed based on the previous basis vectors. -1 C i Project to the subspace generated by the first 1, 2…i basis vectors, and normalize the projection residual as the next basis vector. The formula is:

[0091] v=G -1 C i ;

[0092]

[0093] Among them, v is the initial vector for calculating the next basis vector, is its preceding basis vector q j The projection component on the vector q is obtained by subtracting the projection component. i+1 The matrix C is perpendicular to all the basis vectors q1, q2, ..., q i , and finally normalize it to get the next basis vector. Finally, all basis vectors generate Krvlov subspace. Under this orthogonal basis about C matrix, the initial G-1 The C matrix is ​​transformed into a tridiagonal matrix; the tridiagonal matrix can use two vectors d and e to represent the matrix diagonal elements and subdiagonal elements respectively, thus avoiding the construction of a complete matrix, saving space and speeding up calculations;

[0094] This is an iterative algorithm and can be stopped midway. For each iteration of the algorithm, a fast linear solver is used to solve the linear system A*b, and then an orthogonal basis symmetric about the C matrix is ​​obtained through a non-orthogonal projection algorithm. These orthogonal bases constitute the projection matrix Q, and the coordinates under the orthogonal basis constitute the reduced-order matrix H. The H matrix is ​​a symmetric tridiagonal matrix, so (only) the diagonal elements and sub-diagonal elements need to be calculated. The algorithm complexity is O(n*k), where k is the system dimension to be reduced to (the C-Arnoldi algorithm can be combined with the single matrix projection method to obtain an equivalent system after reduction. The pole and residue of the equivalent system are obtained through eigenvalues, and the eigenvalues ​​of the tridiagonal matrix are implemented through efficient algorithms such as QR. C-Arnoldi can be combined with the double matrix projection method (Double Matrix Projection), and its scope of application includes double matrix projection methods such as PRIMA, and the result is still a symmetric tridiagonal matrix).

[0095] Preferably, for step S5, the iterative process needs to repeat the above steps (steps S1-S4) multiple times to approximate the actual delay value. In each iterative process (the traditional method needs to update the model of the gate circuit and re-reduce the system), after the model of the gate circuit is updated (in step S2, specifically, the RES vector needs to be updated each time), the characteristics of the improved Arnoldi algorithm (i.e., C-Arnoldi algorithm) are used, and there is no need to perform a completely new model reduction, ensuring that the projection matrix Q does not change, and only the reduced-order matrix H needs to be locally updated;

[0096] Specifically, when the gate circuit model is updated and its internal source resistance changes, only the last diagonal element of the reduced-order matrix H needs to be updated as follows:

[0097]

[0098] in:

[0099] A r : The value of the last diagonal element of matrix A under the original resistance value;

[0100] The updated value of the last diagonal element of the A matrix after the resistance value is updated, where u represents update.

[0101] Δr: resistance value change (Δr = rnew -r old );

[0102] ∑c i : The sum of all capacitance values;

[0103] e1: unit vector, the first element of the vector is 1, and the others are 0, e1 = [1; 0; ...];

[0104] e1 ′ : The transpose of a unit vector, or row vector.

[0105] for Figure 1 The compute node waveform in:

[0106] 1. Perform eigenvalue decomposition on the A matrix to obtain the transfer function;

[0107] 2. Solve differential equations in the s-domain;

[0108] 3. Obtain the waveform function in the time domain through inverse Laplace transform.

[0109] For the present invention:

[0110] 1. Represent the topological relationship of the RC network through vectors, including:

[0111] Sort and number the RC nodes. The capacitor number on each node is the number of its non-ground node, and the resistor number is the larger number of the nodes at both ends. The numbering method can be, but is not limited to, breadth-first search (BFS) and depth-first search (DFS).

[0112] The smaller number of the nodes at both ends of the resistor is stored in the vector SRCS, which is used to represent the topology of the RC network.

[0113] Characteristics: The value in SRCS is less than its index value.

[0114] Scope of application: acyclic RC networks, including single-input multi-output RC networks and multi-input multi-output RC networks.

[0115] 2. Construct an equivalent ODE model of the circuit through three vectors, including:

[0116] The critical matrix of resistors is constructed by SRCS, which is an upper triangular matrix.

[0117] The implicit way to construct the G and C matrices. The G and C matrices will not be generated, which reduces memory consumption and improves performance.

[0118] A linear O(n) solver that efficiently solves the linear system Ax = b. This method does not require explicit matrix construction or matrix decomposition.

[0119] Features: does not explicitly construct the system matrix, does not decompose the matrix, and has linear complexity.

[0120] Scope of application: ODE models and corresponding linear systems corresponding to the acyclic RC networks of numerical circuits.

[0121] 3. C-Arnoldi projection method, including:

[0122] The projection process constructs an orthogonal basis based on the diagonal matrix C. This basis is not a standard orthogonal basis.

[0123] The result of projecting an arbitrary matrix is ​​a tridiagonal matrix.

[0124] Solve the tridiagonal matrix, obtain the eigenvalues, and calculate the pole process of the RC network transfer function.

[0125] Features: During the projection process, an orthogonal basis about a matrix is ​​constructed instead of a standard orthogonal basis.

[0126] Scope of application: Projection algorithms for arbitrary square matrices, including but not limited to Krylov subspace projection and iterative algorithms.

[0127] 4. Single matrix projection method based on C-Arnoldi, including:

[0128] Convert it into a single matrix system, reduce the Krylov model by C-Arnoldi to obtain a smaller system, and solve the pole and residue process of the transfer function.

[0129] Instead of solving for the final pole and residue, the absolute value of the pole and the ratio of the residue to the absolute value of the pole are solved. This is a method for solving the waveform function without the final values ​​of the pole and residue.

[0130] Incremental update method. When the values ​​of adjacent input resistors change, the reduced-order model of the new system can be obtained by modifying the last value in the matrix. Applied to the STA iterative algorithm, more than 4x performance improvement is achieved.

[0131] Features: C-Arnoldi algorithm is applied in the single matrix projection method. Model reduction is not recalculated in STA iterations, but incremental modifications are performed.

[0132] Scope of application: Single matrix projection method is used to reduce the order of a system, including but not limited to reducing the order of a circuit system.

[0133] 5. Double matrix projection method based on C-Arnoldi, including:

[0134] The G and C matrices are reduced in order through C-Arnoldi, and then the transfer function is solved.

[0135] Incremental update method: When the values ​​of adjacent input resistors change, there is no need to recalculate the reduced-order G and C matrices. Only the last diagonal value of G^-1C needs to be recalculated to obtain the reduced-order model of the new system.

[0136] Features: C-Arnoldi projection is used in dual matrix projection methods (such as PRIMA).

[0137] Scope of application: PRIMA method is used to reduce the order of the system.

[0138] It is worth mentioning that the technical features such as time delay involved in the patent application of this invention should be regarded as the prior art. The specific structure, working principle and possible control method and spatial layout method of these technical features can be selected by conventional methods in the field, and should not be regarded as the inventive point of this patent. This patent will not be further elaborated.

[0139] For those skilled in the art, it is still possible to modify the technical solutions described in the aforementioned embodiments, or to make equivalent substitutions for some of the technical features therein. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A delay calculation algorithm based on implicit circuit modeling and model order reduction algorithm, characterized in that: The following steps are involved: Step S1: traverse the numbering of nodes in the circuit and use vectors to represent the topological structure; Step S2: creating an equivalent implicit differential model of the circuit; Step S3: solving the linear system; Step S4: Model reduction is performed using the improved Arnoldi algorithm; Step S5: Calculate the final delay of the circuit through an iterative algorithm.

2. The delay calculation algorithm based on implicit circuit modeling and model reduction algorithm according to claim 1, characterized in that: For step S1, the RC network of the circuit is efficiently represented by an RC network representation model, and the RC network representation model includes a RES vector, a CAPS vector, and a SRCS vector, wherein: The RES vector is used to record all resistance values; The CAPS vector is used to record all capacitance values; The SRCS vector is used to record the topology of the RC network.

3. The delay calculation algorithm based on implicit circuit modeling and model reduction algorithm according to claim 2, characterized in that: For step S2, implicit expression is performed through a small vector including RES vector, CAPS vector and SRCS vector. The specific construction method of the equivalent implicit differential model is as follows: G=A g ·diag(1 / RES)·A g T ; C=A c ·diag(CAPS)·A c T 。 Among them, G represents the admittance matrix, C represents the capacitance matrix, and A g and A c is the adjacency matrix of resistors and capacitors in the circuit. The diag() function is used to construct a diagonal matrix. Without considering the coupling capacitor, A c That is, the identity matrix, A g It is constructed through SRCS vector, specifically: Starting from the identity matrix, for each column of the matrix, use its serial number as the index value to search in the SRCS vector, and use the search number as the serial number of the matrix row, and replace A g The matrix element in this column and row is set to -1. In this way, A g The matrix is ​​guaranteed to be upper triangular.

4. The delay calculation algorithm based on implicit circuit modeling and model reduction algorithm according to claim 3, characterized in that: For step S3, the linear system is solved directly through the equivalent implicit differential model and completed in linear time without LU decomposition. The specific implementation is: Gx=C·b A g y=C·b TO g T x=RES.*y; Using A g The matrix is ​​an upper triangular matrix, and the LU decomposition of the G matrix is ​​directly obtained, thereby obtaining an efficient linear system solver, which is divided into two steps; First, use A g Matrix Solution A g y = C·b This linear system, thereby obtaining the solution of y, this step takes O(n) time; The second step is to solve A g *x=y, thus obtaining the solution of x, this step also takes O(n) time.

5. The delay calculation algorithm based on implicit circuit modeling and model reduction algorithm according to claim 4, characterized in that: The algorithm of step S4 is an improvement on the traditional Krylov subspace method Arnoldi algorithm. The algorithm is based on the normal form of the vector about the diagonal matrix C, called C-normal form, and the formula is defined as: Given matrices G and C, construct an orthogonal basis about the C matrix. The first basis vector is: Its value is vector G -1 b, and normalize it to C-normal form. The second and subsequent basis vectors are constructed based on the previous basis vectors. -1 C i Project to the subspace generated by the first 1, 2…i basis vectors, and normalize the projection residual as the next basis vector. The formula is: v=G -1 Cq i ; Among them, v is the initial vector for calculating the next basis vector, is its preceding basis vector q j The projection component on the vector q is obtained by subtracting the projection component. i+1 The matrix C is perpendicular to all the basis vectors q1, q2, ..., q i , and finally normalize it to get the next basis vector. Finally, all basis vectors generate Krvlov subspace. Under this orthogonal basis about C matrix, the initial G -1 The C matrix is ​​transformed into a tridiagonal matrix; This is an iterative algorithm and can be stopped midway. For each iteration of the algorithm, a fast linear solver is used to solve the linear system A*b, and then an orthogonal basis symmetric about the C matrix is ​​obtained through a non-orthogonal projection algorithm. These orthogonal bases constitute the projection matrix Q, and the coordinates under the orthogonal basis constitute the reduced-order matrix H. The H matrix is ​​a symmetric tridiagonal matrix, so the diagonal elements and sub-diagonal elements are calculated. The complexity of the algorithm is O(n*k), where k is the system dimension to be reduced.

6. The delay calculation algorithm based on implicit circuit modeling and model reduction algorithm according to claim 5, characterized in that: For step S5, the iteration process needs to repeat the above steps multiple times to approximate the actual delay value. In each iteration process, when the gate circuit model is updated, the characteristics of the improved Arnoldi algorithm are used, and there is no need to perform a completely new model reduction to ensure that the projection matrix Q does not change. Only the reduced-order matrix H needs to be locally updated; Specifically, when the gate circuit model is updated and its internal source resistance changes, only the last diagonal element of the reduced-order matrix H needs to be updated as follows: in: A r : The value of the last diagonal element of matrix A under the original resistance value; The updated value of the last diagonal element of the A matrix after the resistance value is updated, u represents the update; Δr: change in resistance value; ∑c i : The sum of all capacitance values; e1: unit vector, the first element of the vector is 1, and the others are 0, e1 = [1; 0; ...]; e′1: The transpose of the unit vector, that is, the row vector.

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