92 results about "Circuit modeling" patented technology

The invention discloses a ray tracing-based optical camera simulation imaging method and system. The method comprises optical system simulation, and imaging and photoelectric system simulation, wherein the optical system simulation comprises optical system modeling, camera distortion modeling simulation, camera defocused spot modeling simulation and camera stray light modeling simulation; and the imaging and photoelectric system simulation comprises a spectrum response analysis module, CCD photoelectric conversion modeling simulation, analog circuit modeling simulation and digital-analog quantification modeling simulation. According to the method and the system, influence factors of an optical system and a CCD imaging system of a remote sensing camera to an imaging result are comprehensively considered; a detailed and complete remote sensing camera parameter database is established; a simulated image and a real image have higher close degree; and relatively high simulation precision is achieved.

The invention discloses a hybrid switching system theory-based Buck circuit modeling method and application thereof. The method comprises the following working steps of: 1, analyzing a Buck circuit, portioning a state space, and determining the number of working states; 2, determining switching conditions among the working states; 3, establishing a sate equation and an output equation of the Buck circuit; 4, determining a state matrix, an input matrix and an output matrix of a system according to circuit parameters; and 5, establishing a model of the Buck circuit based on the hybrid switching system theory. By utilizing the hybrid switching system theory, the modeling of the Buck circuit is accurate, and system stability and control performance are accurately analyzed, particularly complicated characteristics of a converter system caused by switching; and the Buck circuit has the advantages of simple structure, small volume, high conversion efficiency and the like.

The invention provides a finite state machine-based Boost circuit modeling method and application thereof. The modeling method is characterized by comprising the following steps: (1) determining the number of operational states; (2) determining conversion conditions among the operational states; (3) establishing a mathematical equation; (4) determining a matrix according to parameters; and (5) building a model. The modeling method has the advantages that the Boost circuit model built by using the finite state machine is very precise and is easy to analyze the control characteristics of a system, especially a plurality of complicated characteristics caused by the switching of a switch in a converter system. The Boost circuit has the advantages of small volume, simple structure, high conversion efficiency and so on.

The present invention is a substrate dependent circuit modeling system for substrate-mounted components. The height and dielectric constant of a substrate have a significant impact on the frequency response of such components, and these effects cannot be treated independently from the circuit model. The equivalent circuit parameters in the model must be made to vary in accordance with changes in the substrate. The invention includes the steps of selecting a substrate mounted electrical circuit component for which an equivalent circuit model is desired, determining equivalent circuit model input parameters, wherein some of which are dependent upon characteristics of the substrate upon which the component is mounted, for the selected component, representing the selected electrical circuit component mounted upon the substrate as an equivalent electrical circuit, formulating mathematical expressions based upon the input parameters, and creating a unique equivalent circuit model for the component mounted upon the given substrate, the unique equivalent circuit model representing the mounting of the component upon the given substrate wherein the equivalent circuit model provides behavior and performance predictions of the component based upon the given substrate characteristics.

A computer-implemented method of determining parasitic capacitance for transistors within an integrated circuit can include determining a first set of coefficients for a first expression that calculates parasitic capacitance for a transistor structure according to a first plurality of parasitic capacitances derived from a plurality of two-dimensional transistor structures (320). The first set of coefficients can be inserted into the first expression (325). The method further can include determining a second set of coefficients for a second expression that calculates parasitic capacitance for a transistor structure according to a second plurality of parasitic capacitances derived from a plurality of three-dimensional transistor structures (345). The second expression can include the first expression (350). The method can include inserting the second set of coefficients into the second expression and outputting the second expression (355).

A method for generating a model for a circuit having logic components is provided. The method includes identifying interface path logic components of the logic components so as to define shell logic, and identifying at least one of the logic components on which a constraint has been annotated so as to define constrained logic components. A subset of the logic components to preserve is then determined, the subset including the shell logic and the constrained logic components so as to define preserved logic. The model is then formed from the preserved logic. A highly accurate model can thus be created, while reducing computational and memory requirements. On-the-fly regeneration of the model is also possible, as is dominant path logic preservation.

Disclosed is a computer implemented method and computer program product to determine metal oxide semiconductor (MOS) gate functional limitations. A simulator obtains a plurality of slices of a MOS gate, the slices each comprising at least one parameter, the parameter comprising a slice gate width and a slice gate length. The simulator determines a current for each slice based on a slice gate length of the slice to form a length-based current for each slice. The simulator determines a length-based current for the MOS gate by summing the length-based current for each slice. The simulator calculates a stress profile for each slice. The simulator determines a slice carrier mobility for each slice based on the stress profile of each slice. The simulator determines a carrier mobility-based current for each slice, based on each slice carrier mobility. The simulator determines a carrier mobility for the MOS gate based on the carrier mobility-based current for each slice. The simulator determines an effective length for the MOS gate based on the length-based current.

Apparatus and systems, as well as methods and articles, may perform operations including selecting a monitor associated with a property of a circuit module, augmenting the circuit module with the monitor to provide an augmented circuit, searching for a test for an output of the augmented circuit to find a sequence of states having a length up to n, establishing a witness to the property if the test is found, and if no test is found to exist within the sequence of states, determining the property to be invalid or false for a bound of n.

The present invention is a substrate dependent circuit modeling system for substrate-mounted components. The height and dielectric constant of a substrate have a significant impact on the frequency response of such components, and these effects cannot be treated independently from the circuit model. The equivalent circuit parameters in the model must be made to vary in accordance with changes in the substrate. The invention includes the steps of selecting a substrate mounted electrical circuit component for which an equivalent circuit model is desired, determining equivalent circuit model input parameters, wherein some of which are dependent upon characteristics of the substrate upon which the component is mounted, for the selected component, representing the selected electrical circuit component mounted upon the substrate as an equivalent electrical circuit, formulating mathematical expressions based upon the input parameters, and creating a unique equivalent circuit model for the component mounted upon the given substrate, the unique equivalent circuit model representing the mounting of the component upon the given substrate wherein the equivalent circuit model provides behavior and performance predictions of the component based upon the given substrate characteristics.

A method is provided for designing and implementing a circuit comprising an integrated circuit (IC) including a number of analog and digital circuit elements for which operating parameters can be set. In one embodiment the method includes entering in a circuit design tool embodied in a computer readable medium on a server specified requirements for a circuit, the specified requirements including physical properties to be sensed by the circuit. The circuit is automatically modeled by the circuit design tool based on the specified requirements and resources available on the IC, the modeling including translating the specified requirements into parameter settings of the number of the analog and digital circuit elements. The circuit is then built, the building including setting parameters of at least one of the analog and digital circuit elements of the IC using the circuit design tool based on the modeling of the circuit.

In a method of determining air humidity, a capacitive moisture measuring element (2) used in a moisture sensor for calculation operations is modelled by a parallel circuit of an ideal capacitor (C) and an ohmic resistance (Rp). Charging and/or discharging of the capacitive moisture measuring element (2) by way of a first measuring resistor (R1; RA) provides for ascertaining a first time constant or a first period duration of the charging and/or discharging operation, and charging and/or discharging of the moisture measuring element (2) by way of a second measuring resistor (R2; RA//R) provides for ascertaining a second one. The capacitance (C) of the moisture measuring element (2) is then calculated from the two time constants or the two period durations, a value for the moisture level finally being ascertained from the capacitance. This method achieves a higher level of measuring accuracy on the part of the moisture sensor.

A method for modeling a circuit includes receiving a netlist that defines a plurality of connections between a plurality of circuit elements and identifying a subset of the connections. The method also includes routing the identified connections with a first group of wires having a first wire width and routing at least a portion of the remaining connections with a second wire width. The second wire width is smaller than the first wire width. The method further includes replacing the first group of wires with a third group of wires having the second wire width.

Systems and methods for modeling a multilayer integrated circuit include three-dimensional interconnect models in multilayered substrates for greater accuracy. Mesh models are used to resolve effects of nearby elements and grid models are used to resolve effects of far-away elements. Sidewall mesh elements of three-dimensional interconnects are projected onto parallel (or substantially parallel) grids between the top and bottom walls of the interconnects so that grid models can be used to resolve three-dimensional effects of interconnects in multilayered substrates.

A method of designing a circuit can include modeling one or more circuits in a hardware design language (HDL) (102) and confirming a basic behavior of such models (104). If a basic behavior has been met, the model can be modified to include an algorithm that is based on an experimental statistical analysis of manufactured circuits representing particular condition (e.g., factor) limits (referred to as “corners”) (106). Once a circuit model has been modified to include an algorithm that can represent performance corners, a simulation can be run that will represent circuit response at such an operational corner (110).

The invention discloses a system for calculating crosstalk strength among cables based on a partial element equivalent circuit (PEEC) theory. The system comprises a computer and a parallel cable crosstalk module stored in the computer, wherein the parallel cable crosstalk module is redacted by applying VC++6.0 in the computer according to the PEEC theory. A parameter input and configuration unit acquires a cable configuration picture of cables and a metal plate according to configuration parameters; an SPICE circuit modeling unit carries out conversion process by adopting the PEEC theory to obtain an SPICE circuit; and an interference strength analysis unit obtains the crosstalk coupling interference strength of near-end equipment and far-end equipment of parallel cables according to an exciting source and a load which are loaded on the SPICE circuit. By adopting the PEEC theory to analyze the crosstalk among the cables, the invention can accurately and effectively calculate the coupling induction and the coupling capacitance between the cables and obtain the crosstalk strength between the cables.

The invention discloses a behavioral model-based electromagnetic compatibility circuit-level integrated modeling method for electronic equipment. The behavioral model-based electromagnetic compatibility circuit-level integrated modeling method comprises the following steps: firstly, performing equivalent circuit modeling of a front-end field structure of the electronic equipment; establishing a lumped element circuit model; then, performing behavioral model-based bottom layer physical circuit modeling; establishing a behavioral model for describing the input/output functional characteristics of a circuit; finally, performing integration on the lumped element circuit model and the behavioral model for describing the input/output functional characteristics of the circuit, and establishing an integrated circuit-level model of the electronic equipment, wherein the integrated circuit-level model is uniformly used for simulated analysis of a circuit level. According to the behavioral model-based electromagnetic compatibility circuit-level integrated modeling method disclosed by the invention, calculation is simplified, and a data interface for traditional field-circuit collaborative analysis is omitted, and the problem that a large number of product differential equations are difficult to solve due to high integration level of the circuit in a system and high complexity of digital-analog hybrid is solved; the behavioral model and the circuit model can also mutually compatible, so that the analysis efficiency is improved; the established integrated circuit model is high in universality; parameters of the model can be flexibly adjusted according to the performance of the electronic equipment; the behavioral model-based electromagnetic compatibility circuit-level integrated modeling method is simple, and is easy to implement.

The invention discloses a method for estimating the decoupling capacitors on a chip of an ASIC based on a chain circuit, and belongs to the field of estimation of the decoupling capacitors in inhibition of mains voltage fluctuation. The method comprises: firstly, adopting Star-RCXT to extract parasitic parameters of the ASIC after wiring, and using Perl to analyze the SPF file format and included information for the modeling of the chain circuit; secondly, using an Euler formula to realize the equivalence of the capacitors, and compressing the circuit by a Y-delta conversion method; thirdly, solving the voltage and the current of various nodes of a compressor circuit, and restoring the solving of the chain circuit; and fourthly, adopting integral idea to obtain the number of decoupling capacitors required to be added according to the principle that the voltage fluctuation of the nodes cannot exceed 10 percent of the mains voltage. The method estimates the number of the decoupling capacitors on a chip required to be added between power ground wires, makes the amplitude of mains fluctuation not exceed 10 percent of the mains voltage, and effectively solves the problem of voltage drop of a power network.

The invention relates to a conduction electromagnetic interference simulation system for an alternating-current motor inverter power circuit of an electric car. The system comprises a cable model simulation module, an inverter power circuit simulation module and a power circuit signal acquisition module. The system is mainly used for analyzing the electric car motor drive system conduction electromagnetic interference production mechanism and propagation path. A cable model simulation module is established under electromagnetic compatibility cable modeling and simulation software, an inverter power circuit simulation module is established under electromagnetic compatibility high-frequency circuit modeling and simulation software, and a power circuit control signal acquisition module is established under mathematical simulation software. During simulation, the power circuit control signal acquisition module inputs control signals to the inverter power circuit simulation module to control the operation of the inverter, and a voltage monitoring module and a current monitoring module of the inverter power circuit simulation module are used for acquiring the power circuit voltage and current.

The invention belongs to the technical field of intra-body communication, and particularly relates to an information interaction modeling method and device based on the current coupling type IBC. The method comprises the steps that firstly, circuit modeling is carried out on an information interaction channel based on the current coupling type IBC to form an overall circuit model; secondly, according to the obtained overall circuit model, circuit modeling is carried out on contact resistance caused by body contact; thirdly, by means of the overall circuit model, an information interaction complete circuit model based on the current coupling type IBC is formed; finally, based on the built complete circuit model, an information interaction mathematic model based on the current coupling type IBC is obtained through circuit analysis. Compared with the prior art, safety guarantee is provided for information interaction based on the current coupling type IBC, the system design basis is provided for the design of the information interaction device based on the current coupling type IBC, the problems of geometric modeling, circuit modeling and mathematic modeling between two living bodies and an electronic device are solved, and the reference is provided for relevant research and design.

The invention discloses a pulse laser ranging system transistor type receiving circuit error correcting method. The pulse laser ranging system transistor type receiving circuit error correcting methodcomprises the following steps that (10) a circuit modeling is received, wherein a circuit equation set is listed according to a circuit structure and a transistor classic model; (20) a circuit equation set is solved, wherein a numerical value approximation solution of the circuit equation set is solved by means of discretization and numerical analysis; (30) the circuit equation set is simplified,wherein the circuit equation set is reserved according to the numerical value approximation solution of the circuit equation set; (40) a linear differential equation set is solved, the linear differential equation set is solved to obtain an approximate relation between the walking error and the input current; (50) an error relation is determined, wherein a double-threshold moment is substituted into the approximate relation to obtain the relation between the walking error and the double-threshold moment; and (60) time error is corrected, wherein the specific numerical value of the double-threshold moment is substituted into the relation to obtain an error value, and the error value is subtracted from the time interval to obtain an accurate time interval. The error correcting method is small in error and high in system measuring precision.