116 results about "Stress profile" patented technology

A wound dressing apparatus includes a wound dressing member dimensioned for positioning relative to a wound bed. The wound dressing member including an internal vacuum reservoir and has a port in communication with the vacuum reservoir for applying subatmospheric pressure to the vacuum reservoir to facilitate removal of fluid from the wound bed. The wound dressing member includes a visual pressure indicator associated therewith for indicating a level of pressure within the vacuum reservoir. The visual pressure indicator includes color indicia having a plurality of colors corresponding to a condition of the pressure within the vacuum reservoir. The wound dressing member includes a lower absorbent member positionable adjacent the wound bed and an upper member which at least partially defines the vacuum reservoir. At least one of the top member and the lower absorbent member has the visual pressure indicator mounted thereto. The preferred visual pressure indicator includes an electronic position sensor. The visual pressure indicator further includes circuit means and visible alarm means. The circuit means is adapted to actuate the visible alarm means when the position sensor detects a relative positioning of the top member of the wound dressing member to provide a visual indication of the condition of the subatmospheric pressure within the vacuum reservoir.

An apparatus, systems and methods for improving strength of a thin glass member for an electronic device are disclosed. In one embodiment, the glass member can have improved strength characteristics in accordance with a predetermined stress profile. The predetermined stress profile can be formed through multiple stages of chemical strengthening. The stages can, for example, have a first ion exchange stage where larger ions are exchanged into the glass member, and a second ion exchange stage where some of the larger ions are exchanged out from the glass member. In one embodiment, the glass member can pertain to a glass cover for a housing for an electronic device. The glass cover can be provided over or integrated with a display.

The present invention relates to a semiconductor device comprising at least one n-channel field effect transistor (n-FET). Specifically, the n-FET comprises first and second patterned stressor layers that both contain a carbon-substituted and tensilely stressed single crystal semiconductor. The first patterned stressor layer has a first carbon concentration and is located in source and drain (S / D) extension regions of the n-FET at a first depth. The second patterned stressor layer has a second, higher carbon concentration and is located in S / D regions of the n-FET at a second, deeper depth. Such an n-FET with the first and second patterned stressor layers of different carbon concentration and different depths provide improved stress profile for enhancing electron mobility in the channel region of the n-FET.

A method is provided for producing a thin substrate with a thickness below 750 microns, comprising providing a mother substrate, the mother substrate having a first main surface and a toughness; inducing a stress with predetermined stress profile in at least a portion of the mother substrate, said portion comprising the thin substrate, the induced stress being locally larger than the toughness of the mother substrate at a first depth under the main surface; such that the thin substrate is released from the mother substrate, wherein the toughness of the mother substrate at the first depth is not lowered prior to inducing the stress. The method can be used in the production of, for example, solar cells.

A method and system is disclosed for automatically correcting for depth errors in measurements taken from a drill-string during the drilling phase of the construction of a hydrocarbon wellbore. The correction is based on a stress profile which in turn is based on the states of the drilling rig, drill string description length spec, borehole description trajectory, friction factor and weight on bit.