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Evaluation method for decoupling capacitor on ASIC sheet based on chain circuit

A technology of ASIC circuit and chain circuit, which is applied in the field of ASIC on-chip decoupling capacitor estimation, and can solve problems such as affecting the circuit and unstable power supply voltage

Active Publication Date: 2009-08-12
SOUTHEAST UNIV
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  • Application Information

AI Technical Summary

Problems solved by technology

When a circuit reverses and draws a certain amount of current from the power bus, it will cause a certain voltage drop on the power network bus, and this voltage drop will affect the circuits that share the power bus in the chip, making the power supply voltage unstable

Method used

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  • Evaluation method for decoupling capacitor on ASIC sheet based on chain circuit
  • Evaluation method for decoupling capacitor on ASIC sheet based on chain circuit
  • Evaluation method for decoupling capacitor on ASIC sheet based on chain circuit

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Embodiment Construction

[0050] Such as figure 1 Shown is the basic flow of the method of the present invention, and its implementation steps are described in detail below.

[0051] A method for estimating decoupling capacitance on an ASIC chip based on a chain circuit, comprising the steps of:

[0052] (1) if figure 2 The RC chain circuit model in the ASIC circuit shown

[0053] According to the characteristics of the ASIC circuit, the entire network is abstracted as a chain circuit, and its main parameter information includes: the connection relationship between component nodes, the resistance value R between nodes i , node capacitance C i And the equivalent current source of the component e i , where the constant current source simulates the charging and discharging process of the standard cell in the chip;

[0054] (2) SPF file extraction

[0055] Use the tool Star-RCXT to extract the parasitic parameter file of the circuit after wiring, that is, the SPF file. The command is: StarXtract-cle...

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Abstract

The invention discloses a method for estimating the decoupling capacitors on a chip of an ASIC based on a chain circuit, and belongs to the field of estimation of the decoupling capacitors in inhibition of mains voltage fluctuation. The method comprises: firstly, adopting Star-RCXT to extract parasitic parameters of the ASIC after wiring, and using Perl to analyze the SPF file format and included information for the modeling of the chain circuit; secondly, using an Euler formula to realize the equivalence of the capacitors, and compressing the circuit by a Y-delta conversion method; thirdly, solving the voltage and the current of various nodes of a compressor circuit, and restoring the solving of the chain circuit; and fourthly, adopting integral idea to obtain the number of decoupling capacitors required to be added according to the principle that the voltage fluctuation of the nodes cannot exceed 10 percent of the mains voltage. The method estimates the number of the decoupling capacitors on a chip required to be added between power ground wires, makes the amplitude of mains fluctuation not exceed 10 percent of the mains voltage, and effectively solves the problem of voltage drop of a power network.

Description

technical field [0001] The invention relates to a method for estimating decoupling capacitance on an ASIC chip based on a chain circuit in the technical field of suppressing power supply voltage fluctuations. Background technique [0002] Studies have shown that the power fluctuation amplitude of the power ground network cannot exceed 10% of the power supply voltage, otherwise it will cause the transmission delay and level of the data signal to be unpredictable, and the synchronous switching noise generated at the same time will bring electromagnetic interference to other signals and reduce the chip's performance. electromagnetic compatibility. [0003] Adding an on-chip decoupling capacitor between the power supply and ground can effectively solve this problem. When the circuit is turned over, it will first draw charge from the adjacent decoupling capacitor instead of the power bus. Charging in the power network, so it can suppress the fluctuation of power supply voltage a...

Claims

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Application Information

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IPC IPC(8): G06F17/50
CPCG06F2217/78G06F17/5063G06F30/36G06F2119/06
Inventor 刘新宁邵金梓杨军时龙兴
Owner SOUTHEAST UNIV
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