Semiconductor device

Abstract

A semiconductor device includes a lower circuit pattern, a bit line shielding structure, a first insulating interlayer, a bit line structure, a first contact plug, a channel, and a capacitor. The lower circuit pattern is on the substrate. A bit line shielding structure is on the lower circuit pattern. A first insulating interlayer is in an opening extending through the bit line shielding structure. The bit line structure is on the bit line shielding structure and at least partially overlaps the bit line shielding structure in a vertical direction substantially perpendicular to the upper surface of the substrate. A first contact plug extends through the first insulating interlayer to contact the bit line structure and is electrically connected to the lower circuit pattern. A channel is on the bit line structure. A capacitor is on and electrically connected to the channel.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0096317 filed in the Korean Intellectual Property Office on July 24, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Example embodiments of the present disclosure relate to a semiconductor device. More particularly, example embodiments of the present disclosure relate to a memory device including a vertical channel. Background Art

[0004] In order to improve the integration of semiconductor devices, a vertical channel memory device including a vertical channel transistor has been developed. In the vertical channel memory device, a bit line shield may be formed to surround the bit line. If the vertical channel memory device has a peripheral upper unit (COP) structure, a wiring structure for electrically connecting the bit line and the lower circuit pattern may be required. Therefore, an area for forming the wiring structure may be required, so that the integration of the vertical channel memory device may be reduced. Summary of the invention

[0005] Example embodiments provide a semiconductor device having improved characteristics.

[0006] According to an example embodiment, a semiconductor device is provided. The semiconductor device may include a lower circuit pattern, a bit line shielding structure, a first insulating interlayer, a bit line structure, a first contact plug, a channel, and a capacitor. The lower circuit pattern may be disposed on a substrate. The bit line shielding structure may be disposed on the lower circuit pattern and may include an opening extending through the bit line shielding structure. The first insulating interlayer may be disposed in the opening extending through the bit line shielding structure. The bit line structure may be disposed on the bit line shielding structure and at least partially overlap the bit line shielding structure in a vertical direction substantially perpendicular to the upper surface of the substrate. The first contact plug may extend through the first insulating interlayer to contact the bit line structure and may be electrically connected to the lower circuit pattern. The channel may be disposed on the bit line structure. The capacitor may be disposed on the channel to be electrically connected to the channel.

[0007] According to example embodiments, a semiconductor device is provided. The semiconductor device may include a bit line shielding structure, a first insulating interlayer, a bit line structure, a channel, and a capacitor. The bit line shielding structure may be disposed on a substrate, and may include a bit line shielding plate and a bit line shielding fin. The bit line shielding plate may have a planar surface extending in a first direction and a second direction substantially parallel to an upper surface of the substrate. The bit line shielding fins may be spaced apart from each other along a first direction on the bit line shielding plate. Each of the bit line shielding fins may protrude from the bit line shielding plate in a vertical direction substantially perpendicular to the upper surface of the substrate, and may extend in a second direction. The first direction and the second direction may intersect with each other. The bit line structure may be disposed on the bit line shielding plate between each pair of bit line shielding fins in the bit line shielding fins, and each of the bit line structures may extend in the second direction. Channels may be disposed on the bit line structures, respectively. Capacitors may be disposed on the channels, respectively, and electrically connected to the channels. The bit line shielding plate may include an opening passing through the bit line shielding plate, and each of the bit line structures may overlap at least one of the openings in a vertical direction.

[0008] According to example embodiments, a semiconductor device is provided. The semiconductor device may include a lower circuit pattern, a first bonding layer and a second bonding layer, a bit line shielding structure, an insulating interlayer, a bit line structure, a contact plug, a channel, and a capacitor. The lower circuit pattern may be disposed on a substrate. The first bonding layer and the second bonding layer may be stacked on the lower circuit pattern in a vertical direction substantially perpendicular to the upper surface of the substrate. The bit line shielding structure may be disposed on the second bonding layer and may include an opening extending through the bit line shielding structure. The insulating interlayer may be disposed between the second bonding layer and the bit line shielding structure. The insulating interlayer may extend on the surface of the bit line shielding structure and may include a portion located in the opening. The bit line structure may be disposed on the bit line shielding structure and may at least partially overlap with the bit line shielding structure in the vertical direction. The contact plug may extend through the portion of the first insulating interlayer located in the opening to contact the bit line structure and may be electrically connected to the lower circuit pattern. The channel may be disposed on the bit line structure. The capacitor may be disposed on the channel and electrically connected to the channel.

[0009] In a semiconductor device according to example embodiments, a bit line shielding structure adjacent to a bit line structure may include an opening passing through the bit line shielding structure, and the bit line structure may be electrically connected to a lower circuit pattern via a contact plug extending through the opening. Therefore, an additional wiring structure bypassing or surrounding the bit line shielding structure may not be formed, and thus the semiconductor device may have an enhanced degree of integration. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 , Figure 2 and Figure 3are plan views and cross-sectional views illustrating a semiconductor device according to example embodiments, and Figure 4 is a perspective view showing the shape of a bit line shielding structure.

[0011] Figure 5 , Figure 6 , Figure 7 , Figure 8 , Fig. 9 , Fig.10 , Fig.11 , Fig.12 , Fig.13 , Fig.14 , Fig.15 , Fig.16 , Fig.17 , Fig.18 , Fig.19 , Fig. 20 , Fig.21 , Fig. 22 , Fig.23 and Fig.24 are plan views and cross-sectional views illustrating a method of manufacturing a semiconductor device according to example embodiments.

[0012] Fig.25 and Fig.26 is a perspective view illustrating a bit line shielding structure included in a semiconductor device according to example embodiments. DETAILED DESCRIPTION

[0013] The above and other aspects and features of the semiconductor device and the method for manufacturing the semiconductor device according to the example embodiments will become easily understood from the detailed description below with reference to the accompanying drawings. When the terms "include", "comprise", "contain" and / or "cover" are used in this article, they specifically refer to the existence of the stated elements, but do not exclude the existence of additional elements. The term "and / or" includes any combination and all combinations of one or more of the relevant listed items. It will be understood that although the terms "first", "second" and / or "third" can be used in this article to describe various materials, layers (films), regions, electrodes, pads, patterns, structures and processes, these materials, layers (films), regions, electrodes, pads, patterns, structures and processes should not be limited by these terms. These terms are only used to distinguish one material, layer (film), region, electrode, pad, pattern, structure and process from another material, layer (film), region, electrode, pad, pattern, structure and process. Therefore, without departing from the teachings of the present inventive concept, the first material, layer (film), region, electrode, pad, pattern, structure and process discussed below may be named as the second or third material, layer (film), region, electrode, pad, pattern, structure and process.

[0014] Hereinafter, in the specification (not necessarily in the claims), two directions substantially perpendicular to each other in a horizontal direction substantially parallel to the upper surface of each of the first to third substrates may be referred to as a first direction D1 and a second direction D2, respectively, and a vertical direction substantially perpendicular to the upper surface of each of the first to third substrates may be referred to as a third direction D3. In example embodiments, the first direction D1 and the second direction D2 may be orthogonal to each other. Each of the first to third directions D1, D2, and D3 may represent not only a direction shown in the drawings, but also a direction opposite to the directions.

[0015] Figures 1 to 3 are plan views and cross-sectional views illustrating a semiconductor device according to example embodiments, and Figure 4 is a perspective view showing the shape of the bit line shielding structure. Specifically, Figure 1 It is a floor plan. Figure 2 is along Figure 1 A cross-sectional view taken along line AA', and Figure 3 is along Figure 1 A cross-sectional view taken along line BB'.

[0016] Reference Figures 1 to 4 The semiconductor device may include a lower circuit pattern, a bit line structure 430 , a bit line shielding structure 460 , first and second gate electrodes 140 and 160 , first and second gate insulating patterns 130 and 150 , a channel 125 , a landing pad 180 , and a capacitor 220 .

[0017] The semiconductor device may further include third and fourth bonding layers 490 and 730 , first and second bonding pads 510 and 750 that may be conductive, first to sixth insulating interlayers 170 , 230 , 480 , 650 , 660 , and 700 , and an insulating layer 450 .

[0018] The third substrate 600 may include a semiconductor material (eg, silicon, germanium, silicon germanium, etc.) or a II IV compound semiconductor (eg, GaP, GaAs, GaSb, etc.). In example embodiments, the third substrate 600 may be a silicon on insulator (SOI) substrate or a germanium on insulator (GOI) substrate.

[0019] In example embodiments, the third substrate 600 may include a cell array region in which memory cells are formed and a peripheral circuit region in which a peripheral circuit pattern is formed. The peripheral circuit region may surround the cell array region, and Figures 1 to 4 Only the cell array region of the third substrate 600 is shown.

[0020] The semiconductor device may have a cell-on-periphery (COP) structure in which a memory cell is formed on a lower circuit pattern.

[0021] The lower circuit pattern may be a circuit pattern of a bit line sense amplifier (BLSA), a sub word line driver (SWD), a column decoder, a column select line (CSL) driver, an input / output sense amplifier (I / O SA), a write driver, and the like. Figures 1 to 4 The circuit pattern of the BLSA is shown.

[0022] The lower circuit patterns 630 , 640 , 670 , 680 , 690 , 710 , 720 may include, for example, transistors, contact plugs, wirings, vias, and the like.

[0023] The transistor may include a gate structure 630 on a third substrate 600 and a source / drain layer or pattern 605 at an upper portion of the third substrate 600 and adjacent to the gate structure 630 .

[0024] The gate structure 630 may include a third gate insulating pattern 610 and a third gate electrode 620 sequentially stacked in the third direction D3. In example embodiments, the gate structure 630 may extend in the second direction D2, and a plurality of gate structures 630 may be spaced apart from each other in the first direction D1. A gate spacer may be formed on each of the opposite sidewalls or the opposite sidewalls of the gate structure 630.

[0025] The third gate insulating pattern 610 may include an oxide, such as silicon oxide, and the third gate electrode 620 may include a conductive material, such as a metal, a metal nitride, a metal silicide, doped polysilicon, or the like.

[0026] Each of the source / drain layers 605 may include n-type impurities (eg, phosphorus, arsenic, etc.) or p-type impurities (eg, boron, aluminum, etc.).

[0027] In example embodiments, transistors may be formed at locations corresponding to the above bit line structures 430 , respectively.

[0028] A fourth insulating interlayer 650 may be formed on the third substrate 600 and may cover the transistor. A second contact plug 640 may extend through the fourth insulating interlayer 650 and may contact an upper surface of a corresponding one of the source / drain layers 605 .

[0029] The fifth insulating interlayer 660 may be formed on the fourth insulating interlayer 650 and the second contact plug 640. The first wiring 670, the first via 680, and the second wiring 690 may be formed in the fifth insulating interlayer 660 and may be sequentially stacked in the third direction D3. The first wiring 670 may contact the upper surface of the second contact plug 640.

[0030] The sixth insulating interlayer 700 may be formed on the fifth insulating interlayer 660 and the second wiring 690. The second via 710 and the third wiring 720 may be formed in the sixth insulating interlayer 700 and may be sequentially stacked in the third direction D3. The second via 710 may contact the upper surface of the second wiring 690.

[0031] The fourth bonding layer 730 may be formed on the sixth insulating interlayer 700 and the third wiring 720. The third contact plug 740 and the second bonding pad 750 may be formed in the fourth bonding layer 730 and may be sequentially stacked in the third direction D3. The third contact plug 740 may contact the upper surface of the third wiring 720.

[0032] The third bonding layer 490 may be formed on the fourth bonding layer 730 and the second bonding pad 750. The third insulating interlayer 480 may be formed on the third bonding layer 490.

[0033] Each of the third to sixth insulating interlayers 480 , 650 , 660 , and 700 may include an oxide such as silicon oxide or a low-k dielectric material, and each of the bonding layers 490 and 730 may include an insulating material such as silicon carbonitride.

[0034] The second bonding pad 750 may include a metal, such as copper, aluminum, etc. Each of the second and third contact plugs 640 and 740, the first to third wirings 670, 690, and 720, and the first and second vias 680 and 710 may include a conductive material, such as a metal, a metal nitride, a metal silicide, doped polysilicon, etc.

[0035] The bit line shielding structure 460 may be formed on the third insulating interlayer 480. In an example embodiment, the bit line shielding structure 460 may include a bit line shielding plate 462 and a bit line shielding fin 464 that are sequentially stacked and in contact with each other along the third direction D3. In an example embodiment, the bit line shielding plate 462 may be a plane substantially parallel to the upper surface of the third substrate 600 (i.e., may be a planar element or may otherwise have a planar surface). The bit line shielding fin 464 may protrude from the bit line shielding plate 462 in the third direction D3 and may extend in the second direction D2. In an example embodiment, a plurality of bit line shielding fins 464 may be spaced apart from each other in the first direction D1.

[0036] Reference Figures 1 to 4 as well as Figures 17 to 19In example embodiments, the bit line shield plate 462 may include a first opening 470, and the first opening 470 may extend through the bit line shield plate 462 and the insulating layer 450 on the bit line shield plate 462 to expose the lower surface of the second conductive pattern 420 included in the bit line structure 430. The first opening 470 may be filled with a third insulating interlayer 480. The terms "surrounding" or "covering" or "filling" as may be used herein may not necessarily completely surround or cover or fill the described element or layer, but may, for example, refer to partially surrounding or covering or filling the described element or layer, for example, with a gap or other space in the entire element or layer.

[0037] In example embodiments, the plurality of first openings 470 may be spaced apart from each other in a fourth direction that may define an acute angle with respect to the first direction D1 and the second direction D2. Alternatively, the plurality of first openings 470 may be spaced apart from each other in each of the first direction D1 and the second direction D2 and may be arranged in a grid pattern in a plan view.

[0038] Each of the bit line shield plate 462 and the bit line shield fin 464 may include a conductive material, such as metal, metal nitride, metal silicide, doped polysilicon, or the like.

[0039] The insulating layer 450 may cover the upper surface of the bit line shield structure 460, ie, the upper surface of the bit line shield plate 462 and the upper surface and sidewalls of the bit line shield fin 464. The insulating layer 450 may include an oxide, such as silicon oxide.

[0040] The bit line structure 430 may be formed on the insulating layer 450 and may extend in the second direction D2. In example embodiments, the plurality of bit line structures 430 may be spaced apart from each other in the first direction D1. Each of the bit line structures 430 may be disposed between adjacent bit line shielding fins (i.e., adjacent pairs) in the bit line shielding fins 464 in the first direction D1, and the sidewalls of each of the bit line structures 430 may be covered by the insulating layer 450. When components are referred to herein as being "immediately adjacent" to each other, there may be no intermediate components of the same type.

[0041] In example embodiments, each of the bit line structures 430 may overlap in the third direction D3 with at least one of the first openings 470 in the bit line shielding plate 462. Components or layers described with reference to “overlapping” in a particular direction may at least partially block each other when viewed along a line extending in the particular direction or in a plane perpendicular to the particular direction.

[0042] In example embodiments, the bit line structure 430 may include a second conductive pattern 420, a barrier pattern 410, and a first conductive pattern 400 sequentially stacked along a third direction D3. The second conductive pattern 420 may include a metal and / or a metal nitride, the barrier pattern 410 may include a metal silicon nitride (e.g., titanium silicon nitride), and the first conductive pattern 400 may include, for example, doped polysilicon.

[0043] The first bonding pad 510 may extend through a lower portion of the third bonding layer 490 or may be exposed by a lower portion of the third bonding layer 490, and the first contact plug 500 may extend through the third bonding layer 490 and a portion of the third insulating interlayer 480 in the first opening 470 to contact an upper surface of the first bonding pad 510 and a lower surface of the second conductive pattern 420. In example embodiments, a plurality of first bonding pads 510 and a plurality of first contact plugs 500 may be arranged in a grid pattern along the fourth direction or along the first direction D1 and the second direction D2 in a plan view, which may correspond to the layout of the first opening 470.

[0044] The first bonding pad 510 may include a metal, such as copper, aluminum, etc. The first contact plug 500 may include a conductive material, such as a metal, a metal nitride, a metal silicide, doped polysilicon, etc.

[0045] Each of the first capping pattern 250 and the second capping pattern 255 may extend in the first direction D1 on the bit line structure 430 and the insulating layer 450. A plurality of first capping patterns 250 may be spaced apart from each other in the second direction D2, and a plurality of second capping patterns 255 may be spaced apart from each other in the second direction D2. In example embodiments, the first capping pattern 250 and the second capping pattern 255 may be alternately and repeatedly disposed in the second direction D2. Each of the first capping pattern 250 and the second capping pattern 255 may include an insulating nitride (e.g., silicon nitride) or an oxide (e.g., silicon oxide).

[0046] The first gate electrode 140 and the second gate electrode 160 may be formed on the first capping pattern 250 and the second capping pattern 255, respectively. Therefore, each of the first gate electrode 140 and the second gate electrode 160 may extend in the first direction D1, and a plurality of first gate electrodes 140 may be spaced apart from each other in the second direction D2, and a plurality of second gate electrodes 160 may be spaced apart from each other in the second direction D2. In example embodiments, the first gate electrodes 140 and the second gate electrodes 160 may be alternately and repeatedly disposed in the second direction D2.

[0047] In example embodiments, the first gate electrode 140 may have a straight line or linear shape extending in the first direction D1 in a plan view, and the second gate electrode 160 may include an extending portion extending in the first direction D1 and a protruding portion protruding in the second direction D2 from each of the opposing side walls or opposite side walls of the second gate electrode 160 in the second direction D2.

[0048] The first gate electrode 140 may include, for example, doped polysilicon, and the second gate electrode 160 may include, for example, metal, metal nitride, metal silicide, etc. In example embodiments, the second gate electrode 160 may serve as a word line of a semiconductor device, and the first gate electrode 140 may serve as a back gate electrode of the semiconductor device.

[0049] The first gate insulating pattern 130 may extend in the first direction D1 on the bit line structure 430 and the insulating layer 450, and may cover each of opposing sidewalls of each of the first gate electrode 140 and the first capping pattern 250 in the second direction D2. Thus, a plurality of first gate insulating patterns 130 may be spaced apart from each other in the second direction D2.

[0050] The second gate insulating pattern 150 may extend in the first direction D1 on the bit line structure 430 and the insulating layer 450, and may cover each of the opposing sidewalls in the second direction D2 of each of the second gate electrode 160 and the second capping pattern 255. Thus, a plurality of second gate insulating patterns 150 may be spaced apart from each other in the second direction D2.

[0051] In example embodiments, the first gate insulating pattern 130 may have a straight line or linear shape extending in the first direction D1, and the second gate insulating pattern 150 may extend in a zigzag or other non-linear pattern along the first direction D1. The sidewall of the second gate insulating pattern 150 may contact a portion of the sidewall of the first gate insulating pattern 130.

[0052] In example embodiments, each of the first gate insulating pattern 130 and the second gate insulating pattern 150 may include an oxide (e.g., silicon oxide) or an insulating nitride (e.g., silicon nitride). Alternatively, each of the first gate insulating pattern 130 and the second gate insulating pattern 150 may have a multi-layer structure including a first layer including an oxide (e.g., silicon oxide) and a second layer including an insulating nitride (e.g., silicon nitride).

[0053] The plurality of channels 125 may be spaced apart from each other in the first direction D1 and the second direction D2 on the bit line structures 430 and the insulating layer 450 . In example embodiments, the plurality of channels 125 may contact an upper surface of the first conductive pattern 400 included in each of the bit line structures 430 .

[0054] In example embodiments, a first sidewall of the channel 125 in the second direction D2 may contact the first gate insulating pattern 130 , and a second sidewall of the channel 125 in the second direction D2 and an opposite sidewall in the first direction D1 may contact the second gate insulating pattern 150 .

[0055] The channel 125 may include a semiconductor material such as silicon, germanium, silicon germanium, or the like.

[0056] A first insulating interlayer 170 may be formed on the first and second gate electrodes 140 and 160 and the first and second gate insulating patterns 130 and 150. The first insulating interlayer 170 may include an oxide, for example, silicon oxide, or a low-k dielectric material.

[0057] The landing pad 180 may extend through the first insulating interlayer 170 and may contact an upper surface of the channel 125 . Figure 2 and Figure 3 It is shown that the area of ​​the lower surface of the landing pad 180 is greater than the area of ​​the upper surface of the channel 125; however, the inventive concept may not be limited thereto. Figure 1 It is illustrated that the landing pad 180 has a rectangular shape in a plan view; however, the inventive concept may not be limited thereto, and the landing pad 180 may have a shape, for example, a circle, an ellipse, a polygon with rounded corners, etc. in a plan view.

[0058] The landing pad 180 may include, for example, metal, metal nitride, metal silicide, or the like.

[0059] The capacitor 220 may include a first capacitor electrode 190 , a dielectric layer 200 , and a second capacitor electrode 210 .

[0060] In example embodiments, the plurality of first capacitor electrodes 190 may be spaced apart from each other in the first direction D1 and the second direction D2 to respectively contact upper surfaces of corresponding landing pads 180 . Figure 1 The first capacitor electrode 190 is shown to have a rectangular shape in a plan view; however, the inventive concept may not be limited thereto, and the first capacitor electrode 190 may have a shape such as a circle, an ellipse, a polygon with rounded corners, etc. in a plan view. In addition, Figure 1 It is illustrated that the first capacitor electrodes 190 are arranged in a mesh pattern in a plan view, however, the inventive concept may not be limited thereto and may be arranged in, for example, a honeycomb pattern in a plan view.

[0061] The first capacitor electrode 190 may include, for example, metal, metal nitride, metal silicide, etc., the dielectric layer 200 may include, for example, metal oxide, and the second capacitor electrode 210 may include, for example, metal, metal nitride, metal silicide, doped silicon germanium, etc.

[0062] The second insulating interlayer 230 may be formed on the first insulating interlayer 170, and may cover the capacitor 220. The second insulating interlayer 230 may include an oxide, such as silicon oxide, or a low-k dielectric material.

[0063] In the semiconductor device, current may flow in the channel 125 along the third direction D3 (ie, in the vertical direction) between the bit line structure 430 and the landing pad 180 , and thus the semiconductor device may include a vertical channel transistor (VCT) having a vertical channel.

[0064] In the semiconductor device, the first opening 470 may be formed through the bit line shielding plate 462 and a portion of the insulating layer 450 covering the lower surface of the bit line structure 430 , and the first opening 470 may be filled with the third insulating interlayer 480 .

[0065] Thus, the bit line structure 430 can be electrically connected to the lower circuit pattern through the first contact plug 500, the first contact plug 500 can extend through the third insulating interlayer 480 in the first opening 470, and the first bonding pad 510, the second bonding pad 750 and the third contact plug 740 can be connected to the first contact plug 500. The term "connected" may be used herein to refer to physical connection and / or electrical connection. When a component or layer is referred to as being "directly on" or "directly connected", there is no intermediate component or layer.

[0066] If the bit line shielding structure 460 below the bit line structure 430 does not include the first opening 470, an additional wiring structure that bypasses or surrounds the bit line shielding structure 460 may be formed so that the bit line structure 430 can be electrically connected to the lower circuit pattern. Therefore, an additional area for forming the additional wiring structure may be required to accommodate the additional wiring structure, so that the integration of the semiconductor device may be deteriorated.

[0067] However, in example embodiments, the bit line shielding structure 460 may include a first opening 470 that serves as a path for electrically connecting the bit line structure 430 to the lower circuit pattern. Therefore, there may be no need to form an additional wiring structure that bypasses or surrounds the bit line shielding structure 460, so that the integration of the semiconductor device can be improved. That is, the first opening 470 may allow more direct wiring of the electrical connection between the bit line structure 430 and the lower circuit pattern below, thereby avoiding circuitous wiring of the electrical connection therebetween.

[0068] Figures 5 to 24 1 is a plan view and a cross-sectional view showing a method of manufacturing a semiconductor device according to an example embodiment. Specifically, Figure 5 , Figure 7 , Fig. 9 , Fig.11, Fig.15 , Fig.17 and Fig. 20 It is a floor plan. Figure 6 , Figure 8 , Fig.10 , Fig.12 , Fig.14 , Fig.18 , Fig.21 and Fig.23 are cross-sectional views taken along line AA' of the corresponding plan view, and Fig.13 , Fig.16 , Fig.19 , Fig. 22 and Fig.24 They are respectively cross-sectional views taken along line BB' of the corresponding plan view.

[0069] Reference Figure 5 and Figure 6 The second body of the first substrate structure including the first body 100, the buried oxide layer 110 and the second body can be patterned to form an initial channel 120, a first gate insulation pattern 130 can be formed on the sidewall of the initial channel 120, and a first gate electrode 140 can be formed between the first gate insulation patterns 130.

[0070] In example embodiments, the preliminary channels 120 may extend in the first direction D1, and a plurality of preliminary channels 120 may be spaced apart from each other in the second direction D2.

[0071] The first gate insulating pattern 130 may be formed by forming a first gate insulating layer on the preliminary channel 120 and the buried oxide layer 110 and anisotropically etching the first gate insulating layer. In example embodiments, the first gate insulating pattern 130 may be formed on each of opposite sidewalls of the preliminary channel 120 in the second direction D2 and may extend in the first direction D1.

[0072] The first gate electrode 140 may be formed by forming a first gate electrode layer on the preliminary channel 120 , the first gate insulating pattern 130 , and the buried oxide layer 110 , and performing a planarization process on the first gate electrode layer until an upper surface of the preliminary channel 120 is exposed.

[0073] The planarization process may include, for example, a chemical mechanical polishing (CMP) process and / or an etch-back process. During the planarization process, upper portions of the preliminary trench 120 and the first gate insulating pattern 130 may be partially removed.

[0074] In example embodiments, the first gate electrode 140 may extend in the first direction D1 between the first gate insulating patterns 130 , and a plurality of first gate electrodes 140 may be spaced apart from each other in the second direction D2 .

[0075] Reference Figure 7 and Figure 8 The preliminary channel 120 may be patterned to form a channel 125 , a second gate insulating pattern 150 may be formed on sidewalls of the channel 125 and the first gate insulating pattern 130 , and a second gate electrode 160 may be formed between the second gate insulating patterns 150 .

[0076] In example embodiments, the plurality of channels 125 may be spaced apart from each other along the first direction D1 on the sidewall of the first gate insulating pattern 130 extending along the first direction D1.

[0077] The second gate insulating pattern 150 may be formed by forming a second gate insulating layer on the channel 125 , the first gate insulating pattern 130 , the first gate electrode 140 , and the buried oxide layer 110 , and anisotropically etching the second gate insulating layer.

[0078] In example embodiments, the second gate insulating pattern 150 may be formed on sidewalls of each of the channel 125 and the first gate insulating pattern 130 in the second direction D2 and may extend in the first direction D1. In example embodiments, the second gate insulating pattern 150 may extend in a nonlinear (e.g., zigzag) pattern along the first direction D1 in a plan view.

[0079] The second gate electrode 160 may be formed by forming a second gate electrode layer on the channel 125 , the first and second gate insulating patterns 130 and 150 , and the buried oxide layer 110 , and performing a planarization process on the second gate electrode layer until an upper surface of the channel 125 is exposed.

[0080] The planarization process may include a CMP process and / or an etch-back process. During the planarization process, the trench 125 and upper portions of the first and second gate insulating patterns 130 and 150 may also be partially removed.

[0081] In example embodiments, the second gate electrode 160 may extend in the first direction D1 between the second gate insulating patterns 150, and a plurality of second gate electrodes 160 may be spaced apart from each other in the second direction D2. In example embodiments, the second gate electrode 160 may include an extending portion extending in the first direction D1 and a protruding portion protruding from each of opposite sidewalls in the second direction D2 in the second direction D2.

[0082] Reference Fig. 9 and Fig.10A first insulating interlayer 170 may be formed on the first and second gate electrodes 140 and 160 , the channel 125 , and the first and second gate insulating patterns 130 and 150 , and a landing pad 180 may be formed through the first insulating interlayer 170 to contact an upper surface of the channel 125 .

[0083] In example embodiments, the plurality of landing pads 180 may be spaced apart from each other in the first direction D1 and the second direction D2 and may contact upper surfaces of corresponding channels 125 , respectively.

[0084] Reference Figures 11 to 13 , a first capacitor electrode 190 can be formed on the first insulating interlayer 170 and the landing pad 180 to contact the upper surface of the landing pad 180, a dielectric layer 200 can be formed on the first capacitor electrode 190, the landing pad 180 and the first insulating interlayer 170, and a second capacitor electrode 210 can be formed on the dielectric layer 200.

[0085] In example embodiments, the plurality of first capacitor electrodes 190 may be spaced apart from each other in the first direction D1 and the second direction D2 and may contact upper surfaces of corresponding landing pads 180 , respectively.

[0086] The first capacitor electrode 190 , the dielectric layer 200 , and the second capacitor electrode 210 may collectively form a capacitor 220 .

[0087] Reference Figures 14 to 16 , a second insulating interlayer 230 may be formed on the first insulating interlayer 170 to cover the capacitor 220 , and a first bonding layer 240 may be formed on the second insulating interlayer 230 .

[0088] In addition, a second bonding layer 310 may be formed on the second substrate 300 , the second substrate 300 may be inverted or flipped, and the second bonding layer 310 and the first bonding layer 240 may be brought into contact with each other so that the first substrate structure and the second substrate 300 may be bonded to each other.

[0089] The first substrate structure and the second substrate 300 bonded to each other may be inverted or flipped, and the first body 100 and the buried oxide layer 110 included in the first substrate structure may be removed so that the upper surfaces of the first gate electrode 140 and the second gate electrode 160, the channel 125, and the first gate insulation pattern 130 and the second gate insulation pattern 150 may be exposed.

[0090] Upper portions of the first and second gate electrodes 140 and 160 may be removed to form first and second recesses, respectively, and first and second capping patterns 250 and 255 may be formed in the first and second recesses, respectively.

[0091] A first conductive layer, a barrier layer, and a second conductive layer may be sequentially stacked on the first capping pattern 250 and the second capping pattern 255, the channel 125, and the first gate insulation pattern 130 and the second gate insulation pattern 150, and the first conductive layer, the barrier layer, and the second conductive layer may be partially removed by an etching process to form a first conductive pattern 400, a barrier pattern 410, and a second conductive pattern 420, respectively, and the first conductive pattern 400, the barrier pattern 410, and the second conductive pattern 420 may together form a bit line structure 430.

[0092] In example embodiments, the bit line structure 430 may extend in the second direction D2 , and a plurality of the bit line structures 430 may be spaced apart from each other in the first direction D1 .

[0093] During the etching process, the channel 125 and upper portions of the first and second gate insulation patterns 130 and 150 may also be partially removed to form a third recess 440 between the bit line structures 430 that exposes the upper surface of the channel 125 and the upper surfaces of the first and second gate insulation patterns 130 and 150 .

[0094] Reference Figures 17 to 19 An insulating layer 450 may be formed on the bit line structure 430 , the first and second capping patterns 250 and 255 , the channel 125 , and the first and second gate insulating patterns 130 and 150 , and a bit line shielding structure 460 may be formed on the insulating layer 450 to fill the third recess 440 .

[0095] The bit line shield structure 460 may have an upper surface that is higher (relative to the substrate 300 ) than an uppermost surface of the insulating layer 450 .

[0096] With respect to the substrate 300, the bit line shielding structure 460 may include a bit line shielding plate 462 higher than the upper surface of the bit line structure 430, and a bit line shielding fin 464 lower than the upper surface of the bit line structure 430. In example embodiments, the bit line shielding plate 462 may be a plane, and the bit line shielding fin 464 may extend in the second direction D2. In example embodiments, a plurality of bit line shielding fins 464 may be spaced apart from each other in the first direction D1.

[0097] The bit line shielding plate 462 included in the bit line shielding structure 460 and the insulating layer 450 under the bit line shielding plate 462 may be partially removed to form a first opening 470 exposing an upper surface of the second conductive pattern 420 included in the bit line structure 430 .

[0098] In example embodiments, the plurality of first openings 470 may be spaced apart from each other in the fourth direction, and the fourth direction may define an acute angle with respect to the first direction D1 and the second direction D2; however, the present inventive concept may not be limited thereto.

[0099] Reference Figure 20 to Figure 22 A third insulating interlayer 480 can be formed on the bit line structure 430 and the bit line shielding structure 460 to fill the first opening 470, a third bonding layer 490 can be formed on the third insulating interlayer 480, and a first contact plug 500 and a first bonding pad 510 can be formed, the first contact plug 500 extends through the lower portion of the third bonding layer 490 and the third insulating interlayer 480 to contact the upper surface of the second conductive pattern 420 included in the bit line structure 430, and the first bonding pad 510 extends through the upper portion of the third bonding layer 490 to contact the upper surface of the first contact plug 500 (relative to the substrate 300).

[0100] In example embodiments, a plurality of first contact plugs 500 may be spaced apart from one another in a fourth direction (as described above, the fourth direction may define an acute angle relative to the first direction D1 and the second direction D2), and a plurality of first bonding pads 510 may be spaced apart from one another in the fourth direction, which may correspond to the first openings 470.

[0101] Reference Fig.23 and Fig.24 , a transistor may be formed on the third substrate 600 , a fourth insulating interlayer 650 may be formed on the third substrate 600 to cover the transistor, and a second contact plug 640 may be formed to pass through the fourth insulating interlayer 650 .

[0102] The transistor may include a gate structure 630 on a third substrate 600 and source / drain layers 605 at upper portions of the third substrate 600 adjacent to the gate structure 630, respectively. The gate structure 630 may include a third gate insulating pattern 610 and a third gate electrode 620 sequentially stacked.

[0103] A fifth insulating interlayer 660 , a first wiring 670 , a first via 680 , and a second wiring 690 may be formed on the fourth insulating interlayer 650 and the second contact plug 640 .

[0104] A sixth insulating interlayer 700 , a second via 710 , and a third wiring 720 may be formed on the fifth insulating interlayer 660 and the second wiring 690 .

[0105] A fourth bonding layer 730 , a third contact plug 740 , and a second bonding pad 750 may be formed on the sixth insulating interlayer 700 and the third wiring 720 .

[0106] Reference Figures 1 to 4 , the third substrate 600 may be inverted or flipped, and the third bonding layer 490 and the fourth bonding layer 730 may be brought into contact with each other, so that the third substrate 600 may be bonded to the first substrate structure and the second substrate 300 .

[0107] In example embodiments, with respect to the substrate 600 , a lower surface of the second bonding pad 750 in the fourth bonding layer 730 may contact an upper surface of the first bonding pad 510 in the third bonding layer 490 .

[0108] The first substrate structure and the second and third substrates 300 and 600 bonded to each other may be reversed or turned over, and the second substrate 300 and the first and second bonding layers 240 and 310 may be removed to complete the manufacture of the semiconductor device.

[0109] Fig.25 and Fig.26 is a perspective view showing a bit line shielding structure included in a semiconductor device according to example embodiments, which may be Figure 4 Corresponding.

[0110] Reference Fig.25 The bit line shield plate 462 included in the bit line shield structure 460 may include a second opening 472 (eg, a linear opening) extending through the bit line shield plate 462 .

[0111] In example embodiments, the second opening 472 may extend in a fourth direction having an acute angle with respect to the first direction D1 and the second direction D2. Thus, the bit line structure 430 may be electrically connected to the lower circuit pattern through the first contact plug 500, and the first and second bonding pads 510 and 750 connected to the first contact plug 500, and the third contact plug 740, which extends through a portion of the third insulating interlayer 480 in the second opening 472.

[0112] Reference Fig.26 The bit line shield plate 462 included in the bit line shield structure 460 may include a third opening 474 (eg, a rectangular opening) extending through the bit line shield plate 462 .

[0113] In example embodiments, the third openings 474 may extend in the second direction D2 , and a plurality of third openings 474 may be spaced apart from each other in the first direction D1 .

[0114] It will be understood that, unless otherwise indicated, spatially relative terms (such as "on," "above," "above," "below," "below," "side," etc.) may be expressed relative to a reference frame (e.g., a substrate) shown in the drawings. It will be understood that such spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the drawings. For example, if the device in the drawings is flipped, an element described as being "below" or "beneath" other elements or features will then be oriented "above" the other elements or features. Thus, the term "below" may encompass both the orientations of above and below. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

[0115] The foregoing is an illustration of example embodiments and is not to be construed as limiting thereof. Although some example embodiments have been described, it will be readily appreciated by those skilled in the art that many modifications may be made in the example embodiments without substantially departing from the teachings and advantages of the inventive concept. Therefore, all such modifications are intended to be included within the scope of the inventive concept as defined in the claims. In the claims, means-plus-function items are intended to cover structures described herein as performing the functions, and include not only structural equivalents, but also equivalent structures. Therefore, it is to be understood that the foregoing is an illustration of the various example embodiments and is not to be construed as being limited to the specific example embodiments disclosed, and modifications to the disclosed example embodiments and other example embodiments are intended to be included within the scope of the appended claims.

Claims

1. A semiconductor device comprising: a lower circuit pattern, which is on the substrate; a bit line shielding structure on the lower circuit pattern, the bit line shielding structure comprising an opening extending through the bit line shielding structure; a first insulating interlayer in the opening extending through the bit line shielding structure; a bit line structure on the bit line shielding structure, the bit line structure at least partially overlapping the bit line shielding structure in a vertical direction substantially perpendicular to an upper surface of the substrate; a first contact plug extending through the first insulating interlayer to contact the bit line structure, the first contact plug being electrically connected to the lower circuit pattern; a channel on the bit line structure; as well as A capacitor is on the channel, wherein the capacitor is electrically connected to the channel.

2. The semiconductor device according to claim 1, further comprising a plurality of bit line structures, wherein The bit line structure is included in the plurality of bit line structures, Wherein, the multiple bit line structures are spaced apart along a first direction substantially parallel to the upper surface of the substrate, and each of the multiple bit line structures extends in a second direction on the bit line shielding structure, wherein the second direction is substantially parallel to the upper surface of the substrate and substantially perpendicular to the first direction.

3. The semiconductor device according to claim 2, further comprising a plurality of openings in the bit line shielding structure, wherein: the opening is included in the plurality of openings, The plurality of openings are spaced apart from one another in a third direction substantially parallel to the upper surface of the substrate, and the third direction defines an acute angle with respect to the first direction and the second direction.

4. The semiconductor device according to claim 2, wherein: The opening extends in a third direction substantially parallel to an upper surface of the substrate, the third direction defining an acute angle with respect to the first direction and the second direction.

5. The semiconductor device according to claim 2, further comprising a plurality of openings in the bit line shielding structure and spaced apart from each other in the first direction, wherein the opening is included in the plurality of openings, Wherein, each of the plurality of openings extends in the second direction.

6. The semiconductor device according to claim 1, wherein The bit line shielding structure comprises: a bit line shield plate having a planar surface extending in a first direction and a second direction substantially parallel to an upper surface of the substrate; and Bit line shielding fins are provided on the bit line shielding plate, each of the bit line shielding fins protruding in the vertical direction and extending in the second direction, wherein the bit line shielding fins are spaced apart from each other in the first direction.

7. The semiconductor device according to claim 6, wherein: The bit line structure is on the bit line shield plate between immediately adjacent ones of the bit line shield fins.

8. The semiconductor device according to claim 1, further comprising: a second insulating interlayer on the substrate between the first insulating interlayer and the lower circuit pattern; a first bonding layer on the second insulating intermediate layer; as well as a second bonding layer on the first bonding layer, wherein the first insulating intermediate layer is on the second bonding layer and extends on a surface of the bit line shielding structure facing the second bonding layer, and Wherein, the first contact plug partially extends through the second bonding layer.

9. The semiconductor device according to claim 8, further comprising: a first conductive bonding pad in the second bonding layer, the first conductive bonding pad contacting a surface of the first contact plug; a second contact plug in the first bonding layer, the second contact plug contacting the lower circuit pattern; as well as A second conductive bonding pad is in the first bonding layer, the second conductive bonding pad contacts a surface of the second contact plug and a surface of the first conductive bonding pad.

10. The semiconductor device according to claim 9, wherein: Each of the first bonding layer and the second bonding layer includes silicon carbon nitride, and each of the first conductive bonding pad and the second conductive bonding pad includes copper.

11. A semiconductor device comprising: A bit line shielding structure, which is on a substrate, The bit line shielding structure comprises: a bit line shield plate having a planar surface extending in a first direction and a second direction substantially parallel to an upper surface of the substrate; and bit line shielding fins spaced apart from each other along the first direction on the bit line shielding plate, each of the bit line shielding fins protruding from the bit line shielding plate in a vertical direction substantially perpendicular to the upper surface of the substrate and extending in the second direction, the first direction and the second direction intersecting each other; a bitline structure on the bitline shielding plate between pairs of the bitline shielding fins, each of the bitline structures extending in the second direction; channels, which are respectively on the bit line structures; and capacitors, each on the channel and electrically connected to the channel, The bit line shielding plate includes an opening passing through the bit line shielding plate, and each of the bit line structures overlaps with at least one of the openings in the vertical direction.

12. The semiconductor device according to claim 11, wherein The openings are spaced apart from each other in a third direction substantially parallel to an upper surface of the substrate, the third direction defining an acute angle with respect to the first direction and the second direction.

13. The semiconductor device according to claim 11, wherein Each of the openings extends in a third direction substantially parallel to an upper surface of the substrate, the third direction defining an acute angle with respect to the first direction and the second direction.

14. The semiconductor device according to claim 11, wherein The openings are spaced apart from each other in the first direction, and each of the openings extends in the second direction.

15. The semiconductor device according to claim 11, further comprising: an insulating interlayer in the opening extending through the bit line shield; as well as Contact plugs extend through the insulating interlayer to contact surfaces of the bit line structures, respectively.

16. The semiconductor device according to claim 15, further comprising: The lower circuit pattern, which is on the substrate, Wherein, the contact plug is electrically connected to the lower circuit pattern.

17. A semiconductor device comprising: a lower circuit pattern, which is on the substrate; a first bonding layer and a second bonding layer, the first bonding layer and the second bonding layer being stacked on the lower circuit pattern along a vertical direction substantially perpendicular to an upper surface of the substrate; a bit line shielding structure on the second bonding layer, the bit line shielding structure comprising an opening extending through the bit line shielding structure; an insulating interlayer between the second bonding layer and the bit line shielding structure, wherein the insulating interlayer is on a surface of the bit line shielding structure and includes a portion in the opening; a bit line structure on the bit line shielding structure, the bit line structure at least partially overlapping the bit line shielding structure in the vertical direction; a contact plug extending through the portion of the insulating interlayer in the opening to contact the bit line structure, the contact plug being electrically connected to the lower circuit pattern; a channel on the bit line structure; and A capacitor is on the channel, the capacitor being electrically connected to the channel.

18. The semiconductor device according to claim 17, further comprising a plurality of bit line structures, wherein The bit line structure is included in the plurality of bit line structures, The plurality of bit line structures are spaced apart along a first direction substantially parallel to the upper surface of the substrate, and each of the plurality of bit line structures extends on the bit line shielding structure in a second direction substantially parallel to the upper surface of the substrate and substantially perpendicular to the first direction.

19. The semiconductor device of claim 18, further comprising a plurality of openings in the bit line shielding structure, wherein: the opening is included in the plurality of openings, The plurality of openings are spaced apart from one another in a third direction substantially parallel to the upper surface of the substrate, and the third direction defines an acute angle with respect to the first direction and the second direction.

20. The semiconductor device according to claim 18, wherein The bit line shielding structure comprises: a bit line shield plate having a planar surface extending in the first direction and the second direction substantially parallel to an upper surface of the substrate; and Bit line shielding fins are provided on the bit line shielding plate, each of the bit line shielding fins protruding in the vertical direction, wherein the bit line shielding fins are spaced apart from each other in the first direction.

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