Semiconductor structure and manufacturing method thereof

Abstract

The invention relates to a semiconductor structure and a manufacturing method thereof. The semiconductor structure comprises a substrate; the memory unit is arranged on the substrate, the memory unit comprises a transistor and a capacitor, the transistor comprises a first source / drain electrode, a grid electrode, a second source / drain electrode and a semiconductor layer surrounding the side wall of the grid electrode, the first source / drain electrode, the second source / drain electrode and the semiconductor layer are sequentially arranged in the first direction, and the first source / drain electrode and the second source / drain electrode are connected with the grid electrode through the semiconductor layer; the capacitor is arranged on one side of the second source / drain electrode and covers part of the side surface of the semiconductor layer; the bit line is arranged on one side of the first source / drain electrode and covers part of the side face of the semiconductor layer, the contact area of the bit line and the semiconductor layer is smaller than the contact area of the capacitor and the semiconductor layer, the contact area of the bit line and the transistor is reduced, and the opposite area of the bit line and the grid electrode of the transistor is reduced; therefore, the parasitic capacitance between the bit line and the grid electrode of the transistor is reduced, and the reading capability of the transistor is improved.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and in particular to a semiconductor structure and a manufacturing method thereof. Background Art

[0002] Semiconductor memory is usually a planar structure. At present, the size of planar semiconductor memory has been reduced to the limit, and it is difficult to continue to shrink to maintain the effectiveness of Moore's Law. Semiconductor memory has begun to develop from a planar structure to a three-dimensional structure.

[0003] The memory cell of the three-dimensional planar ring-channel transistor is one of the main development directions of the three-dimensional semiconductor memory. However, the distance between the gate and the bit line of the planar ring-channel transistor is very close, and the parasitic capacitance between the gate and the bit line of the transistor is large, which will not only cause signal crosstalk during the device read and write operations, but also increase the capacitance load on the word line, making it more difficult to read the signal. Summary of the invention

[0004] Based on this, it is necessary to provide a semiconductor structure and a manufacturing method thereof to address the problem of large parasitic capacitance between the gate and the drain of a transistor in the prior art.

[0005] In order to achieve the above object, in a first aspect, the present invention provides a semiconductor structure, comprising:

[0006] substrate;

[0007] At least one memory cell, the memory cell is arranged on the substrate, each of the memory cells comprises a transistor and a capacitor, the transistor comprises a first source / drain, a gate, a second source / drain arranged in sequence along a first direction, and a semiconductor layer surrounding and covering a side wall of the gate, the first source / drain and the second source / drain are connected to the gate through the semiconductor layer, the first direction is parallel to the top surface of the substrate, the capacitor is arranged on one side of the second source / drain, and the lower electrode of the capacitor covers a part of the side surface of the semiconductor layer;

[0008] At least one bit line is disposed on one side of the first source / drain, the bit line covers a portion of a side surface of the semiconductor layer, and a contact area between the bit line and the semiconductor layer is smaller than a contact area between the capacitor and the semiconductor layer.

[0009] In one embodiment, in a second direction perpendicular to the first direction and parallel to the substrate, the semiconductor layer has a first maximum length, and the contact surface between the bit line and the semiconductor layer has a second maximum length, and the second maximum length is less than half of the first maximum length.

[0010] In one embodiment, the bit line includes a first conductive layer, the first conductive layer covers a portion of a sidewall of the semiconductor layer away from the capacitor, and the first source / drain is disposed in the first conductive layer.

[0011] In one embodiment, the first conductive layer includes a first extension portion and at least one second extension portion, the first extension portion extends along the second direction, the second extension portions are spaced apart along the second direction on a side of the first extension portion close to the transistor, the second extension portions and the transistors are arranged one-to-one and cover a portion of the side wall of the semiconductor layer away from the capacitor, and the first source / drain is arranged in the second extension portion.

[0012] In one embodiment, the semiconductor structure further comprises:

[0013] a second conductive layer, the second conductive layer extending along the first direction on one side of the second source / drain electrode, the second conductive layer covering a portion of a side wall of the semiconductor layer, and the second source / drain electrode being arranged in the second conductive layer;

[0014] The capacitor uses the second conductive layer as the lower electrode.

[0015] In one embodiment, the transistor further comprises:

[0016] A gate dielectric layer surrounds the sidewall of the gate and is disposed between the gate and the semiconductor layer.

[0017] In one of the embodiments, at least one of the memory cells is arranged in an array on the substrate along the first direction, and / or the second direction, and / or the third direction, and the first direction, the second direction, and the third direction are perpendicular to each other; and the semiconductor structure further includes:

[0018] At least one word line is vertically arranged on the substrate along the third direction, and each of the word lines is connected to the gates of a column of the transistors arranged along the third direction.

[0019] In a second aspect, the present invention provides a method for manufacturing a semiconductor structure, comprising the following steps:

[0020] Providing a substrate, forming a stacked structure on the substrate, the stacked structure comprising a first dielectric layer and a conductive material layer alternately stacked on the substrate, and the stacked structure defines an isolation region;

[0021] The stacked structure of the isolation region is removed, an isolation trench is formed in the isolation region, and the conductive material layers retained in each layer form an initial conductive layer;

[0022] Filling a second dielectric layer in the isolation trench;

[0023] Etching and removing a portion of the second dielectric layer and a portion of the stacked structure to form a trench penetrating the stacked structure, wherein the trench divides the initial conductive layer into a first conductive layer and a second conductive layer that are independently arranged, wherein the first conductive layer and the second conductive layer are arranged on opposite sides of the trench along a first direction, and an area of ​​the first conductive layer exposed by the trench is smaller than an area of ​​the second conductive layer exposed by the trench, wherein the first conductive layer is a bit line;

[0024] forming a semiconductor layer, wherein the semiconductor layer covers a groove wall of the trench, and a contact area between the first conductive layer and the semiconductor layer is smaller than a contact area between the second conductive layer and the semiconductor layer;

[0025] A gate is formed, the gate covering the semiconductor layer and filling the channel.

[0026] In one embodiment, along a second direction perpendicular to the first direction, the semiconductor layer has a first maximum length, and a contact surface between the first conductive layer and the semiconductor layer has a second maximum length, and the second maximum length is less than half of the first maximum length.

[0027] In one embodiment, the initial conductive layer includes a first initial conductive layer and a second initial conductive layer, the second initial conductive layer extends along the first direction, the first initial conductive layer is arranged on one side of the second initial conductive layer, the first initial conductive layer extends along the second direction, and along the first direction, the first initial conductive layer and the second initial conductive layer are separated and arranged; forming a channel groove running through the stacked structure, including:

[0028] Etching and removing a portion of the first initial conductive layer, a portion of the second initial conductive layer, a portion of the first dielectric layer, and the second dielectric layer located between the first initial conductive layer and the second initial conductive layer to form the trench, etching the retained first initial conductive layer to form the first conductive layer, and etching the retained second initial conductive layer to form the second conductive layer;

[0029] An overlapping area of ​​a projection of the trench on the substrate and a projection of the first initial conductive layer on the substrate is smaller than an overlapping area of ​​a projection of the trench on the substrate and a projection of the second initial conductive layer on the substrate.

[0030] In one embodiment, the initial conductive layer includes a first portion extending along the first direction, a second portion disposed on one side of the first portion, and a third portion connecting the first portion and the second portion, wherein the second portion extends along the second direction, the third portion is disposed between the first portion and the second portion, and along the second direction, the size of the third portion is smaller than that of the first portion; forming a channel groove penetrating the stacked structure, including:

[0031] Part of the first part, part of the third part, part of the first dielectric layer and part of the second dielectric layer are etched away to form the channel groove, the first part retained by etching is formed into the first conductive layer, and the second part and the third part retained by etching are formed into the second conductive layer.

[0032] In one embodiment, before forming the gate, the method further includes:

[0033] A gate dielectric layer is formed, wherein the gate dielectric layer covers the semiconductor layer, and the gate electrode and the semiconductor layer are separated by the gate dielectric layer.

[0034] In one embodiment, the method for manufacturing the semiconductor structure further includes:

[0035] The second conductive layer is used as a lower electrode, and a capacitor is formed on one side of the second conductive layer.

[0036] In one embodiment, forming a capacitor on one side of the second conductive layer includes:

[0037] removing a portion of the dielectric layer to expose the sidewall of the second conductive layer;

[0038] forming a high-K dielectric layer, wherein the high-K dielectric layer covers the sidewalls of the second conductive layer;

[0039] An upper electrode is formed, wherein the upper electrode covers the high-K dielectric layer, and the second conductive layer, the high-K dielectric layer and the upper electrode form the capacitor.

[0040] The semiconductor structure and the manufacturing method thereof of the present invention have the following beneficial effects:

[0041] In the semiconductor structure of the present invention, the contact area between the bit line and the semiconductor layer is smaller than the contact area between the capacitor and the semiconductor layer, thereby reducing the contact area between the bit line and the transistor, and reducing the facing area between the bit line and the gate of the transistor, thereby reducing the parasitic capacitance between the bit line and the gate of the transistor, and improving the reading capability of the transistor;

[0042] In the method for manufacturing a semiconductor structure of the present invention, when forming a channel groove, the center line of the channel groove is biased toward the second conductive layer, so that the area of ​​the first conductive layer exposed by the channel groove is smaller than the area of ​​the second conductive layer exposed by the channel groove. After the transistor is formed, the contact area between the first conductive layer (i.e., the bit line) and the semiconductor layer of the transistor is smaller than the contact area between the second conductive layer and the semiconductor layer, thereby reducing the facing area between the bit line and the gate of the transistor, reducing the parasitic capacitance between the bit line and the gate, and thus improving the reading capability of the transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0044] Figure 1 A projection diagram of a semiconductor structure formed on a substrate is provided in an exemplary embodiment.

[0045] Figure 2 A projection diagram of a semiconductor structure formed on a substrate is provided in an exemplary embodiment.

[0046] Figure 3 A projection diagram of a semiconductor structure formed on a substrate is provided in an exemplary embodiment.

[0047] Figure 4 A schematic diagram of a semiconductor structure is provided in an exemplary embodiment.

[0048] Figure 5 FIG. 2 is a cross-sectional view of an AA cross section of a semiconductor structure provided in an exemplary embodiment.

[0049] Figure 6 A schematic diagram of a semiconductor structure is provided in an exemplary embodiment.

[0050] Figure 7 A flow chart of a method for manufacturing a semiconductor structure is provided in an exemplary embodiment.

[0051] Figure 8 FIG. 4 is a schematic diagram of a structure after a stacked structure is formed on a substrate in an exemplary embodiment.

[0052] Fig. 9 FIG. 4 is a projection diagram of an initial conductive layer formed on a substrate in an exemplary embodiment.

[0053] Fig.10FIG. 1 is a projection diagram of an initial conductive layer formed on a substrate after forming a second dielectric layer in an exemplary embodiment.

[0054] Fig.11 FIG. 1 is a projection diagram formed on a substrate after a trench is formed in an exemplary embodiment.

[0055] Fig.12 FIG. 1 is a projection diagram formed on a substrate after forming a transistor in an exemplary embodiment.

[0056] Fig.13 FIG. 4 is a projection diagram formed on a substrate after forming a first trench in an exemplary embodiment.

[0057] Fig.14 FIG. 4 is a projection diagram of an initial conductive layer formed on a substrate in an exemplary embodiment.

[0058] Fig.15 FIG. 1 is a projection diagram of an initial conductive layer formed on a substrate after forming a second dielectric layer in an exemplary embodiment.

[0059] Fig.16 FIG. 1 is a projection diagram formed on a substrate after a trench is formed in an exemplary embodiment.

[0060] Fig.17 FIG. 1 is a projection diagram formed on a substrate after forming a transistor in an exemplary embodiment.

[0061] Description of reference numerals:

[0062] 10. substrate; 100. transistor; 110. first source / drain; 120. second source / drain; 130. gate; 140. semiconductor layer; 150. gate dielectric layer; 200. capacitor; 20. memory cell; 210. lower electrode; 220. high-K dielectric layer; 230. upper electrode; 30. bit line; 310. first conductive layer; 311. first extension; 312. second extension; 320. second conductive layer; 40. word line; 50. stacked structure; 51. first dielectric layer; 52. conductive material layer; 53. second dielectric layer; 54. first trench; 70. initial conductive layer; 71. first initial conductive layer; 72. second initial conductive layer; 701. first portion; 702. second portion; 703. third portion; 80. channel groove; 90. isolation trench;

[0063] D1, first direction; D2, second direction; D3, third direction; L1, first maximum length; L2, second maximum length. DETAILED DESCRIPTION

[0064] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0065] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0066] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to or coupled to other elements or layers, it may be directly on, adjacent to, connected to or coupled to other elements or layers, or there may be intervening elements or layers. On the contrary, when an element is referred to as being "directly on, directly adjacent to, directly connected to or directly coupled to other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or portion discussed below may be represented as a second element, component, region, layer or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0067] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0068] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "consisting of" and / or "comprising" are used in this specification, the presence of the features, integers, steps, operations, elements and / or parts can be determined, but the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups is not excluded. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0069] Embodiments of the invention are described herein with reference to cross-sectional views which are schematic diagrams of ideal embodiments (and intermediate structures) of the invention, such that variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances are anticipated. Thus, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but rather include deviations in shapes due to, for example, manufacturing techniques. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Thus, the regions shown in the figures are schematic in nature, their shapes do not represent the actual shape of the region of the device, and do not limit the scope of the invention.

[0070] An embodiment of the present invention provides a semiconductor structure and a method for manufacturing the same, which reduces the contact area between the bit line and the transistor and the facing area between the bit line and the gate of the transistor, thereby reducing the parasitic capacitance between the bit line and the gate of the transistor and improving the reading capability of the transistor.

[0071] According to an exemplary embodiment, this embodiment provides a semiconductor structure, referring to Figure 1 , Figure 2 , Figure 3 , Figure 4 , Figure 5 As shown, the semiconductor structure includes a substrate 10, at least one memory cell 20 and at least one bit line 30. At least one memory cell 20 is disposed on the substrate 10, each memory cell 20 includes a transistor 100 and a capacitor 200, the transistor 100 includes a first source / drain 110, a gate 130, a second source / drain 120 sequentially disposed along a first direction D1, and a semiconductor layer 140 surrounding and covering the sidewall of the gate 130, the first source / drain 110 and the second source / drain 120 are connected through the semiconductor layer 140 and the gate 130, the first direction D1 is parallel to the top surface of the substrate 10, the capacitor 200 is disposed on one side of the second source / drain 120, and the lower electrode 210 of the capacitor 200 covers a part of the side surface of the semiconductor layer 140. At least one bit line 30 is disposed on one side of the first source / drain 110, the bit line 30 covers a part of the side surface of the semiconductor layer 140, and the contact area between the bit line 30 and the semiconductor layer 140 is smaller than the contact area between the capacitor 200 and the semiconductor layer 140.

[0072] Reference Figure 1 , Figure 2 , Figure 3 In the orientation shown, one side of the first source / drain 110 in this embodiment is the right side of the gate 130 , and one side of the second source / drain 120 is the left side of the gate 130 .

[0073] The present embodiment does not limit the shape of the gate 130 . For example, the projection of the gate 130 on the substrate 10 may be circular, quasi-circular, elliptical, long strip, or rounded rectangular.

[0074] Reference Figure 5 In this embodiment, the gate 130 is disposed above the substrate 10 . The gate 130 includes a top surface and a bottom surface parallel to the substrate 10 , and a circumferential side wall perpendicular to the substrate 10 . The semiconductor layer 140 continuously surrounds and covers the circumferential side wall of the gate 130 .

[0075] In some embodiments, reference Figure 1 , Figure 2 , Figure 3 As shown, the transistor 100 further includes a gate dielectric layer 150, which surrounds the sidewall of the gate 130 and is disposed between the gate 130 and the semiconductor layer 140. That is, the circumferential sidewall of the gate 130 is covered by the gate dielectric layer 150 and the semiconductor layer 140 in sequence.

[0076] Reference Figure 1 , Figure 2 , Figure 3The capacitor 200 is disposed on one side of the second source / drain 120 of the transistor 100, and the second source / drain 120 of the transistor 100 is connected to the lower electrode 210 of the capacitor 200. The bit line 30 is disposed on one side of the first source / drain 110 of the transistor 100, and the first source / drain 110 of the transistor 100 is connected to the bit line 30, and the bit line 30 and the gate 130 are separated by the semiconductor layer 140 and the gate dielectric layer 150.

[0077] According to the capacitance determination formula C=εS / d, where C is capacitance, ε is dielectric constant, S is coupling area, and d is coupling distance. It can be seen that the size of the parasitic capacitance is positively correlated with the coupling area (i.e., the area facing each other of the two conductive devices). The semiconductor structure of this embodiment reduces the contact area between the bit line and the transistor, which is equivalent to reducing the area facing each other between the bit line and the gate of the transistor, thereby reducing the parasitic capacitance between the bit line and the gate of the transistor, reducing the adverse effects of the parasitic capacitance on the semiconductor structure, and is conducive to improving the response speed of the transistor and enhancing the ability of the transistor to read data.

[0078] In some embodiments, reference Figure 1 , Figure 2 , Figure 3 , in a second direction D2 perpendicular to the first direction D1 and parallel to the substrate 10, the semiconductor layer 140 has a first maximum length L1, and the contact surface between the bit line and the semiconductor layer 140 has a second maximum length L2, and the second maximum length L2 is less than one-half of the first maximum length L1. For example, the second maximum length L2 may be one-third, one-quarter, or one-fifth of the first maximum length L1. It can be understood that the projection formed by the contact surface between the bit line 30 and the semiconductor layer 140 on the gate 130 is the area directly facing the bit line 30 and the gate 130. In this embodiment, by reducing the second maximum length L2 of the contact surface between the bit line 30 and the semiconductor layer 140 in the second direction D2, the area directly facing the bit line 30 and the gate 130 is reduced, thereby achieving the effect of reducing the parasitic capacitance between the bit line 30 and the gate 130 of the transistor 100.

[0079] In some examples, reference Figure 1 , Figure 2As shown, the projection of the gate 130 of the transistor 100 on the substrate 10 is circular, the projection of the semiconductor layer 140 on the substrate 10 is annular, the first maximum length L1 of the semiconductor layer 140 in the second direction D2 is the diameter of the semiconductor layer 140, the contact surface between the bit line 30 and the semiconductor layer 140 of the transistor 100 is an arc surface, and the second maximum length L2 of the contact surface between the bit line 30 and the semiconductor layer 140 of the transistor 100 in the second direction D2 is the chord length of the contact surface, that is, the chord length of the contact surface between the bit line 30 and the semiconductor layer 140 is less than half of the diameter of the semiconductor layer 140. In this example, the contact surface between the bit line 30 and the semiconductor layer 140 is an arc surface, the contact area between the bit line 30 and the semiconductor layer 140 is the largest, and the contact resistance is the smallest, while reducing the parasitic capacitance between the bit line 30 and the gate 130 of the transistor 100, it can ensure that the bit line 30 and the semiconductor layer 140 of the transistor 100 have good electrical conduction ability, and further improve the electrical performance of the semiconductor structure.

[0080] In other examples, refer to Figure 3 As shown, the projection of the gate 130 of the transistor 100 on the substrate 10 is a long strip or a rounded rectangle, the projection of the semiconductor layer 140 on the substrate 10 is a long strip or a rounded rectangle surrounding the projection of the gate 130, and the contact surface between the bit line 30 and the semiconductor layer 140 of the transistor 100 is a plane. The second maximum length L2 of the contact surface between the bit line 30 and the semiconductor layer 140 of the transistor 100 in the second direction D2 is less than half of the first maximum length L1 of the semiconductor layer 140 in the second direction D2.

[0081] In some embodiments, reference Figure 1 , Figure 2 , Figure 3 , Figure 4 As shown, and refer to Fig.12 The bit line 30 includes a first conductive layer 310 , which covers a portion of a sidewall of the semiconductor layer 140 away from the capacitor 200 , and the first source / drain 110 of the transistor 100 is disposed in the first conductive layer 310 .

[0082] In some embodiments, reference Figure 2 , Figure 4 As shown, and refer to Fig.17 The first conductive layer 310 includes a first extension portion 311 and at least one second extension portion 312. The first extension portion 311 extends along the second direction D2. The second extension portions 312 are arranged at intervals along the second direction D2 on a side of the first extension portion 311 close to the transistor 100. The second extension portions 312 and the transistors 100 are arranged one by one and cover a portion of the side wall of the semiconductor layer 140 away from the capacitor 200. The first source / drain 110 of the transistor 100 is arranged in the second extension portion 312.

[0083] The bit line 30 is in contact with the semiconductor layer 140 of the transistor 100 through the second extension portion 312. The second maximum length L2 of the contact surface between the bit line 30 and the semiconductor layer 140 is the length of the second extension portion 312 in the second direction D2. In this way, the second maximum length L2 of the contact surface between the bit line 30 and the semiconductor layer 140 is precisely controllable, thereby reducing the parasitic capacitance between the bit line 30 and the gate 130. At the same time, the second extension portion 312 increases the distance between the first extension portion 311 and the transistor 100, and the thickness of the insulating material disposed between the first extension portion 311 and the transistor 100 can be increased (it can be understood that, refer to Figure 4 As shown, the first extension portion 311 and the transistor 100, the transistors 100, and the capacitors 200 are all filled with insulating materials to avoid short-circuiting of adjacent conductive devices), so as to avoid the distance between the first extension portion 311 and the transistor 100 being too close, resulting in the transistor 100 being repeatedly turned on and off during operation of the semiconductor structure, and the transistor 100 and the bit line 30 being turned on and short-circuited, which affects the performance and service life of the semiconductor structure.

[0084] In some embodiments, reference Figure 1 , Figure 2 , Figure 3 As shown, the semiconductor structure also includes a second conductive layer 320, which extends along the first direction D1 on one side of the second source / drain 120, and the second conductive layer 320 covers a portion of the side wall of the semiconductor layer 140. The second source / drain 120 of the transistor 100 is arranged in the second conductive layer 320, and the capacitor 200 uses the second conductive layer 320 as the lower electrode 210. In this way, the lower electrode 210 of the capacitor 200 and the semiconductor layer 140 have a large contact area, which can ensure that the capacitor 200 has a good charge storage capacity.

[0085] Reference Figure 1 , Figure 2 , Figure 3 As shown, the capacitor 200 further includes a high-K dielectric layer 220 and an upper electrode 230 . The high-K dielectric layer 220 covers the sidewall of the second conductive layer 320 away from the semiconductor layer 140 , and the upper electrode 230 covers the high-K dielectric layer 220 .

[0086] In some embodiments, reference Figure 4 As shown, the semiconductor structure further includes a word line 40 disposed on the substrate 10 along a third direction D3 , where the third direction D3 is perpendicular to the top surface of the substrate 10 , and the word line 40 is connected to the gate 130 of the transistor 100 .

[0087] According to an exemplary embodiment, this embodiment provides a semiconductor structure, referring to Figure 6As shown, the semiconductor structure includes at least one memory cell 20, the structure of the memory cell 20 is the same as the structure of the memory cell 20 in the above embodiment, and at least one memory cell 20 is arranged in an array along a first direction D1, and / or a second direction D2, and / or a third direction D3.

[0088] The semiconductor structure further includes at least one bit line 30 and at least one word line 40. The bit line 30 extends along the second direction D2 on the substrate 10 (refer to Figure 5 ), the bit lines 30 are arranged in an array along the first direction D1 and / or the third direction D3; the word lines 40 are arranged on the substrate 10 along the third direction D3, and the word lines 40 are arranged in an array along the first direction D1 and / or the second direction D2. The transistors 100 of the plurality of memory cells 20 are arranged at the intersection nodes of the plurality of word lines 40 and the plurality of bit lines 30, each word line 40 is connected to the gate 130 of a column of transistors 100 arranged along the third direction D3, and each bit line 30 is connected to the first source / drain 110 of a column of transistors 100 arranged along the second direction D2. The bit line 30 covers a portion of the surface of the semiconductor layer 140 of the transistor 100 connected thereto, and the contact area between the bit line 30 and the semiconductor layer 140 is smaller than the contact area between the capacitor 200 and the semiconductor layer 140.

[0089] The semiconductor structure of this embodiment is a memory of three-dimensional stacking of planar ring-channel transistors. By reducing the contact area between the bit line and the transistor, the parasitic capacitance between the bit line and the gate of the transistor is reduced, thereby overcoming the problem of large parasitic capacitance between the planar ring-channel transistor and the bit line, reducing the adverse effects of parasitic capacitance on the semiconductor structure, and helping to improve the response speed of the transistor and enhance the ability of the transistor to read data.

[0090] In an exemplary embodiment of the present disclosure, a method for manufacturing a semiconductor structure is provided. Figure 7 As shown, Figure 7 A flowchart of a method for manufacturing a semiconductor structure provided according to an exemplary embodiment of the present disclosure is shown. Figure 8-Figure 17 The schematic diagram of each stage of the semiconductor structure manufacturing method is shown below. Figure 8-Figure 17 And refer to Figure 1 A method for manufacturing the semiconductor structure of this embodiment is introduced.

[0091] This embodiment does not limit the semiconductor structure. The semiconductor structure will be introduced as a dynamic random access memory (DRAM) as an example below, but this embodiment is not limited to this. The semiconductor structure in this embodiment can also be other types of memory, such as static random access memory (SRAM), flash EPROM, ferroelectric random access memory (FRAM), magnetic random access memory (MRAM), phase change random access memory (PRAM), etc.

[0092] like Figure 7 As shown, a method for manufacturing a semiconductor structure provided by an exemplary embodiment of the present disclosure includes the following steps:

[0093] Step S110: providing a substrate, and forming a stacked structure on the substrate, wherein the stacked structure includes a first dielectric layer and a conductive material layer alternately stacked on the substrate, and the stacked structure defines an isolation region.

[0094] like Figure 8 As shown, the substrate 10 can be made of semiconductor material, insulating material, conductive material or any combination thereof. Figure 5 ) can be a single-layer structure or a multi-layer structure. For example, substrate 10 (refer to Figure 5 ) may be a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate or other III / V semiconductor substrates or II / VI semiconductor substrates. Alternatively, for example, the substrate 10 (see Figure 5 ) may be a layered substrate including, for example, Si / SiGe, Si / SiC, silicon on insulator (SOI), or silicon germanium on insulator.

[0095] In this embodiment, a stacked structure 50 is formed on a substrate 10, and the following implementation methods may be adopted:

[0096] like Figure 8As shown, any one of the deposition processes including chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or sputtering can be used to deposit the insulating material to form a first dielectric layer 51 on the top surface of the substrate 10.

[0097] Then, a conductive material layer 52 is deposited by any of the above deposition processes, and the conductive material layer 52 covers the top surface of the first dielectric layer 51. The steps of forming the first dielectric layer 51 and the conductive material layer 52 are repeated to form a stacked structure 50 on the substrate 10. The stacked structure 50 includes alternately stacked first dielectric layers 51 and conductive material layers 52. In this embodiment, the top layer structure and the bottom layer structure of the stacked structure 50 are both the first dielectric layer 51.

[0098] The first dielectric layers 51 and the conductive material layers 52 of the stacked structure 50 may be alternately stacked in 2 to 1024 layers or more. For example, the first dielectric layers 51 and the conductive material layers 52 may be alternately stacked in 48, 64, 128, 256 or 512 layers.

[0099] The material of the first dielectric layer 51 may include at least one of silicon oxide, silicon nitride or silicon oxynitride. In this embodiment, the material of the first dielectric layer 51 remains silicon oxide.

[0100] The material of the conductive material layer 52 can be selected from metal materials such as cobalt (Co), titanium (Ti), tungsten (W), tantalum (Ta), titanium nitride (TiN), tantalum titanium (TaTi), tungsten nitride (WN), etc. In this embodiment, the material of the conductive material layer 52 includes titanium nitride.

[0101] An isolation region (not numbered in the figure, see Figure 8 , Fig. 9 , Fig. 9 The portion of the stacked structure 50 removed is the isolation region), and the isolation region is used to form an isolation trench 90 in a subsequent step (which will be described in detail in the subsequent step).

[0102] Step S120: removing the stacked structure in the isolation region, forming an isolation trench in the isolation region, and the conductive material layers retained in each layer form an initial conductive layer.

[0103] A mask layer is formed on the top surface of the stacked structure 50, and the mask layer exposes the top surface of the stacked structure 50 in the isolation region. The first dielectric layer 51 and the conductive material layer 52 are etched layer by layer according to the mask layer until the top surface of the substrate 10 is exposed and the etching is stopped to remove the stacked structure 50 in the isolation region, and an isolation trench 90 is formed in the isolation region. In this embodiment, the stacked structure 50 can be etched by a dry process or a wet process.

[0104] Reference Fig. 9 As shown, after the isolation trench 90 is formed, the remaining portion of each conductive material layer 52 is etched to form an initial conductive layer 70 .

[0105] In this embodiment, the present solution is described by taking the implementation mode that the initial conductive layer 70 includes a first initial conductive layer 71 and a second initial conductive layer 72. Fig. 9 As shown, the second initial conductive layer 72 extends along the first direction D1, the first initial conductive layer 71 is arranged on one side of the second initial conductive layer 72, the first initial conductive layer 71 extends along the second direction D2, and along the first direction D1, the first initial conductive layer 71 and the second initial conductive layer 72 are separated and arranged.

[0106] Step S130: filling the isolation trench with a second dielectric layer.

[0107] Reference Fig.10 As shown, any one of chemical vapor deposition, physical vapor deposition, atomic layer deposition or sputtering can be used to deposit and form the second dielectric layer 53 to fill the isolation trench 90, and the top surface of the second dielectric layer 53 is flush with the stacked structure 50 to facilitate subsequent processing of the stacked structure 50. The material of the second dielectric layer 53 may include at least one of silicon oxide, silicon nitride or silicon oxynitride. In this embodiment, the material of the second dielectric layer 53 includes silicon oxide.

[0108] Step S140: etching and removing a portion of the second dielectric layer and a portion of the stacked structure to form a trench penetrating the stacked structure, wherein the trench divides the initial conductive layer into an independently arranged first conductive layer and a second conductive layer, wherein the first conductive layer and the second conductive layer are arranged on both sides of the trench relatively along a first direction, and an area of ​​the first conductive layer exposed by the trench is smaller than an area of ​​the second conductive layer exposed by the trench, wherein the first conductive layer is a bit line.

[0109] Reference Fig.10 , Fig.11 , etching and removing part of the first initial conductive layer 71, part of the second initial conductive layer 72, and part of the first dielectric layer 51 (refer to Figure 8) and a second dielectric layer 52 located between the first initial conductive layer 71 and the second initial conductive layer 72 to form a trench 80, the retained first initial conductive layer 71 is etched to form a first conductive layer 310, and the retained second initial conductive layer 72 is etched to form a second conductive layer 320.

[0110] The projection of the trench 80 on the substrate 10 may be in a circular, quasi-circular, elliptical, long strip, or rounded rectangular shape. Along the first direction D1, the two ends of the trench 80 extend into the first initial conductive layer 71 and the second initial conductive layer 72, respectively. The overlapping area of ​​the projection of the trench 80 on the substrate 10 and the projection of the first initial conductive layer 71 on the substrate 10 is smaller than the overlapping area of ​​the projection of the trench 80 on the substrate 10 and the projection of the second initial conductive layer 72 on the substrate 10. In the first direction D1, the distance between the center line of the trench 80 and the first conductive layer 310 is smaller than the distance between the center line of the trench 80 and the second conductive layer 320, that is, the center line of the trench 80 is biased toward one side of the first conductive layer 310, and the area of ​​the first conductive layer 310 exposed by the trench 80 is smaller than the area of ​​the second conductive layer 320 exposed by the trench 80.

[0111] Reference Fig.11 The first conductive layer 310 formed in this step extends above the substrate 10, and the first conductive layer 310 serves as the bit line 30 of the semiconductor structure. The area of ​​the first conductive layer 310 exposed by the trench 80 is smaller than the area of ​​the second conductive layer 320 exposed by the trench 80, that is, the contact area between the semiconductor layer 140 (which will be described in detail in the subsequent steps) subsequently formed in the trench 80 and the bit line 30 is smaller than the contact area between the semiconductor layer 140 and the second conductive layer 320.

[0112] Step S150: forming a semiconductor layer, wherein the semiconductor layer covers the groove wall of the trench, and the contact area between the first conductive layer and the semiconductor layer is smaller than the contact area between the second conductive layer and the semiconductor layer.

[0113] Reference Fig.12 The semiconductor layer 140 can be formed by deposition using any deposition process such as chemical vapor deposition, physical vapor deposition, atomic layer deposition (ALD) or sputtering. The semiconductor layer 140 covers the channel 80 (see Fig.11 ) of the groove wall.

[0114] The material of the semiconductor layer 140 is a metal oxide semiconductor material, and the material of the metal oxide may be indium gallium zinc oxide (IGZO). When the metal oxide material is indium gallium zinc oxide, the leakage current of the channel of the formed transistor 100 can be reduced, the control force of the channel of the transistor 100 can be improved, and the refresh frequency of the transistor 100 in the semiconductor structure can be ensured. For example, the material of the semiconductor layer 140 may include at least one of the following materials: zinc tin oxide (ZTO), indium zinc oxide (IZO), indium tin oxide (ITO), tungsten-doped indium oxide (IWO), zinc oxide (ZnOx), indium oxide (InOx, In2O3), tin oxide (SnO2), titanium oxide (TiOx), indium zinc oxide (InSnOx), zinc oxynitride (ZnxOyNz), magnesium zinc oxide (MgxZnyOz), indium zinc oxide (InxZnyOz), indium gallium zinc oxide (InxGayZnzO a), zirconium indium zinc oxide (ZrxInyZnzOa), hafnium indium zinc oxide (HfxInyZnzOa), indium tin zinc oxide (SnxInyZnzOa), aluminum tin indium zinc oxide (AlxSnyInzZnaOd), silicon indium zinc oxide (SixInyZnzOa), zinc tin oxide (ZnxSnyOz), aluminum zinc tin oxide (AlxZnySnzOa), gallium zinc tin oxide (GaxZnySnzOa), zirconium zinc tin oxide (ZrxZnySnzOa), indium gallium silicon oxide (InGaSiO).

[0115] Step S160: forming a gate, the gate covers the semiconductor layer and fills the channel.

[0116] In one embodiment, before forming the gate, the following steps are further performed:

[0117] Step S161: forming a gate dielectric layer, wherein the gate dielectric layer covers the semiconductor layer, and the gate electrode and the semiconductor layer are separated by the gate dielectric layer.

[0118] Reference Fig.12 The gate dielectric layer 150 may be formed by deposition using any one of chemical vapor deposition, physical vapor deposition, atomic layer deposition or sputtering processes. The material of the gate dielectric layer 150 may include at least one of silicon dioxide (SiO2), silicon oxynitride (SiON), silicon nitride (SiN), aluminum oxide (Al2O3), aluminum oxynitride (AlON), and hafnium oxide (HfO2).

[0119] The gate 130 may be formed by the following embodiments: the gate 130 is formed by deposition using any of the above deposition processes, and the gate 130 covers the gate dielectric layer 150 and fills the channel 80 (see Fig.11) is not filled. The material of the gate 130 may include metal tungsten or a tungsten compound, metal titanium or a titanium compound. In this embodiment, the material of the gate 130 includes metal tungsten. The portion of the first conductive layer 310 connected to the semiconductor layer 140 serves as the first source / drain 110, and the portion of the second conductive layer 320 connected to the semiconductor layer 140 serves as the second source / drain 120. The gate 150, the semiconductor layer 140, the first source / drain 110, and the second source / drain 120 together form the transistor 100.

[0120] In the method for manufacturing the semiconductor structure of the present embodiment, when forming a channel groove, the center line of the channel groove is biased toward the second conductive layer, so that the area of ​​the first conductive layer exposed by the channel groove is smaller than the area of ​​the second conductive layer exposed by the channel groove, so that after the transistor is formed, the contact area between the first conductive layer (that is, the bit line) and the semiconductor layer of the transistor is smaller than the contact area between the second conductive layer and the semiconductor layer of the transistor, thereby reducing the facing area between the bit line and the gate of the transistor, reducing the parasitic capacitance between the bit line and the gate of the transistor, and thus improving the transistor reading capability.

[0121] In some embodiments, reference Fig.12 , along the second direction D2 perpendicular to the first direction D1, the semiconductor layer 140 has a first maximum length L1, and the contact surface between the first conductive layer 310 and the semiconductor layer 140 has a second maximum length L2, and the second maximum length L2 is less than one-half of the first maximum length L1. For example, the second maximum length L2 may be one-third, one-quarter, or one-fifth of the first maximum length L1.

[0122] It can be understood that the projection of the contact surface between the first conductive layer 310 and the semiconductor layer 140 on the gate 130 is the area directly facing the bit line 30 and the gate 130. In this embodiment, the second maximum length L2 of the contact surface between the first conductive layer 310 and the semiconductor layer 140 in the second direction D2 is reduced, thereby reducing the area directly facing the bit line 30 and the gate 130, thereby further reducing the parasitic capacitance between the bit line 30 and the gate 130 of the transistor 100.

[0123] According to an exemplary embodiment, the manufacturing method of this embodiment includes all the steps of the above embodiment. After step S150, this embodiment further performs the following steps:

[0124] Step S170: using the second conductive layer as a lower electrode, forming a capacitor on one side of the second conductive layer.

[0125] In this embodiment, a capacitor is formed on one side of the second conductive layer, using the following implementation method:

[0126] Step S171: removing a portion of the first dielectric layer and a portion of the second dielectric layer to expose the surface of the second conductive layer.

[0127] A capacitor region (not numbered in the figure) is defined according to the layout of the first conductive layer 310 and the second conductive layer 320, a mask layer (not shown in the figure) defining a capacitor pattern is formed on the top surface of the structure, the mask layer defining the capacitor pattern exposes the top surface of the second dielectric layer 53 in the capacitor region, the second dielectric layer 53 is etched according to the mask layer defining the capacitor pattern, and a first trench 54 is formed in the capacitor region, the first trench 54 exposes the top surface of the substrate 10, and the first trench 54 also exposes a portion of the sidewalls of the second conductive layer 320 and a portion of the sidewalls of the first dielectric layer 51 located between adjacent second conductive layers 320.

[0128] The first dielectric layer 51 exposed by etching the first grooves 54 is etched away to remove the second conductive layer 320 between adjacent first dielectric layers 51 , thereby forming gaps between adjacent second conductive layers 320 and exposing a portion of the top surface and a portion of the bottom surface of the second conductive layer 320 .

[0129] Step S162: forming a high-K dielectric layer, wherein the high-K dielectric layer covers the sidewalls of the second conductive layer.

[0130] Reference Figure 1 , Figure 4 , Figure 5 , Fig.13 As shown, any one of chemical vapor deposition, physical vapor deposition, atomic layer deposition or sputtering can be used to deposit and form the high-K dielectric layer 220, and the high-K dielectric layer 220 covers the exposed sidewalls, bottom surface and top surface of the second conductive layer 320. The material of the high-K dielectric layer 220 may include at least one of strontium titanate (SrTiO3), aluminum oxide (Al2O3), zirconium oxide (ZrO) or hafnium oxide (HfO2).

[0131] Step S163 : forming an upper electrode, wherein the upper electrode covers the high-K dielectric layer, and the second conductive layer, the high-K dielectric layer and the upper electrode form a capacitor 200 .

[0132] Reference Figure 1 , Figure 4 , Figure 5 , Fig.13 As shown, the upper electrode 230 can be formed by depositing any one of chemical vapor deposition, physical vapor deposition, atomic layer deposition or sputtering processes. The upper electrode 230 covers the surface of the high-K dielectric layer 220. The material of the upper electrode 230 may include a high melting point metal, such as at least one of cobalt (Co), titanium (Ti), nickel (Ni), tungsten (W) and / or molybdenum (Mo); or, the material of the upper electrode 230 may also include a metal nitride, such as titanium nitride, titanium silicon nitride, titanium aluminum nitride, tantalum nitride, tantalum silicon nitride, tantalum aluminum nitride, and / or tungsten nitride.

[0133] The second conductive layer 320 serves as the lower electrode 210, and together with the high-K dielectric layer 220 and the upper electrode 230, forms a capacitor 200. The contact area between the lower electrode 210 of the capacitor 200 and the semiconductor layer 140 of the transistor 100 is larger than the contact area between the bit line 30 and the semiconductor layer 140, thereby reducing the parasitic capacitance between the bit line 30 and the gate 130 of the transistor 100, while ensuring that the capacitor 200 has good charge storage capacity.

[0134] In some embodiments, reference Figure 8 , Fig.14 As shown, the initial conductive layer 70 formed by etching the stacked structure 50 includes a first portion 701 extending along a first direction D1, a second portion 702 arranged on one side of the first portion 701, and a third portion 703 connecting the first portion 701 and the second portion 702, the second portion 702 extending along a second direction D2, the third portion 703 being arranged between the first portion 701 and the second portion 702, and the size of the third portion 703 along the second direction D2 is smaller than the size of the first portion 701.

[0135] In this embodiment, a trench penetrating the stacked structure is formed by the following implementation method:

[0136] Reference Fig.15 As shown, first, a second dielectric layer 53 is formed to fill the removed portion of the stacked structure 50 .

[0137] Reference Fig.16 , Fig.17 As shown, then, part of the first part 701, part of the third part 703, part of the first dielectric layer 51 and part of the second dielectric layer are etched away to form a channel groove 80, and the first part 701 retained by etching forms a first conductive layer 310, and the second part 702 and the third part 703 retained by etching together form a second conductive layer 320.

[0138] In some embodiments, reference Figure 3 , Fig.16 As shown, the projection of the channel groove 80 formed on the substrate 10 is in the shape of a long strip, and the projection of the gate 130 of the transistor 100 formed on the substrate 10 is in the shape of a long strip.

[0139] In the method for manufacturing the semiconductor structure of the present embodiment, the length of the contact surface between the bit line and the semiconductor layer of the transistor in the second direction, that is, the length of the third part in the second direction, by limiting the size of the third part in the present embodiment, the area of ​​the contact surface between the bit line and the semiconductor layer of the transistor can be accurately controlled, thereby reducing the parasitic capacitance between the bit line and the gate of the transistor. The process is simple and highly controllable, and the formed semiconductor structure is more in line with expectations.

[0140] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features of the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0141] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.

Claims

1. A semiconductor structure, characterized in that: include: substrate; At least one memory cell, the memory cell is arranged on the substrate, each of the memory cells comprises a transistor and a capacitor, the transistor comprises a first source / drain, a gate, a second source / drain arranged in sequence along a first direction, and a semiconductor layer surrounding and covering a side wall of the gate, the first source / drain and the second source / drain are connected to the gate through the semiconductor layer, the first direction is parallel to the top surface of the substrate, the capacitor is arranged on one side of the second source / drain, and the lower electrode of the capacitor covers a part of the side surface of the semiconductor layer; At least one bit line is disposed on one side of the first source / drain, the bit line covers a portion of a side surface of the semiconductor layer, and a contact area between the bit line and the semiconductor layer is smaller than a contact area between the capacitor and the semiconductor layer.

2. The semiconductor structure according to claim 1, characterized in that: In a second direction perpendicular to the first direction and parallel to the substrate, the semiconductor layer has a first maximum length, and a contact surface between the bit line and the semiconductor layer has a second maximum length, which is less than half of the first maximum length.

3. The semiconductor structure according to claim 2, characterized in that: The bit line includes a first conductive layer, the first conductive layer covers a portion of a side wall of the semiconductor layer at a side away from the capacitor, and the first source / drain is disposed in the first conductive layer.

4. The semiconductor structure according to claim 3, characterized in that: The first conductive layer includes a first extension portion and at least one second extension portion, the first extension portion extends along the second direction, the second extension portions are spaced apart along the second direction on a side of the first extension portion close to the transistor, the second extension portions and the transistors are arranged one by one and cover a portion of the side wall of the semiconductor layer away from the capacitor, and the first source / drain is arranged in the second extension portion.

5. The semiconductor structure according to claim 1, characterized in that: The semiconductor structure further comprises: a second conductive layer, the second conductive layer extending along the first direction on one side of the second source / drain electrode, the second conductive layer covering a portion of a side wall of the semiconductor layer, and the second source / drain electrode being arranged in the second conductive layer; The capacitor uses the second conductive layer as the lower electrode.

6. The semiconductor structure according to claim 1, characterized in that The transistor further comprises: A gate dielectric layer surrounds the sidewall of the gate and is disposed between the gate and the semiconductor layer.

7. The semiconductor structure according to claim 1, characterized in that: At least one of the storage units is arranged in an array on the substrate along the first direction, and / or the second direction, and / or the third direction, and the first direction, the second direction, and the third direction are perpendicular to each other; the semiconductor structure further includes: At least one word line is vertically arranged on the substrate along the third direction, and each of the word lines is connected to the gates of a column of the transistors arranged along the third direction.

8. A method for manufacturing a semiconductor structure, characterized in that: The following steps are involved: Providing a substrate, forming a stacked structure on the substrate, the stacked structure comprising a first dielectric layer and a conductive material layer alternately stacked on the substrate, and the stacked structure defines an isolation region; The stacked structure of the isolation region is removed, an isolation trench is formed in the isolation region, and the conductive material layers retained in each layer form an initial conductive layer; Filling a second dielectric layer in the isolation trench; Etching and removing a portion of the second dielectric layer and a portion of the stacked structure to form a trench penetrating the stacked structure, wherein the trench divides the initial conductive layer into a first conductive layer and a second conductive layer that are independently arranged, wherein the first conductive layer and the second conductive layer are arranged on opposite sides of the trench along a first direction, and an area of ​​the first conductive layer exposed by the trench is smaller than an area of ​​the second conductive layer exposed by the trench, wherein the first conductive layer is a bit line; forming a semiconductor layer, wherein the semiconductor layer covers a groove wall of the trench, and a contact area between the first conductive layer and the semiconductor layer is smaller than a contact area between the second conductive layer and the semiconductor layer; A gate is formed, the gate covering the semiconductor layer and filling the channel.

9. The method for manufacturing a semiconductor structure according to claim 8, characterized in that: Along a second direction perpendicular to the first direction, the semiconductor layer has a first maximum length, and a contact surface between the first conductive layer and the semiconductor layer has a second maximum length, and the second maximum length is less than half of the first maximum length.

10. The method for manufacturing a semiconductor structure according to claim 9, characterized in that: The initial conductive layer comprises a first initial conductive layer and a second initial conductive layer, the second initial conductive layer extends along the first direction, the first initial conductive layer is arranged on one side of the second initial conductive layer, the first initial conductive layer extends along the second direction, and the first initial conductive layer and the second initial conductive layer are arranged separately along the first direction; forming a channel groove penetrating the stacked structure, comprising: Etching and removing a portion of the first initial conductive layer, a portion of the second initial conductive layer, a portion of the first dielectric layer, and the second dielectric layer located between the first initial conductive layer and the second initial conductive layer to form the trench, etching the retained first initial conductive layer to form the first conductive layer, and etching the retained second initial conductive layer to form the second conductive layer; An overlapping area of ​​a projection of the trench on the substrate and a projection of the first initial conductive layer on the substrate is smaller than an overlapping area of ​​a projection of the trench on the substrate and a projection of the second initial conductive layer on the substrate.

11. The method for manufacturing a semiconductor structure according to claim 9, characterized in that: The initial conductive layer comprises a first portion extending along the first direction, a second portion arranged at one side of the first portion, and a third portion connecting the first portion and the second portion, wherein the second portion extends along the second direction, the third portion is arranged between the first portion and the second portion, and along the second direction, the size of the third portion is smaller than that of the first portion; Forming a channel groove penetrating the stacked structure, comprising: Part of the first part, part of the third part, part of the first dielectric layer and part of the second dielectric layer are etched away to form the channel groove, the first part retained by etching is formed into the first conductive layer, and the second part and the third part retained by etching are formed into the second conductive layer.

12. The method for manufacturing a semiconductor structure according to claim 8, characterized in that: Before forming the gate, it also includes: A gate dielectric layer is formed, wherein the gate dielectric layer covers the semiconductor layer, and the gate electrode and the semiconductor layer are separated by the gate dielectric layer.

13. The method for manufacturing a semiconductor structure according to claim 8, characterized in that: The method for manufacturing the semiconductor structure further includes: The second conductive layer is used as a lower electrode, and a capacitor is formed on one side of the second conductive layer.

14. The method for manufacturing a semiconductor structure according to claim 13, characterized in that: A capacitor is formed on one side of the second conductive layer, comprising: removing a portion of the dielectric layer to expose the sidewall of the second conductive layer; forming a high-K dielectric layer, wherein the high-K dielectric layer covers the sidewalls of the second conductive layer; An upper electrode is formed, wherein the upper electrode covers the high-K dielectric layer, and the second conductive layer, the high-K dielectric layer and the upper electrode form the capacitor.

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