Data link processing method, apparatus, device, medium and product

Abstract

The application provides a data link processing method, device, equipment, medium and product. The method comprises the following steps: acquiring a plurality of measurement data of a quantum measurement and control instrument; in response to a data write instruction, determining a data flow direction of each measurement data according to a preset data storage strategy; based on each data flow direction, selecting a target first-in-first-out (FIFO) memory for storing each measurement data from a plurality of FIFO memories and writing the measurement data into the target FIFO memory; in response to a data read instruction, reading the corresponding measurement data from each target FIFO memory; performing data construction on each measurement data to obtain a plurality of target data; and delivering the plurality of target data to an external device. The data link processing method provided by the application uses a plurality of FIFO memories to cache a large amount of measurement data, realizes instant data storage and reading operation, reduces the response time and delay time, further timely performs the data construction and data delivery process, and effectively improves the data processing speed.

Description

Technical Field

[0001] This invention relates to the field of data processing technology, and in particular to a data link processing method, apparatus, device, medium, and product. Background Technology

[0002] Traditional quantum telemetry and control instruments employ a top-down data link processing method, consisting of four processes: data acquisition, data standardization, data construction, and data transmission. In this process, traditional quantum telemetry and control instruments use a single FIFO (First-In-First-Out) memory or pre-store small batches of data without a FIFO memory, resulting in minimal impact on time latency.

[0003] With the ever-increasing volume of big data, the data link processing methods of traditional quantum measurement and control instruments can no longer support large-scale data processing, resulting in problems such as slow data processing speed and long response time. Summary of the Invention

[0004] This invention provides a data link processing method, apparatus, device, medium, and product to solve the problems of slow data processing speed and long response time in the prior art.

[0005] In a first aspect, the present invention provides a data link processing method, comprising:

[0006] Acquire multiple measurement data from the quantum measurement and control instrument;

[0007] In response to a data write command, the data flow direction of each measurement data is determined according to a preset data storage strategy;

[0008] Based on the data flow direction of each measurement data, a target FIFO memory for storing each measurement data is selected from multiple first-in-first-out FIFO memories, and each measurement data is written into the corresponding target FIFO memory;

[0009] In response to a data read command, the corresponding measurement data is read from the FIFO memory of each target.

[0010] Data construction is performed on each measurement data point to obtain multiple target data points;

[0011] The multiple target data are sent to external devices.

[0012] In one embodiment, the plurality of FIFO memories include at least a first FIFO memory and a second FIFO memory; when determining the data flow direction of each measurement data according to a preset data storage strategy, the following steps are performed for each measurement data:

[0013] If the first FIFO memory issues a write request signal, it is determined that the measurement data flows to the first FIFO memory;

[0014] If the first FIFO memory issues a write-full signal and the second FIFO memory issues a write request signal, then it is determined that the measurement data flows to the second FIFO memory.

[0015] If the first FIFO memory sends a full write signal and the second FIFO memory sends a full write signal, then it is determined that the measurement data will not flow to the first FIFO memory and the second FIFO memory for the time being.

[0016] In one embodiment, reading the corresponding measurement data from each target FIFO memory includes:

[0017] First, read the corresponding measurement data from the target FIFO memory belonging to the first FIFO memory;

[0018] Then, the corresponding measurement data is read from the target FIFO memory belonging to the second FIFO memory.

[0019] In one embodiment, when constructing data for each measurement data to obtain multiple target data, the following steps are performed for each measurement data:

[0020] The measurement data is divided into multiple data segments according to a preset number of bits per period.

[0021] Each split data point is processed through a data pipeline to obtain multiple processed data points.

[0022] The target data is obtained by integrating the multiple processed data.

[0023] In one embodiment, the integration of the multiple processed data to obtain the target data includes:

[0024] Based on the location of each processed data point within the original measurement data, the multiple processed data points are spliced ​​and integrated to obtain integrated data.

[0025] The integrated data is then concatenated again at the end to obtain the target data.

[0026] In one embodiment, when the plurality of target data are sent to an external device, the following steps are performed for each target data:

[0027] In response to a write request signal from the third FIFO memory, the target data is written into the third FIFO memory;

[0028] In response to a data read command, the target data is read from the third FIFO memory;

[0029] The target data is standardized to obtain standard data;

[0030] The standard data is divided into multiple signals and transmitted to external devices.

[0031] In a second aspect, the present invention also provides a data link processing apparatus, comprising:

[0032] The acquisition module is used to acquire multiple measurement data from the quantum measurement and control instrument;

[0033] The determination module is used to determine the data flow direction of each measurement data in response to a data write command, according to a preset data storage strategy.

[0034] The data writing module is used to select a target FIFO memory for storing each measurement data from multiple first-in-first-out FIFO memories based on the data flow direction of each measurement data, and write each measurement data into the corresponding target FIFO memory;

[0035] The data reading module is used to read the corresponding measurement data from each target FIFO memory in response to a data reading command;

[0036] The data construction module is used to construct data for each measurement data to obtain multiple target data.

[0037] The data delivery module is used to deliver the multiple target data to external devices.

[0038] Thirdly, the present invention provides an apparatus comprising an electronic device, the electronic device including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the steps of any of the data link processing methods described above.

[0039] Fourthly, the present invention also provides a medium comprising a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of any of the data link processing methods described above.

[0040] Fifthly, the present invention also provides a product comprising a computer program product, the computer program product comprising a computer program, the computer program being able to be stored on a non-transitory computer-readable storage medium, and the computer program, when executed by the processor, implementing the steps of any of the data link processing methods described above.

[0041] The data link processing method, apparatus, device, medium, and product provided by this invention can use multiple FIFO memories to cache large batches of measurement data after the arrival of the quantum measurement and control instrument. According to the preset data storage strategy, each measurement data can be written to the corresponding target FIFO memory, eliminating the need to wait for other data processing to complete, realizing real-time data storage and retrieval operations, reducing response time and latency. Once the corresponding measurement data is read from the target FIFO memory, the data construction and data distribution process can be carried out in a timely manner, realizing a complete top-down link, effectively improving data processing speed, and thus improving the overall efficiency of data link processing. Attached Figure Description

[0042] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0043] Figure 1 This is one of the flowcharts illustrating the data link processing method provided by the present invention.

[0044] Figure 2 This is the second flowchart of the data link processing method provided by the present invention.

[0045] Figure 3 This is a schematic diagram of the internal structure of the data receiving module provided by the present invention.

[0046] Figure 4 This is a schematic diagram of the internal structure of the data construction module provided by the present invention.

[0047] Figure 5 This is a schematic diagram of the internal structure of the data delivery module provided by the present invention.

[0048] Figure 6 This is a schematic diagram of the data link processing device provided by the present invention.

[0049] Figure 7 This is a schematic diagram of the structure of the electronic device provided by the present invention. Detailed Implementation

[0050] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0051] The terms "first," "second," etc., used in this invention are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the invention can be implemented in orders other than those illustrated or described herein.

[0052] The following is combined with Figures 1-7 This invention describes the data link processing methods, apparatus, devices, media, and products provided by the present invention.

[0053] Combination Figure 1 and Figure 2 , Figure 1 This is one of the flowcharts illustrating the data link processing method provided by the present invention. Figure 2 This is the second flowchart of the data link processing method provided by the present invention.

[0054] like Figure 1 As shown, the method includes the following:

[0055] Step 101: Acquire multiple measurement data from the quantum measurement and control instrument;

[0056] Step 102: In response to the data write command, determine the data flow direction of each measurement data according to the preset data storage strategy;

[0057] Step 103: Based on the data flow direction of each measurement data, select the target FIFO memory from multiple first-in-first-out FIFO memories to store each measurement data, and write each measurement data into the corresponding target FIFO memory;

[0058] Step 104: In response to the data read command, read the corresponding measurement data from each target FIFO memory;

[0059] Step 105: Perform data construction for each measurement data to obtain multiple target data;

[0060] Step 106: Send the multiple target data to external devices.

[0061] It should be noted that the data link processing method provided in this embodiment of the invention is implemented based on a parallel processor in the data link processing device, such as a Field Programmable Gate Array (FPGA). To address the problems of slow processing speed, long response time, and weak concurrency capabilities in existing technologies when handling large volumes of data, this embodiment of the invention provides an efficient and simple data link processing method for a quantum telemetry and control instrument. This method simplifies the data link processing process by addressing the three major problems mentioned above, including three processes: data reception, data construction, and data transmission. These processes are implemented by a data reception module, a data construction module, and a data transmission module, respectively. (See reference...) Figure 2 Data reception is used for data preprocessing, data construction is used for data reconstruction, and data distribution is used for data standardization. Data reception and data distribution address the problem of long response times, while data construction addresses the problems of slow processing speed and weak concurrency capabilities.

[0062] This invention describes a data link processing method using a parallel processor as the execution subject as an example.

[0063] Combination Figure 3 , Figure 3 This is the internal structure of the data receiving module provided by the present invention. For example... Figure 3 As shown, the data receiving module internally consists of an arbitrator and multiple FIFO memories. This embodiment uses two FIFO memories as an example, but is not limited to two FIFO memories. For distinction, the two FIFO memories are divided into a first FIFO memory and a second FIFO memory, denoted as FIFO1 and FIFO2. The arbitrator determines the flow direction of external data data0, whether it flows to the first FIFO memory via data1 or to the second FIFO memory via data2. The first and second FIFO memories are used to alternately buffer data and complete the cross-clock domain conversion of data from the low clock domain to the high clock domain.

[0064] It should be noted that arbitrators are typically used to coordinate access requests for shared resources from multiple devices or processing units, ensuring efficient system operation and effective resource utilization. Their main function is to determine, based on a specific decision algorithm, which device or processing unit gains the right to use the resource at a given time. FIFO (First-In, First-Out) memory is a special type of memory that follows the first-in, first-out data access principle. Simply put, data is stored in the order it arrives and read out in the same order, similar to a queuing mechanism. This type of memory is typically used in situations where data needs to be processed strictly in chronological order. During data link processing, FIFO memory can effectively buffer data, making data flow more orderly and controllable, and preventing data corruption or loss.

[0065] Specifically, when multiple FIFO memories still have cache space inside, the multiple FIFO memories will send a request to the arbitrator to make data available for writing, informing the arbitrator that data storage is currently possible. The parallel processor generates corresponding data write instructions based on the data available for writing requests sent by the multiple FIFO memories to the arbitrator.

[0066] Furthermore, when multiple measurement data from the quantum measurement and control instrument are ready, the parallel processor responds to the data write command and determines the data flow direction of each measurement data according to the preset data storage strategy.

[0067] The preset data storage strategy is an internal arbiter mechanism with three current states that determine the data flow based on the write request signal (locked state) and the full signal (unlocked state) of the FIFO memory. The three current states are: writing data to the first FIFO memory, writing data to the second FIFO memory, and not writing data to either the first or second FIFO memory. Following the principle of "writing to the first FIFO memory first, then to the second FIFO memory," when the state is "writing data to the first FIFO memory," the first FIFO memory is filled before writing data to the second FIFO memory; when the state is "writing data to the second FIFO memory," the second FIFO memory is filled before writing data to the first FIFO memory; and when the state is "not writing data to either the first or second FIFO memory," the system waits for subsequent data to arrive before selecting which FIFO memory to write data to, following the principle of "writing to the first FIFO memory first, then to the second FIFO memory."

[0068] Furthermore, based on the data flow direction of each measurement data, the parallel processor selects the target FIFO memory from multiple FIFO memories to store each measurement data. That is, the target FIFO memory is either the first FIFO memory or the second FIFO memory. Therefore, multiple data can be stored according to the principle of "writing to the first FIFO memory first and then writing to the second FIFO memory" to achieve the alternating storage of data between the two FIFO memories.

[0069] Furthermore, the parallel processor writes each measurement data point into the corresponding target FIFO memory.

[0070] Furthermore, after multiple measurement data are stored in their corresponding target FIFO memories, these target FIFO memories will send readable signals to the next-level data construction module.

[0071] Combination Figure 4 , Figure 4 This is the internal structure of the data construction module provided by the present invention. For example... Figure 4 As shown, the data construction module includes a controller. The controller generates data read instructions to read data (data3) from the previous-level data receiving module. Data (data3) can be considered as the corresponding measurement data read from the target FIFO memory through a shared signal channel. The arbitrator can select when the first FIFO memory occupies data3 and when the second FIFO memory occupies data3.

[0072] Furthermore, the controller generates a data read instruction, and the parallel processor responds to the data read instruction by reading the corresponding measurement data from each target FIFO memory through a shared signal channel and transmitting it to the data construction module for data construction.

[0073] It's important to note that FIFO memory enables cross-clock domain data transfer from low to high clock domains because the speed of writing to the FIFO (low clock) differs from the speed of reading from the FIFO (high clock). By writing data at a low clock speed and then reading it at a high clock speed, a simple cross-clock domain processing is achieved. When the next stage completes data reading and uses a high-frequency clock, the FIFO memory decouples it from the previous stage's clock domain, thus avoiding clock signal synchronization issues and ensuring data accuracy and stability.

[0074] Furthermore, the parallel processor constructs data for each measurement data through a data construction module, thereby obtaining the target data corresponding to each measurement data after data construction.

[0075] Furthermore, the parallel processor uses a data delivery module to send multiple target data to external devices.

[0076] The data link processing method provided by this invention can cache large amounts of measurement data using multiple FIFO memories after the arrival of the quantum measurement and control instrument. According to the preset data storage strategy, each measurement data can be written to the corresponding target FIFO memory, eliminating the need to wait for other data processing to complete. This enables real-time data storage and retrieval operations, reducing response time and latency. Once the corresponding measurement data is read from the target FIFO memory, the data construction and data distribution process can be carried out in a timely manner, realizing a complete top-down link, effectively improving data processing speed, and thus improving the overall efficiency of data link processing.

[0077] Furthermore, based on step 102, when determining the data flow direction of each measurement data according to the preset data storage strategy, the following steps are performed for each measurement data:

[0078] If the first FIFO memory issues a write request signal, it is determined that the measurement data flows to the first FIFO memory;

[0079] If the first FIFO memory issues a write-full signal and the second FIFO memory issues a write request signal, then it is determined that the measurement data flows to the second FIFO memory.

[0080] If the first FIFO memory sends a full write signal and the second FIFO memory sends a full write signal, then it is determined that the measurement data will not flow to the first FIFO memory and the second FIFO memory for the time being.

[0081] Specifically, the parallel processor uses an arbitrator to determine whether there is still cache space inside the first FIFO memory and the second FIFO memory.

[0082] Furthermore, if the first FIFO memory issues a write request signal, the arbitrator determines that the measurement data flows to the first FIFO memory and informs the parallel processor. The parallel processor then determines that the measurement data flows to the first FIFO memory and writes the measurement data into the first FIFO memory.

[0083] Furthermore, if the first FIFO memory issues a write-full signal and the second FIFO memory issues a write request signal, the arbitrator determines that the measurement data flows to the second FIFO memory and informs the parallel processor. The parallel processor then determines that the measurement data flows to the second FIFO memory and writes the measurement data into the second FIFO memory.

[0084] Furthermore, if both the first FIFO memory and the second FIFO memory issue a write-full signal, the arbitrator determines that the measurement data will not flow to the first FIFO memory and the second FIFO memory for the time being. Furthermore, the parallel processor determines that the measurement data will not flow to the first FIFO memory and the second FIFO memory for the time being, in order to determine whether subsequent data needs to flow to the first FIFO memory or the second FIFO memory.

[0085] In one embodiment, the state "writing data to the first FIFO memory" is numbered 1, the state "writing data to the second FIFO memory" is numbered 2, and the state "not writing data to the first FIFO memory or the second FIFO memory" is numbered 3. The first FIFO memory is denoted as FIFO1, and the second FIFO memory is denoted as FIFO2. The loop mechanism consisting of these three states is represented as follows: .

[0086] This invention uses two FIFO registers to alternately store measurement data, which avoids empty cycles, improves real-time response time, supports large-scale data storage, and ensures high data reception sustainability, thereby improving operating efficiency and response speed.

[0087] Further, based on step 104, reading the corresponding measurement data from each target FIFO memory includes:

[0088] First, read the corresponding measurement data from the target FIFO memory belonging to the first FIFO memory;

[0089] Then, the corresponding measurement data is read from the target FIFO memory belonging to the second FIFO memory.

[0090] Specifically, following the principle of "reading the first FIFO memory first and then reading the second FIFO memory", the parallel processor first reads the corresponding measurement data from the target FIFO memory belonging to the first FIFO memory, and then reads the corresponding measurement data from the target FIFO memory belonging to the second FIFO memory.

[0091] This can be understood as follows: the parallel processor reads multiple measurement data stored in the first FIFO memory in sequence according to the first-in-first-out principle of the FIFO memory; furthermore, the parallel processor reads multiple measurement data stored in the second FIFO memory in sequence according to the first-in-first-out principle of the FIFO memory.

[0092] The embodiments of the present invention read measurement data sequentially according to the principle of "reading the first FIFO memory first and then reading the second FIFO memory", which can ensure that the data is read and processed in the correct order and timing, and avoid data loss or confusion.

[0093] Furthermore, based on step 105, when constructing data for each measurement data to obtain multiple target data, the following steps are performed for each measurement data:

[0094] The measurement data is divided into multiple data segments according to a preset number of bits per period.

[0095] Each split data point is processed through a data pipeline to obtain multiple processed data points.

[0096] The target data is obtained by integrating the multiple processed data.

[0097] like Figure 4 As shown, the data construction module also includes an extraction and distribution submodule, a data processing submodule, and a splicing and integration submodule. The extraction and distribution submodule splits the unprocessed data (data3) into multiple distributed data streams (data4), for example, splitting it into four streams: data_1, data_2, data_3, and data_4. The data processing submodule performs pipelined processing on each of the multiple distributed data streams (data4) to obtain the processed data (data5). The splicing and integration submodule splices the processed multiple data streams (data5) into a new, spliced ​​and integrated data stream (data6), which is then transmitted to the next-level module. This enables data reorganization and accelerates the processing.

[0098] Specifically, the parallel processor splits the measurement data into multiple split data according to a preset number of bits per cycle. This can be considered as splitting one measurement data into multiple split data for transmission. The preset number of bits is set according to the actual situation.

[0099] In one embodiment, the extraction is performed by splitting the data in 4-bit cycles. For example, bits 1, 5, 9, ... form data_1; bits 2, 6, 10, ... form data_2; bits 3, 7, 11, ... form data_3; and bits 4, 8, 12, ... form data_4. The extracted data is transmitted in real time to the corresponding next-level data processing.

[0100] Furthermore, the parallel processor pipelines each split data point to obtain multiple processed data points.

[0101] It's important to note that each data pipeline process involves a one-cycle delay while temporarily storing the data in a register, followed by another one-cycle delay and temporary storage in a register. These two temporary data storage cycles are used simultaneously for computation without affecting the continuous input of data4. This is essentially a process of implementing pipelined operations. Programmatically, this involves delaying the arrival time of data and temporarily storing the delayed data. Parallel processors can simultaneously perform computations and updates on the delayed data. This data pipelined processing method further improves the speed of data pipelined processing, and simultaneous pipelined processing across multiple paths also enhances data concurrency capabilities.

[0102] Furthermore, the parallel processor integrates multiple processing data to obtain the target data.

[0103] This invention, through splitting measurement data and forming multiple distributed data streams, enables the simultaneous processing of single-channel data into multiple channels, effectively improving data concurrency capabilities and significantly increasing the speed of data processing in high clock domains. Furthermore, by integrating the multiple data streams, complete data can be obtained again, thus ensuring data integrity while improving data processing speed.

[0104] Furthermore, the integration of the multiple processed data to obtain the target data includes:

[0105] Based on the location of each processed data point within the original measurement data, the multiple processed data points are spliced ​​and integrated to obtain integrated data.

[0106] The integrated data is then concatenated again at the end to obtain the target data.

[0107] like Figure 4 As shown, the four data streams data5_1, data5_2, data5_3, and data5_4, which have completed the data pipeline processing, are entered into the splicing and integration process in real time. The splicing process is carried out according to the order of the splitting and the corresponding positions. The difference is that each data stream is spliced ​​again into the same data after splicing. That is, the bit width of data6 is twice that of data3, which further improves the transmission bandwidth.

[0108] Specifically, the parallel processor concatenates and integrates multiple processing data according to their corresponding positions in the original measurement data. This can also be understood as concatenating and integrating multiple processing data according to their corresponding positions in the order of splitting, thus obtaining integrated data.

[0109] Furthermore, the parallel processor concatenates the integrated data again at the end to obtain the target data. At this point, the bit width of the target data is twice the bit width of its corresponding original measurement data, which can further improve the transmission bandwidth.

[0110] This invention integrates multiple data streams according to their original splitting order, thereby reconstructing complete data. This ensures data integrity while improving data processing speed. Furthermore, by adding the same data to the end of the integrated data, the transmission bandwidth is increased, significantly improving data transmission speed and thus efficiently completing data link processing.

[0111] Furthermore, based on step 106, when sending the plurality of target data to external devices, the following steps are performed for each target data:

[0112] In response to a write request signal from the third FIFO memory, the target data is written into the third FIFO memory;

[0113] In response to a data read command, the target data is read from the third FIFO memory;

[0114] The target data is standardized to obtain standard data;

[0115] The standard data is divided into multiple signals and transmitted to external devices.

[0116] Combination Figure 5 , Figure 5 This is a schematic diagram of the internal structure of the data delivery module provided by the present invention. For example... Figure 5 As shown, the data delivery module consists of a third FIFO register and a standardization submodule. The third FIFO register is FIFO3. It buffers the data from the previous level, data6. The standardization submodule reads data7 from the third FIFO register, standardizes it, and outputs the standard data format data8 for easy recognition by the next level.

[0117] Specifically, when there is cache space inside the third FIFO memory, it will send a write request signal to the data construction module. Furthermore, the parallel processor generates the corresponding data write instruction based on the write request signal sent by the third FIFO memory.

[0118] Furthermore, in response to a data write instruction, the parallel processor writes the target data into the third FIFO memory.

[0119] Furthermore, the standardization submodule sends a read signal, and the parallel processor generates the corresponding data read instruction based on the read signal sent by the standardization submodule.

[0120] Furthermore, in response to a data read instruction, the parallel processor reads the target data from the third FIFO memory.

[0121] Furthermore, the parallel processor performs standardization processing on the target data through the standardization submodule to obtain standard data. The standardization process includes, but is not limited to, processing methods such as uniform bit width, timing, and differential processing.

[0122] Furthermore, the parallel processor divides standard data into multiple signals and transmits them to external devices through a standardized submodule. It can transmit signals to external devices or external chips in four ways.

[0123] This invention embodiment again uses FIFO memory to temporarily store the constructed target data, thereby realizing multi-level register temporary data storage, ensuring uninterrupted data processing, strong data pipeline operability, further standardizing the target data to ensure data consistency and accuracy, facilitating identification at the next level, and dividing the standard data into multiple signals for transmission to external devices or external chips, which can significantly improve the overall transmission efficiency and speed when a large amount of data needs to be transmitted simultaneously, thereby improving the overall efficiency of data link processing.

[0124] The data link processing apparatus provided by the present invention is described below. The data link processing apparatus described below and the data link processing method described above can be referred to in correspondence.

[0125] Reference Figure 6 , Figure 6 This is a schematic diagram of the data link processing device provided by the present invention.

[0126] The data link processing device includes:

[0127] The acquisition module 610 is used to acquire multiple measurement data from the quantum measurement and control instrument.

[0128] The determination module 620 is used to determine the data flow direction of each measurement data in response to a data write command, according to a preset data storage strategy.

[0129] The data writing module 630 is used to select a target FIFO memory for storing each measurement data from multiple first-in-first-out FIFO memories based on the data flow direction of each measurement data, and write each measurement data into the corresponding target FIFO memory.

[0130] The data reading module 640 is used to read the corresponding measurement data from each target FIFO memory in response to a data reading command.

[0131] The data construction module 650 is used to construct data for each measurement data to obtain multiple target data.

[0132] The data distribution module 660 is used to distribute the multiple target data to external devices.

[0133] The data link processing device provided by this invention can cache large amounts of measurement data using multiple FIFO memories after the arrival of the quantum measurement and control instrument. According to the preset data storage strategy, each measurement data can be written into the corresponding target FIFO memory, eliminating the need to wait for other data processing to complete. This enables real-time data storage and retrieval operations, reducing response time and latency. Once the corresponding measurement data is read from the target FIFO memory, the data construction and data distribution process can be carried out in a timely manner, realizing a complete top-down link, effectively improving data processing speed, and thus improving the overall efficiency of data link processing.

[0134] Furthermore, the determining module 620 is also used for:

[0135] If the first FIFO memory issues a write request signal, it is determined that the measurement data flows to the first FIFO memory;

[0136] If the first FIFO memory issues a write-full signal and the second FIFO memory issues a write request signal, then it is determined that the measurement data flows to the second FIFO memory.

[0137] If the first FIFO memory sends a full write signal and the second FIFO memory sends a full write signal, then it is determined that the measurement data will not flow to the first FIFO memory and the second FIFO memory for the time being.

[0138] Furthermore, the data reading module 640 is also used for:

[0139] First, read the corresponding measurement data from the target FIFO memory belonging to the first FIFO memory;

[0140] Then, the corresponding measurement data is read from the target FIFO memory belonging to the second FIFO memory.

[0141] Furthermore, the data construction module 650 is also used for:

[0142] The measurement data is divided into multiple data segments according to a preset number of bits per period.

[0143] Each split data point is processed through a data pipeline to obtain multiple processed data points.

[0144] The target data is obtained by integrating the multiple processed data.

[0145] Furthermore, the data construction module 650 is also used for:

[0146] Based on the location of each processed data point within the original measurement data, the multiple processed data points are spliced ​​and integrated to obtain integrated data.

[0147] The integrated data is then concatenated again at the end to obtain the target data.

[0148] Furthermore, the data distribution module 660 is also used for:

[0149] In response to a write request signal from the third FIFO memory, the target data is written into the third FIFO memory;

[0150] In response to a data read command, the target data is read from the third FIFO memory;

[0151] The target data is standardized to obtain standard data;

[0152] The standard data is divided into multiple signals and transmitted to external devices.

[0153] Figure 7 This is a schematic diagram of the structure of the electronic device provided by the present invention, such as... Figure 7 As shown, the electronic device may include a processor 710, a communications interface 720, a memory 730, and a communication bus 740, wherein the processor 710, communications interface 720, and memory 730 communicate with each other via the communication bus 740. The processor 710 can call logical instructions in the memory 730 to execute a data link processing method, which includes: acquiring multiple measurement data from a quantum measurement and control instrument; responding to a data write instruction, determining the data flow direction of each measurement data according to a preset data storage strategy; based on the data flow direction of each measurement data, selecting a target FIFO memory from multiple first-in-first-out FIFO memories to store each measurement data, and writing each measurement data into the corresponding target FIFO memory; responding to a data read instruction, reading the corresponding measurement data from each target FIFO memory; constructing data from each measurement data to obtain multiple target data; and sending the multiple target data to an external device.

[0154] Furthermore, the logical instructions in the aforementioned memory 730 can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, essentially, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0155] On the other hand, the present invention also provides a computer program product, the computer program product including a computer program stored on a non-transitory computer-readable storage medium, the computer program including program instructions, and when the program instructions are executed by a computer, the computer is able to execute the data link processing method provided in the above embodiments, the method including: acquiring multiple measurement data of a quantum measurement and control instrument; in response to a data write instruction, determining the data flow direction of each measurement data according to a preset data storage strategy; based on the data flow direction of each measurement data, selecting a target FIFO memory for storing each measurement data from multiple first-in-first-out FIFO memories, and writing each measurement data into the corresponding target FIFO memory; in response to a data read instruction, reading the corresponding measurement data from each target FIFO memory; constructing data for each measurement data to obtain multiple target data; and sending the multiple target data to an external device.

[0156] In another aspect, the present invention also provides a non-transitory computer-readable storage medium storing a computer program thereon. When executed by a processor, the computer program is implemented to perform the data link processing method provided in the above embodiments. The method includes: acquiring multiple measurement data from a quantum measurement and control instrument; in response to a data write instruction, determining the data flow direction of each measurement data according to a preset data storage strategy; based on the data flow direction of each measurement data, selecting a target FIFO memory for storing each measurement data from multiple first-in-first-out FIFO memories, and writing each measurement data into the corresponding target FIFO memory; in response to a data read instruction, reading the corresponding measurement data from each target FIFO memory; constructing data for each measurement data to obtain multiple target data; and sending the multiple target data to an external device.

[0157] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.

[0158] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.

[0159] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method of data link processing, characterized by, The application is applied to a parallel processor, and comprises: Obtaining a plurality of measurement data of a quantum measurement and control instrument; In response to a data write instruction, determining a data flow direction of each measurement data according to a preset data storage strategy; Based on the data flow direction of each measurement data, selecting a target first-in-first-out (FIFO) memory for storing each measurement data from a plurality of FIFO memories, and writing each measurement data into the corresponding target FIFO memory; In response to a data read instruction, reading the corresponding measurement data from each target FIFO memory; Performing data construction on each measurement data to obtain a plurality of target data; Downlinking the plurality of target data to an external device.

2. The data link processing method of claim 1, wherein, The plurality of FIFO memories at least comprises a first FIFO memory and a second FIFO memory; when determining the data flow direction of each measurement data according to the preset data storage strategy, the following steps are performed for each measurement data: If the first FIFO memory sends a write request signal, it is determined that the measurement data flows to the first FIFO memory; If the first FIFO memory sends a full signal and the second FIFO memory sends a write request signal, it is determined that the measurement data flows to the second FIFO memory; If the first FIFO memory sends a full signal and the second FIFO memory sends a full signal, it is determined that the measurement data does not flow to the first FIFO memory and the second FIFO memory.

3. The data link processing method of claim 2, wherein, The reading of the corresponding measurement data from each target FIFO memory comprises: First, reading the corresponding measurement data from the target FIFO memory belonging to the first FIFO memory; Then, reading the corresponding measurement data from the target FIFO memory belonging to the second FIFO memory.

4. The data link processing method of claim 1, wherein, When performing data construction on each measurement data to obtain a plurality of target data, the following steps are performed for each measurement data: Splitting the measurement data according to a preset bit number as a period to obtain a plurality of split data; Performing data pipeline processing on each split data to obtain a plurality of processing data; Integrating based on the plurality of processing data to obtain target data.

5. The data link processing method of claim 4, wherein, The integration based on the plurality of processing data to obtain target data comprises: Splicing and integrating the plurality of processing data according to the position of each processing data in the original measurement data to obtain integrated data; Splicing the integrated data again at the end of the integrated data to obtain target data.

6. The data link processing method of claim 1, wherein, When downlinking the plurality of target data to an external device, the following steps are performed for each target data: In response to a write request signal sent by a third FIFO memory, writing the target data into the third FIFO memory; In response to a data read instruction, reading the target data from the third FIFO memory; Performing standardization processing on the target data to obtain standard data; Dividing the standard data into a plurality of signals and transmitting to an external device.

7. A data link processing device, characterized by Comprise: An obtaining module is configured to obtain a plurality of measurement data of a quantum measurement and control instrument; A determining module is configured to determine a data flow direction of each measurement data according to a preset data storage strategy in response to a data write instruction; A data writing module is configured to select a target FIFO memory for storing each measurement data from a plurality of FIFO memories based on the data flow direction of each measurement data, and write each measurement data into the corresponding target FIFO memory; A data reading module is configured to read the corresponding measurement data from each target FIFO memory in response to a data read instruction; A data constructing module is configured to perform data construction on each measurement data to obtain a plurality of target data; A data issuing module is configured to issue the plurality of target data to an external device.

8. An apparatus comprising an electronic device, the electronic device comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, wherein, The processor executes the computer program to implement the steps of the data link processing method according to any one of claims 1 to 6.

9. A medium comprising a non-transitory computer-readable storage medium having stored thereon a computer program, characterized in that, The computer program is executed by the processor to implement the steps of the data link processing method according to any one of claims 1 to 6.

10. A product comprising a computer program product comprising a computer program, characterized in that The computer program is executed by the processor to implement the steps of the data link processing method according to any one of claims 1 to 6.

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