Generation method of readable file, intelligent terminal and computer readable storage medium

Abstract

The invention discloses a readable file generation method, an intelligent terminal and a computer readable storage medium. The readable file generation method comprises the steps of obtaining design processing parameters and design processing graphs of a circuit board; the design interlayer via holes and / or the design interlayer groove bodies with the different design machining parameters are / is rendered in the design machining graph by adopting different colors and / or adding different character labels, so that a marked machining graph is obtained; different character name numbers are added to different design processing parameters, and the parameters are stored in a preset two-dimensional array in rows; processing process monitoring parameters and customer acceptance parameters are obtained; adding the processing process monitoring parameters and the customer acceptance parameters into a preset two-dimensional array in rows corresponding to different design processing parameters, so as to render and obtain a quality inspection parameter document; and exporting the marked processing graph and the quality inspection parameter file as a readable file. By means of the scheme, the method for generating the readable file can achieve one-key automatic drawing output, and is simple and easy to expand.

Description

Technical Field

[0001] The present application relates to the technical field of data management, and in particular to a method for generating a readable file, an intelligent terminal, and a computer-readable storage medium. Background Art

[0002] In daily life and industrial production, in order to intuitively display and analyze specific information, software programs can usually be used to process and integrate information to generate readable files, such as PDF (Portable Document Forma, portable file format) files, Word (word processing) files, and any other reasonable readable and writable files. In particular, in the field of packaging substrates, because customers have acceptance requirements for the aperture of vias in circuit boards, the width and length of slots, for example: a group of holes: 200+ / -50um (micrometers), a group of slots: slot width*slot length=>100+ / -50um*2000+ / -50um, if the processed finished product exceeds the upper and lower limits, the product will be scrapped.

[0003] In order to ensure that the finished circuit board meets the customer's size acceptance requirements, on-site quality inspectors need to perform multiple three-dimensional measurements of the hole diameters, slot widths, and slot lengths in the circuit board. However, on-site quality inspectors are usually unable to view the graphic data delivered by the customer, and are unable to compare and inspect the vias and slots on the actual board with the acceptance values. Therefore, the design end personnel are required to produce quality inspection drawings to distinguish and mark vias with different hole diameters and slots with different (slot widths * slot lengths) in the circuit board with different colors to indicate process size monitoring and customer size acceptance, so that on-site quality inspectors can spot check each batch of holes and slots in the circuit board according to the quality inspection drawings, and determine whether the actual size can meet process size monitoring and customer size acceptance.

[0004] However, the existing method of producing quality inspection drawings is usually to manually add process dimension monitoring of holes and slots and customer dimension acceptance to the design drawings. Therefore, the production process is time-consuming and labor-intensive, and prone to errors. When there are too many slots of different (slot width * slot length), the colors are similar and on-site quality inspection cannot effectively distinguish them. Summary of the invention

[0005] The main technical problem solved by the present application is to provide a method for generating a readable file, an intelligent terminal and a computer-readable storage medium, so as to solve the problem that the method for generating a readable file in the prior art requires manual processing, the production process is time-consuming and labor-intensive, and prone to errors and omissions.

[0006] In order to solve the above problems, the first aspect of the present application provides a method for generating a readable file, wherein the method for generating a readable file includes: obtaining the design processing parameters and design processing graphics of the circuit board; in the design processing graphics, using different colors for the design inter-layer vias and / or design inter-layer grooves with different design processing parameters, and / or adding different character labels for rendering to obtain marked processing graphics; adding different character name numbers to different design processing parameters, respectively, and storing them in a preset two-dimensional array in rows; obtaining the processing process monitoring parameters and customer acceptance parameters of the circuit board; adding the processing process monitoring parameters and customer acceptance parameters to the preset two-dimensional array in rows corresponding to different design processing parameters, respectively, to render to obtain a quality inspection parameter document; exporting the marked processing graphics and quality inspection parameter documents as readable files.

[0007] Among them, the step of obtaining the design processing parameters and design processing graphics of the circuit board includes: obtaining the initial design processing parameters and initial design processing graphics of the circuit board; classifying the initial design processing parameters and initial design processing graphics according to the design interlayer distribution and design opening direction of the design interlayer vias and / or design interlayer grooves in the initial design processing graphics, so as to obtain at least two design processing parameters and their corresponding at least two design processing graphics.

[0008] Among them, the design processing parameters include interlayer via parameters and interlayer slot parameters, the colors include a first color and a second color, and in the design processing graphics, different colors are used for the designed interlayer vias and / or designed interlayer slots with different design processing parameters, and / or different character labels are added for rendering to obtain the marked processing graphics. The steps include: in the design processing graphics, different first colors are used for rendering the designed interlayer vias with different interlayer via parameters; different second colors are used for the designed interlayer slots with different interlayer slot parameters, and different character labels are added for rendering to obtain the marked processing graphics.

[0009] Among them, the character labels include a first character label and / or a second character label. In the step of using different colors and / or adding different character labels to render the design interlayer vias and / or design interlayer grooves with different design processing parameters in the design processing graphics to obtain the marked processing graphics, it also includes: obtaining the first midpoint coordinates of the design interlayer vias in the design processing graphics; adding different first character labels at the first midpoint coordinates for rendering; and / or obtaining the second midpoint coordinates of the design interlayer grooves in the design processing graphics; adding different second character labels at the second midpoint coordinates for rendering.

[0010] After the step of obtaining the design processing parameters and the design processing graphics of the circuit board, the method further includes: establishing different drilling tool table serial number indexes for different design processing parameters.

[0011] Among them, after the step of rendering the design inter-layer vias and / or design inter-layer grooves with different design processing parameters in the design processing graphics with different colors and / or adding different character labels to obtain the marked processing graphics, it also includes: establishing a first identification code index link at the design inter-layer vias and / or design inter-layer grooves in the marked processing graphics; wherein the first identification code includes the inter-layer number, name number and dimension marking number.

[0012] Among them, after the step of adding different character name numbers to different design and processing parameters and storing them in a preset two-dimensional array in rows, it also includes: establishing a second identification code index link at the character name number in the preset two-dimensional array; wherein the second identification code includes an inter-layer number, a name number, a dimension number and a coordinate number.

[0013] Among them, after the step of adding the processing process monitoring parameters and customer acceptance parameters corresponding to different design processing parameter branches into a preset two-dimensional array to render a quality inspection parameter document, it also includes: detecting whether the difference between the processing process monitoring parameters and the customer acceptance parameters corresponding to the same design processing parameters is within a set threshold; if the difference is not within the set threshold, issuing an alarm indication.

[0014] In order to solve the above problems, the second aspect of the present application provides an intelligent terminal, wherein the intelligent terminal includes a memory and a processor coupled to each other, the memory stores program data; the processor is used to execute the program data to implement the method for generating a readable file as described in any of the above items.

[0015] In order to solve the above problems, the third aspect of the present application provides a computer-readable storage medium on which program instructions are stored. When the program instructions are executed by a processor, any method for generating a readable file as described above is implemented.

[0016] The beneficial effect of the present invention is as follows: Different from the prior art, the method for generating a readable file provided by the present application obtains the design processing parameters and design processing graphics of the circuit board, so as to render the design interlayer vias and / or design interlayer grooves with different design processing parameters in the design processing graphics with different colors and / or different character labels, obtain the marked processing graphics, and add different character name numbers to different design processing parameters, so as to store them in a preset two-dimensional array in rows, thereby obtaining the processing process monitoring parameters and customer acceptance parameters of the circuit board, adding the processing process monitoring parameters and customer acceptance parameters to the preset two-dimensional array in rows corresponding to different design processing parameters, rendering to obtain the quality inspection parameter document, and exporting the marked processing graphics and the quality inspection parameter document as a readable file, so as to realize one-click automatic drawing by parsing and processing the data, completely eliminating the need for manual operation by personnel, being simple and easy to expand, greatly improving the drawing efficiency of the readable file, and effectively realizing zero error in drawing and zero change in the readable file; and facilitating on-site quality inspectors to distinguish the design interlayer vias and / or design interlayer grooves with different design processing parameters, thereby speeding up the delivery time of the circuit board products. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 It is a flowchart of a first implementation method of a method for generating a readable file of the present application;

[0018] Figure 2 It is a structural schematic diagram of an embodiment of the marking processing figure of the present application;

[0019] Figure 3 yes Figure 1 S11 is a flow chart of an embodiment;

[0020] Figure 4 yes Figure 1 A schematic diagram of the process of an embodiment of S12;

[0021] Figure 5 yes Figure 1 A schematic diagram of a specific embodiment of S12;

[0022] Figure 6 It is a flowchart of a second implementation method of the method for generating a readable file of the present application;

[0023] Figure 7 It is a schematic diagram of a framework of an implementation method of a smart terminal of the present application;

[0024] Figure 8 It is a schematic diagram of a framework of an implementation scheme of a computer-readable storage medium of the present application. DETAILED DESCRIPTION

[0025] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0026] The terms "first", "second" and "third" in this application are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Thus, the features defined as "first", "second" and "third" can explicitly or implicitly include at least one of the features. In the description of this application, the meaning of "multiple" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined. All directional indications (such as up, down, left, right, front, back...) in the implementation mode of this application are only used to explain the relative position relationship, movement, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication also changes accordingly. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but optionally also includes steps or units that are not listed, or optionally also includes other steps or units inherent to these processes, methods, products or devices.

[0027] Reference to "embodiment" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiment may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0028] The present application is described in detail below with reference to the accompanying drawings and implementation methods.

[0029] See also Figure 1 , Figure 1 This is a flowchart of the first implementation method of the method for generating a readable file of the present application. Specifically, it may include the following steps:

[0030] S11: Obtain design processing parameters and design processing graphics of the circuit board.

[0031] Among them, the method for generating a readable file in this embodiment can be specifically understood as a method in which the design software running in an intelligent terminal, such as a computer, server or smart phone, or any other reasonable terminal device with program processing function, uses the original design data of the circuit board and / or the graphic data delivered by the customer to generate a reference file for on-site quality inspectors to conduct quality inspection.

[0032] Specifically, the smart terminal can also be understood as a software platform that receives user uploads, or directly obtains the original design data of the circuit board and / or the graphic data delivered by the customer from the local database, so as to parse, classify and process the data to obtain the design processing parameters and design processing graphics.

[0033] It is worth explaining that the design processing parameters refer to the theoretical processing parameters designed and adopted by the circuit board designer in any reasonable processing flow such as drilling, grooving, etching, electroplating, etc. between the core boards in the circuit board in order to realize the design circuit logic, such as the theoretical design parameters such as the aperture of the interlayer via, the length and width of the interlayer groove, and the etching depth; the design processing graphics refer to the structural schematic diagrams used to indicate one or more of the reasonable processing positions of the circuit board, or any one or more layers of the core boards in the circuit board, such as the hole position, grooving position, routing position, component embedding position, etc.

[0034] In addition, the software platform can be understood as software for processing graphic data, or any reasonable application software program such as circuit board design software, and this application does not limit this.

[0035] S12: in the design processing graph, different colors are used for the design inter-layer vias and / or the design inter-layer slots with different design processing parameters, and / or different character labels are added for rendering to obtain a marked processing graph.

[0036] Among them, Figure 2 As shown, Figure 2 It is a structural schematic diagram of an embodiment of the marked processing graphics of the present application. The marked processing graphics can be specifically understood as a structural schematic diagram for indicating the opening position and the slot position obtained after the circuit board 20 or any one or more layers of the core board in the circuit board 20 are specifically marked. The designed interlayer via 21 in the circuit board 20 can specifically include a first via 211, a second via 212, and a third via 213, and the designed interlayer slot body 22 can include a first slot body 221, a second slot body 222, a third slot body 223, and a fourth slot body 224; and the apertures of the first via 211, the second via 212, and the third via 213 are different, and the length and width of the first slot body 221, the second slot body 222, the third slot body 223, and the fourth slot body 224 are different. In order to facilitate the size comparison in the subsequent quality inspection, it is necessary to make a distinction.

[0037] Specifically, based on the design processing pattern, the software platform sequentially locates each design interlayer via 21 and / or each design interlayer slot 22 in the design processing pattern, so as to sequentially process each design interlayer via 21 and / or each design interlayer slot with different design processing parameters, such as Figure 2 The first via hole 211 , the second via hole 212 , the third via hole 213 , the first slot body 221 , the second slot body 222 , the third slot body 223 and the fourth slot body 224 are rendered in different colors to obtain a marked processing pattern.

[0038] It is worth noting that the number of the first vias 211 can be one or more, and when the number of the first vias 211 is multiple, the software platform specifically uses the same color to render each first via 211 in the designed processing figure; similarly, when the number of the second vias 212, the third vias 213, the first slot 221, the second slot 222, the third slot 223 or the fourth slot 224 is multiple, the software platform can also use the same color to render each second via 212, the third via 213, the first slot 221, the second slot 222, the third slot 223 or the fourth slot 224 in the designed processing figure; but the rendering colors of the first via 211, the second via 212, the third via 213, the first slot 221, the second slot 222, the third slot 223 and the fourth slot 224 are different, or different vias use different colors, different slots use different colors, but the vias and the slots can share the same color.

[0039] In other embodiments, the circuit board 20 may include any reasonable number of vias, such as 1, 2 or 5, and / or any reasonable number of slots, such as 1, 2 or 5, and the present application does not impose any limitation on this.

[0040] In another embodiment, the software platform can also specifically add different character labels for rendering the design inter-layer vias 21 and / or design inter-layer slots 22 with different design processing parameters, that is, the first via 211, the second via 212, the third via 213, the first slot 221, the second slot 222, the third slot 223 and the fourth slot 224 in the design processing graphics; or, while rendering with different colors, add different character labels to render the first via 211, the second via 212, the third via 213, the first slot 221, the second slot 222, the third slot 223 and the fourth slot 224 to obtain a labeled processing graphics, which is not limited to the present application.

[0041] In a specific embodiment, the first via 211, the second via 212 and the third via 213 in the marked processing figure can be rendered by red, green, yellow, and / or adding a, b, c respectively; and the first slot body 221, the second slot body 222, the third slot body 223 and the fourth slot body 224 can be rendered by orange, gray, white, blue, and / or adding 1, 2, 3, 4 respectively.

[0042] In other embodiments, the character labels corresponding to different design layer vias 21 and design layer slots 22 may be English letters or Arabic numerals, or may be one or more of any other reasonable different types of characters such as Roman numerals, Latin letters, Chinese characters, etc., and the present application does not limit this.

[0043] S13: adding different character name numbers to different design processing parameters respectively, and storing them in a preset two-dimensional array in rows.

[0044] Specifically, the software platform classifies the currently acquired design and processing parameters to correspond to different design and processing parameters, such as 100, 80, 90*250, 90*1100, etc., and adds different character name numbers, a first via (aperture), b second via (aperture), 1 first slot (width*length), 1 first slot (width*length), 3 third slot (width*length), etc., and stores them in rows in a preset two-dimensional array. That is, different design and processing parameters are added with different character name numbers and stored in different rows in the preset two-dimensional array to facilitate subsequent distinction and interpretation.

[0045] It is worth mentioning that an array (one-dimensional array) refers to a structure used to store multiple data of the same type. Two-dimensional array: An array containing two dimensions, which can be regarded as a table in which each row is a one-dimensional array.

[0046] In other embodiments, the character name number may specifically include one or more of any reasonable different types of characters such as Chinese characters, English letters, Arabic numerals, Roman numerals, Latin letters, etc., and this application does not limit this.

[0047] S14: Obtaining the processing monitoring parameters and customer acceptance parameters of the circuit board.

[0048] Furthermore, the software platform obtains processing monitoring parameters and customer acceptance parameters that are locally stored, uploaded by users, or sent by circuit board manufacturing and testing equipment.

[0049] It is worth noting that the processing monitoring parameters refer to the actual measurement parameters obtained by three-dimensional measurement and monitoring of any reasonable processing dimensions in the circuit board during the production process, such as the aperture of a via and / or the length and width of a slot. Among them, the three-dimensional measurement, also known as three-dimensional measurement or three-dimensional scanning, is a technology used to measure the size and shape of an object.

[0050] In addition, the customer acceptance parameters refer to the various size requirements of the customer for the finished circuit board.

[0051] S15: Add the processing monitoring parameters and the customer acceptance parameters corresponding to different design processing parameter branches into the preset two-dimensional array to render and obtain the quality inspection parameter document.

[0052] Furthermore, the currently acquired processing monitoring parameters and customer acceptance parameters are added to the preset two-dimensional array in corresponding rows to different design processing parameters. That is, the processing monitoring parameters and customer acceptance parameters are added to different rows of the preset two-dimensional array in corresponding rows to different design processing parameters, and correspond to different character name numbers to render a quality inspection parameter document.

[0053] For ease of understanding, as shown in Table 1 below, the processing process monitoring parameters may specifically include etching window process monitoring parameters, laser drilling process monitoring parameters, and electroplating finished product parameters. Table 1 can be understood as a preset two-dimensional array. Among them, different character name numbers are added to correspond to different design processing parameters, such as 100, 60, 90*250, 90*1100, etc., that is, a first via (aperture), b second via (aperture), 1 first slot (width * length), 3 third slot (width * length), etc., and are stored in the preset two-dimensional array in rows, and then the etching window process monitoring parameters, that is, 95+ / -7, 75+ / -7, (85+ / -7)*(245+ / -30), (85+ / -7)*(1095+ / -30), etc., and the laser drilling process monitoring parameters, that is, 100+ / -7, 80+ / -7, (90*250)+ / -7, (90*1100)+ / -7, etc., electroplating finished product parameters, i.e. 100+ / -50, 80+ / -50, (90*250)+ / -50, (90*1100)+ / -50, etc., and customer acceptance parameters, i.e. 100+ / -50, 80+ / -50, (90*250)+ / -50, (90*1100)+ / -50, etc., are added to the preset two-dimensional array in rows corresponding to different design and processing parameters, and after adding the corresponding project names, the quality inspection parameter document is rendered.

[0054] Table 1

[0055]

[0056] In other embodiments, when the number of designed inter-layer vias and / or designed inter-layer slots in the circuit board is any other reasonable number, the preset two-dimensional array may specifically have 1 row, 3 rows, 10 rows, or any other reasonable number of rows, and each via and slot may specifically correspond to any other reasonable character name number; the processing process monitoring parameters may specifically include one or two of the etching window opening process monitoring parameters, the laser drilling process monitoring parameters, and the electroplating finished product parameters, or further include any other reasonable parameters actually measured and monitored during the processing process, such as the drilling and washing process monitoring parameters, and the present application does not limit this.

[0057] It is worth noting that in Figure 2 When the annotated processing graphics specifically correspond to the graphics after the design processing graphics of any one or more layers of the core board of the circuit board are specifically annotated, the number of the design processing graphics and their corresponding annotated processing graphics can also specifically correspond to multiple. For example, when the circuit board is specifically a 4-layer board, the design processing graphics and its corresponding annotated processing graphics can also include one or more of the interlayer design processing graphics and their corresponding interlayer annotated processing graphics between every two core boards, such as the first layer core board and the second layer core board d12 of the circuit board, the fourth layer core board and the third layer core board d43 of the circuit board, the second layer core board and the third layer core board d23 of the circuit board, etc., and the present application does not limit this.

[0058] S16: Export the marked processing graphics and quality inspection parameter documents as readable files.

[0059] Specifically, the annotated processing graphics and their corresponding quality inspection parameter documents are laid out and exported as readable files, such as PDF files, Word files, or any other reasonable readable and writable files, to be displayed to users for quality inspection and comparison. This application does not limit this.

[0060] The above solution realizes one-click automatic drawing by parsing and processing the data. It does not require manual operation and is simple and easy to expand. It greatly improves the efficiency of drawing readable files and effectively achieves zero errors in drawing and zero changes in readable files. It is also convenient for on-site quality inspectors to distinguish between design layer vias and / or design layer grooves with different design processing parameters, thereby speeding up the delivery time of circuit board products.

[0061] Furthermore, in one embodiment, after the above S11, it specifically includes: establishing different drilling tool table serial number indexes for different design processing parameters.

[0062] Specifically, a mapping relationship between each design processing parameter and the drilling tool table serial number is established in the software platform, and a unique matching index is established in the software platform to facilitate subsequent retrieval of the corresponding drilling tool table serial number according to the design processing parameter.

[0063] When the aperture of the designed interlayer via hole is the same as the slot width of the designed interlayer slot body, they will correspond to the same drilling tool table number.

[0064] Furthermore, in one embodiment, after the above S12, it specifically includes: establishing a first identification code index link at the designed inter-layer via hole and / or the designed inter-layer groove in the marked processing graphic.

[0065] The first identification code includes a layer number, a name number and a dimension number.

[0066] It is understandable that when there are multiple inter-layer vias and inter-layer slots in the design processing graphics, in order to facilitate subsequent comparison and identification, it is necessary to establish an identification code for each inter-layer via and each inter-layer slot.

[0067] To facilitate identification and distinction, the software platform can specifically encode information such as design processing parameters, design layer distribution, and design opening direction of each design layer via and each design layer slot. For example, when a via with a diameter of 80, a via with a diameter of 90, a via with a diameter of 100, a slot with a slot width*slot length of 100*2000, and a slot with a slot width*slot length of 100*2500 are provided between the first core board and the second core board of the circuit board, the first identification code will be established: d12_hole_80, d12_hole_90, d12_hole_100, d12_slot_100*2000, d12_slot_100*2500.

[0068] Among them, d12 is the inter-layer number, corresponding to the design inter-layer distribution and the design opening direction; the hole and slot are the name numbers, representing the via and the slot respectively; the 80, 90, 100, 100*2000, 100*2500 are the dimension marking numbers.

[0069] Furthermore, in other embodiments, the first identification code may specifically include a unique character identification number to facilitate subsequent identification of the designed inter-layer vias and / or designed inter-layer slots having the same design processing parameters.

[0070] It is understandable that the annotated processing graphic can also be specifically displayed on the display interface of the software platform, so that when an index link with a first identification code is established at the design layer via and / or the design layer slot in the annotated processing graphic, the user can display the first identification code by clicking on the index link to identify the design processing parameters, design layer distribution and other information of each design layer via and / or design layer slot.

[0071] Furthermore, in one embodiment, after the above S13, it specifically includes: establishing a second identification code index link at the character name number in the preset two-dimensional array.

[0072] The second identification code includes a layer number, a name number, a dimension number and a coordinate number.

[0073] Similarly, the preset two-dimensional array can also be displayed on the display interface of the software platform, so that an index link of a second identification code can be established at each character name number in the preset two-dimensional array, so that the user can display the second identification code by clicking on the index link to identify the design processing parameters of the vias between design layers and / or the slots between design layers, the distribution between design layers and other information.

[0074] It is worth noting that the coordinate number can specifically be the midpoint coordinates of each design layer via and / or design layer slot in the annotated processing figure, and can be understood as a unique character identification number; and when multiple design layer vias or design layer slots have the same design processing parameters, the character name number corresponding to the design processing parameters will correspond to multiple second identification codes, that is, when clicking the index link at the character name number, multiple second identification codes will pop up.

[0075] In other embodiments, the index link of the second identification code may also be specifically established at each design processing parameter in the preset two-dimensional array, or at the customer acceptance parameter, which is not limited in the present application.

[0076] Furthermore, in one embodiment, after the above S15, it specifically includes: displaying the design processing graphics and the quality inspection parameter document on the display interface of the software platform.

[0077] Furthermore, in one embodiment, after the above S16, it specifically includes: a pop-up window asks the user whether to open or print the readable file, and after the user clicks OK, the readable file is automatically opened or printed for the user to check whether the readable file is generated correctly.

[0078] See also Figure 3 , Figure 3 yes Figure 1In one embodiment, the method for generating a readable file of the present application further includes some more specific steps in addition to the above S11-S16. Specifically, the above S11 may further include the following steps:

[0079] S111: Acquire initial design processing parameters and initial design processing graphics of the circuit board.

[0080] Specifically, the software platform receives information uploaded by users, or directly obtains initial design and processing parameters and initial design and processing graphics of the circuit board from a local database.

[0081] The initial design processing pattern may specifically correspond to the overall design drawing of the circuit board, or the decomposed interlayer design drawing obtained by splitting each core board layer corresponding to each design processing parameter. For example, in a circuit board with a four-layer core board, the initial design processing pattern may specifically include d12, d43, d23, sca23, scb23, d13, d32, sca32, scb32.

[0082] It is worth mentioning that d12 refers to the decomposed interlayer design drawing showing the vias opened from the first core board to the second core board; similarly, d23 refers to the decomposed interlayer design drawing showing the vias opened from the second core board to the third core board; sca23 refers to the decomposed interlayer design drawing showing the first slot body opened from the second core board to the third core board; scb23 refers to the decomposed interlayer design drawing showing the second slot body opened from the second core board to the third core board, and the length and width of the second slot body are different from those of the first slot body; it should be specially noted that d32 refers to the decomposed interlayer design drawing showing the vias opened from the third core board to the second core board, which is different from d23; and by analogy, the reference meanings of d43, d13, sca32, and scb32 can be obtained, which will not be repeated here.

[0083] S112: Classifying the initial design processing parameters and the initial design processing graphics according to the design interlayer distribution and design opening direction of the design interlayer vias and / or design interlayer slots in the initial design processing graphics, so as to obtain at least two design processing parameters and their corresponding at least two design processing graphics.

[0084] Furthermore, the specific method is to integrate, analyze, classify and process the initial design processing parameters and the initial design processing graphics according to the design interlayer distribution and design opening direction of each design interlayer via and / or each design interlayer slot in the initial design processing graphics to obtain at least two design processing parameters and their corresponding at least two design processing graphics.

[0085] For example, d23, sca23, and scb23 are combined to obtain the designed processing figure d23+++; d32, sca32, and scb32 are combined to obtain the designed processing figure d32+++; d12, d43, and d13 are equivalent to the designed processing figures d12+++, d43+++, and d13+++, respectively.

[0086] It is understandable that the software platform can specifically use d12+++ to obtain the marked processing graphics and their corresponding quality inspection parameter documents, as mentioned above Figure 2 As described in Table 1, and the Figure 2 And Table 1 can specifically constitute one page of the readable file, such as the specific display content of the first page; and the software platform can also specifically use d43+++, d23+++, d32+++, and d13+++ in sequence to obtain other annotated processing graphics and their corresponding quality inspection parameter documents, and in turn constitute the specific display content of the second, third, fourth, and fifth pages of the readable file, which will not be repeated here.

[0087] See also Figure 4 , Figure 4 yes Figure 1 In one embodiment, the method for generating a readable file of the present application further includes some more specific steps in addition to the above S11-S16. Specifically, in the above S12, the following steps may be included:

[0088] S121: In the design processing graph, the designed inter-layer vias with different inter-layer via parameters are rendered using different first colors respectively.

[0089] The design processing parameters include interlayer via parameters and interlayer slot parameters, and the color includes a first color and a second color.

[0090] Specifically, Figure 2 As shown, Figure 2 What is shown can be understood as a software platform that can specifically utilize the annotated processing graphics obtained by d12+++, so that on the basis of the d12+++ design processing graphics, each designed interlayer via 21 with different interlayer via parameters is rendered using a different first color, for example, the first via 211, the second via 212, and the third via 213 are rendered using red, green, and yellow, respectively.

[0091] S122: using different second colors for the designed interlayer slots with different interlayer slot parameters, and adding different character labels for rendering to obtain a marked processing graphic.

[0092] Furthermore, on the basis of the design processing graphics, different second colors are used for the designed interlayer slots 22 with different interlayer slot parameters. For example, orange, gray, white and blue are used for the first slot 221, the second slot 222, the third slot 223 and the fourth slot 224 respectively, and different character labels such as 1, 2, 3, 4 are added for rendering to obtain the marked processing graphics.

[0093] In other embodiments, the character labels corresponding to different design layer vias 21 and design layer slots 22 may be English letters or Arabic numerals, or may be one or more of any other reasonable different types of characters such as Roman numerals, Latin letters, Chinese characters, etc.; the second color may be the same as the first color or different, and the present application does not limit this.

[0094] See also Figure 5 , Figure 5 yes Figure 1 A schematic diagram of a flow chart of a specific embodiment of S12 in FIG.

[0095] Specifically, in one embodiment, in the above S12, the following steps may be further included:

[0096] S1211: Obtain the first midpoint coordinates of the designed inter-layer via in the designed processing graphic.

[0097] The character label includes a first character label and / or a second character label.

[0098] Specifically, Figure 2 As shown, Figure 2 The software platform shown can be specifically understood as a marked processing graphic obtained by using d12+++, and the software platform can specifically obtain the first midpoint coordinates of each designed inter-layer via 21 in the designed processing graphic.

[0099] S1212: Add different first character labels at the first midpoint coordinates for rendering.

[0100] Furthermore, different first character labels are added to the first midpoint coordinates of each design interlayer via 21 in the design processing figure for rendering, for example, a, b, and c are added to the first midpoint coordinates of the first via 211, the second via 212, and the third via 213 for rendering.

[0101] S1213: Obtain the second midpoint coordinates of the designed interlayer groove in the designed processing graphic.

[0102] Similarly, the second midpoint coordinates of each designed interlayer slot 22 in the designed processing pattern are obtained.

[0103] S1214: Add a different second character label at the second midpoint coordinate for rendering.

[0104] Different second character labels are added to the second midpoint coordinates of the slot 22 between each design layer in the design processing figure for rendering. For example, 1, 2, 3, and 4 are added to the second midpoint coordinates of the first slot 221, the second slot 222, the third slot 223, and the fourth slot 224 for rendering.

[0105] It is understandable that the first character label and the second character label can be the same or different, and can also be one or more of any other reasonable different types of characters such as Roman numerals, Latin letters, Chinese characters, etc., and this application does not limit this.

[0106] See also Figure 6 , Figure 6 : is a flow chart of the second embodiment of the method for generating a readable file of the present application. The method for generating a readable file of this embodiment is Figure 1 A flowchart of a detailed embodiment of a method for generating a readable file in the embodiment of the present invention comprises the following steps:

[0107] S31: Obtain design processing parameters and design processing graphics of the circuit board.

[0108] S32: using different colors and / or adding different character labels to render the design inter-layer vias and / or the design inter-layer slots with different design processing parameters in the design processing graph, so as to obtain a marked processing graph.

[0109] S33: adding different character name numbers to different design processing parameters respectively, and storing them in a preset two-dimensional array in rows.

[0110] S34: Obtaining the processing monitoring parameters and customer acceptance parameters of the circuit board.

[0111] S35: Add the processing monitoring parameters and the customer acceptance parameters corresponding to different design processing parameter branches into the preset two-dimensional array to render and obtain the quality inspection parameter document.

[0112] S36: Export the marked processing graphics and quality inspection parameter documents as readable files.

[0113] Among them, S31, S32, S33, S34, S35 and S36 are Figure 1 S11, S12, S13, S14, S15 and S16 are the same. Please refer to S11, S12, S13, S14, S15 and S16 and their related text descriptions for details, which will not be repeated here.

[0114] S37: Detect whether the difference between the processing monitoring parameter and the customer acceptance parameter corresponding to the same design processing parameter is within a set threshold.

[0115] Specifically, the software platform can also automatically compare the processing process monitoring parameters corresponding to the same design processing parameters in the preset two-dimensional array with the customer acceptance parameters to detect whether the difference between the two is within the set threshold, that is, to detect whether the processing process monitoring parameters meet the customer acceptance requirements.

[0116] If the difference is within the set threshold, S38 is executed; if the difference is not within the set threshold, S39 is executed.

[0117] S38: Acceptance passed.

[0118] It can be understood that when it is determined that the difference between the processing monitoring parameters corresponding to the same design processing parameters and the customer acceptance parameters is within the set threshold, it indicates that the design inter-layer vias and / or design inter-layer grooves in the currently processed circuit board meet the customer acceptance requirements, that is, the acceptance is qualified.

[0119] S39: If the difference is not within the set threshold, an alarm indication is issued.

[0120] If the difference between the processing monitoring parameters and the customer acceptance parameters corresponding to the same design processing parameters is not within the set threshold, it indicates that the vias between the design layers and / or the grooves between the design layers in the currently processed circuit board do not meet the customer acceptance requirements, and an audible and visual alarm indication must be issued, or an alarm window must be popped up to remind the user that defective products have occurred.

[0121] See also Figure 7 , Figure 7 Schematic diagram of a framework of an embodiment of the smart terminal of the present application. In this embodiment, the smart terminal 40 includes a memory 41 and a processor 42 coupled to each other, and the processor 42 is used to execute program instructions stored in the memory 41 to implement the steps of any of the above-mentioned embodiments of the method for generating a readable file.

[0122] In a specific implementation scenario, the smart terminal 40 may include but is not limited to: monitoring equipment, drones, mobile phones, tablet computers, and any other reasonable terminal devices that include flash memory and have data storage scenarios with multiple data sources. This application does not limit this.

[0123] Specifically, the processor 42 is used to control itself and the memory 41 to implement the steps of any of the above-mentioned video display method embodiments. The processor 42 can also be called a CPU (Central Processing Unit). The processor 42 may be an integrated circuit chip with signal processing capabilities. The processor 42 can also be a general-purpose processor, a digital signal processor (Digital Signal Processor, DSP), an application-specific integrated circuit (Application Specific Integrated Circuit, ASIC), a field-programmable gate array (Field-Programmable Gate Array, FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components. The general-purpose processor can be a microprocessor or the processor 42 can also be any conventional processor, etc. In addition, the processor 42 can be implemented by an integrated circuit chip.

[0124] See also Figure 8 , Figure 8 It is a schematic diagram of a framework of an embodiment of a computer-readable storage medium of the present application. In this embodiment, the computer-readable storage medium 50 stores program instructions 51 that can be executed by a processor, and the program instructions 51 are used to implement the steps of any of the above-mentioned embodiments of the method for generating a readable file.

[0125] In the several embodiments provided in the present application, it should be understood that the disclosed methods and devices can be implemented in other ways. For example, the device implementation described above is only schematic. For example, the division of modules or units is only a logical function division. There may be other division methods in actual implementation, such as units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, and the indirect coupling or communication connection of devices or units can be electrical, mechanical or other forms.

[0126] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the present embodiment.

[0127] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0128] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions to enable a computer device (which can be a personal computer, server, or network device, etc.) or a processor (processor) to perform all or part of the steps of each implementation method of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk and other media that can store program code.

Claims

1. A method for generating a readable file, applied to process dimension monitoring of a circuit board, characterized in that: The generation of the readable file includes: Obtaining design processing parameters and design processing graphics of the circuit board; In the design processing graph, different colors are used for the design interlayer vias and / or the design interlayer slots with different design processing parameters, and / or different character labels are added for rendering to obtain a marked processing graph; Add different character name numbers to different design processing parameters respectively, so as to store them in a preset two-dimensional array in rows; Obtaining processing monitoring parameters and customer acceptance parameters of the circuit board; Adding the processing monitoring parameters and the customer acceptance parameters corresponding to different design processing parameter branches to the preset two-dimensional array to render and obtain a quality inspection parameter document; The annotated processing graphics and the quality inspection parameter document are exported as readable files.

2. The method for generating a readable file according to claim 1, characterized in that: The step of obtaining the design processing parameters and design processing graphics of the circuit board includes: Obtaining initial design processing parameters and initial design processing graphics of the circuit board; The initial design processing parameters and the initial design processing graphics are classified according to the design interlayer distribution and design opening direction of the design interlayer vias and / or the design interlayer grooves in the initial design processing graphics to obtain at least two of the design processing parameters and their corresponding at least two design processing graphics.

3. The method for generating a readable file according to claim 1, characterized in that: The design processing parameters include interlayer via parameters and interlayer slot parameters, the colors include a first color and a second color, and the steps of using different colors and / or adding different character labels to render the designed interlayer vias and / or the designed interlayer slots with different design processing parameters in the designed processing graphics to obtain the marked processing graphics include: In the designed processing graph, the designed interlayer vias with different interlayer via parameters are rendered using different first colors respectively; Different second colors are used for the designed interlayer slots with different interlayer slot parameters, and different character labels are added for rendering to obtain the marked processing graphics.

4. The method for generating a readable file according to claim 1, characterized in that: The character labels include a first character label and / or a second character label, and in the step of rendering the design interlayer vias and / or the design interlayer slots with different design processing parameters in the design processing graph using different colors and / or adding different character labels to obtain the marked processing graph, the step further includes: Obtaining the first midpoint coordinates of the designed inter-layer via in the designed processing graph; Adding different first character labels at the first midpoint coordinates for rendering; and / or, obtaining the coordinates of the second midpoint of the designed interlayer groove in the designed processing figure; A different second character label is added at the second midpoint coordinate for rendering.

5. The method for generating a readable file according to claim 1, characterized in that: After the step of obtaining the design processing parameters and design processing graphics of the circuit board, the method further includes: Different drilling tool table serial number indexes are established for different design processing parameters.

6. The method for generating a readable file according to claim 1, characterized in that: After the step of rendering the designed interlayer vias and / or designed interlayer slots with different designed processing parameters in the designed processing graph using different colors and / or adding different character labels to obtain the marked processing graph, the step further includes: A first identification code index link is established at the designed inter-layer via and / or the designed inter-layer slot in the annotated processing graphic; wherein the first identification code includes an inter-layer number, a name number, and a dimension marking number.

7. The method for generating a readable file according to claim 1, characterized in that: After the step of adding different character name numbers to the different design processing parameters to store them in a preset two-dimensional array in rows, the method further includes: A second identification code index link is established at the character name number in the preset two-dimensional array; wherein the second identification code includes a layer number, a name number, a dimension number and a coordinate number.

8. The method for generating a readable file according to claim 1, characterized in that: After the step of adding the processing monitoring parameters and the customer acceptance parameters to the preset two-dimensional array corresponding to different design processing parameter branches to render and obtain a quality inspection parameter document, the method further includes: Detecting whether the difference between the processing monitoring parameter and the customer acceptance parameter corresponding to the same design processing parameter is within a set threshold; If the difference is not within the set threshold, an alarm indication is issued.

9. An intelligent terminal, characterized in that: The intelligent terminal includes a memory and a processor coupled to each other; The memory stores program data; The processor is used to execute the program data to implement the method for generating a readable file according to any one of claims 1 to 8.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores program data, and the program data can be executed to implement the method for generating a readable file according to any one of claims 1 to 8.

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